
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:17:59 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_23808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:71424*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71424*0 + 3*0*FLEN/8, x4, x1, x2)

inst_23809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:71427*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71427*0 + 3*1*FLEN/8, x4, x1, x2)

inst_23810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:71430*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71430*0 + 3*2*FLEN/8, x4, x1, x2)

inst_23811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:71433*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71433*0 + 3*3*FLEN/8, x4, x1, x2)

inst_23812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:71436*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71436*0 + 3*4*FLEN/8, x4, x1, x2)

inst_23813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:71439*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71439*0 + 3*5*FLEN/8, x4, x1, x2)

inst_23814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b0823 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x45b5b0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb0823; op2val:0x8045b5b0;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:71442*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71442*0 + 3*6*FLEN/8, x4, x1, x2)

inst_23815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:71445*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71445*0 + 3*7*FLEN/8, x4, x1, x2)

inst_23816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:71448*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71448*0 + 3*8*FLEN/8, x4, x1, x2)

inst_23817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:71451*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71451*0 + 3*9*FLEN/8, x4, x1, x2)

inst_23818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:71454*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71454*0 + 3*10*FLEN/8, x4, x1, x2)

inst_23819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:71457*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71457*0 + 3*11*FLEN/8, x4, x1, x2)

inst_23820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:71460*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71460*0 + 3*12*FLEN/8, x4, x1, x2)

inst_23821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:71463*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71463*0 + 3*13*FLEN/8, x4, x1, x2)

inst_23822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:71466*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71466*0 + 3*14*FLEN/8, x4, x1, x2)

inst_23823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:71469*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71469*0 + 3*15*FLEN/8, x4, x1, x2)

inst_23824:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:71472*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71472*0 + 3*16*FLEN/8, x4, x1, x2)

inst_23825:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:71475*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71475*0 + 3*17*FLEN/8, x4, x1, x2)

inst_23826:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:71478*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71478*0 + 3*18*FLEN/8, x4, x1, x2)

inst_23827:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:71481*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71481*0 + 3*19*FLEN/8, x4, x1, x2)

inst_23828:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:71484*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71484*0 + 3*20*FLEN/8, x4, x1, x2)

inst_23829:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:71487*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71487*0 + 3*21*FLEN/8, x4, x1, x2)

inst_23830:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:71490*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71490*0 + 3*22*FLEN/8, x4, x1, x2)

inst_23831:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7800000; valaddr_reg:x3; val_offset:71493*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71493*0 + 3*23*FLEN/8, x4, x1, x2)

inst_23832:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7800001; valaddr_reg:x3; val_offset:71496*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71496*0 + 3*24*FLEN/8, x4, x1, x2)

inst_23833:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7800003; valaddr_reg:x3; val_offset:71499*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71499*0 + 3*25*FLEN/8, x4, x1, x2)

inst_23834:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7800007; valaddr_reg:x3; val_offset:71502*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71502*0 + 3*26*FLEN/8, x4, x1, x2)

inst_23835:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x780000f; valaddr_reg:x3; val_offset:71505*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71505*0 + 3*27*FLEN/8, x4, x1, x2)

inst_23836:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x780001f; valaddr_reg:x3; val_offset:71508*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71508*0 + 3*28*FLEN/8, x4, x1, x2)

inst_23837:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x780003f; valaddr_reg:x3; val_offset:71511*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71511*0 + 3*29*FLEN/8, x4, x1, x2)

inst_23838:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x780007f; valaddr_reg:x3; val_offset:71514*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71514*0 + 3*30*FLEN/8, x4, x1, x2)

inst_23839:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x78000ff; valaddr_reg:x3; val_offset:71517*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71517*0 + 3*31*FLEN/8, x4, x1, x2)

inst_23840:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x78001ff; valaddr_reg:x3; val_offset:71520*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71520*0 + 3*32*FLEN/8, x4, x1, x2)

inst_23841:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x78003ff; valaddr_reg:x3; val_offset:71523*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71523*0 + 3*33*FLEN/8, x4, x1, x2)

inst_23842:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x78007ff; valaddr_reg:x3; val_offset:71526*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71526*0 + 3*34*FLEN/8, x4, x1, x2)

inst_23843:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7800fff; valaddr_reg:x3; val_offset:71529*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71529*0 + 3*35*FLEN/8, x4, x1, x2)

inst_23844:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7801fff; valaddr_reg:x3; val_offset:71532*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71532*0 + 3*36*FLEN/8, x4, x1, x2)

inst_23845:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7803fff; valaddr_reg:x3; val_offset:71535*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71535*0 + 3*37*FLEN/8, x4, x1, x2)

inst_23846:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7807fff; valaddr_reg:x3; val_offset:71538*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71538*0 + 3*38*FLEN/8, x4, x1, x2)

inst_23847:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x780ffff; valaddr_reg:x3; val_offset:71541*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71541*0 + 3*39*FLEN/8, x4, x1, x2)

inst_23848:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x781ffff; valaddr_reg:x3; val_offset:71544*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71544*0 + 3*40*FLEN/8, x4, x1, x2)

inst_23849:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x783ffff; valaddr_reg:x3; val_offset:71547*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71547*0 + 3*41*FLEN/8, x4, x1, x2)

inst_23850:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x787ffff; valaddr_reg:x3; val_offset:71550*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71550*0 + 3*42*FLEN/8, x4, x1, x2)

inst_23851:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x78fffff; valaddr_reg:x3; val_offset:71553*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71553*0 + 3*43*FLEN/8, x4, x1, x2)

inst_23852:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x79fffff; valaddr_reg:x3; val_offset:71556*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71556*0 + 3*44*FLEN/8, x4, x1, x2)

inst_23853:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7bfffff; valaddr_reg:x3; val_offset:71559*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71559*0 + 3*45*FLEN/8, x4, x1, x2)

inst_23854:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7c00000; valaddr_reg:x3; val_offset:71562*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71562*0 + 3*46*FLEN/8, x4, x1, x2)

inst_23855:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7e00000; valaddr_reg:x3; val_offset:71565*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71565*0 + 3*47*FLEN/8, x4, x1, x2)

inst_23856:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7f00000; valaddr_reg:x3; val_offset:71568*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71568*0 + 3*48*FLEN/8, x4, x1, x2)

inst_23857:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7f80000; valaddr_reg:x3; val_offset:71571*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71571*0 + 3*49*FLEN/8, x4, x1, x2)

inst_23858:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fc0000; valaddr_reg:x3; val_offset:71574*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71574*0 + 3*50*FLEN/8, x4, x1, x2)

inst_23859:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fe0000; valaddr_reg:x3; val_offset:71577*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71577*0 + 3*51*FLEN/8, x4, x1, x2)

inst_23860:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ff0000; valaddr_reg:x3; val_offset:71580*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71580*0 + 3*52*FLEN/8, x4, x1, x2)

inst_23861:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ff8000; valaddr_reg:x3; val_offset:71583*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71583*0 + 3*53*FLEN/8, x4, x1, x2)

inst_23862:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffc000; valaddr_reg:x3; val_offset:71586*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71586*0 + 3*54*FLEN/8, x4, x1, x2)

inst_23863:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffe000; valaddr_reg:x3; val_offset:71589*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71589*0 + 3*55*FLEN/8, x4, x1, x2)

inst_23864:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fff000; valaddr_reg:x3; val_offset:71592*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71592*0 + 3*56*FLEN/8, x4, x1, x2)

inst_23865:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fff800; valaddr_reg:x3; val_offset:71595*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71595*0 + 3*57*FLEN/8, x4, x1, x2)

inst_23866:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fffc00; valaddr_reg:x3; val_offset:71598*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71598*0 + 3*58*FLEN/8, x4, x1, x2)

inst_23867:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fffe00; valaddr_reg:x3; val_offset:71601*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71601*0 + 3*59*FLEN/8, x4, x1, x2)

inst_23868:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffff00; valaddr_reg:x3; val_offset:71604*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71604*0 + 3*60*FLEN/8, x4, x1, x2)

inst_23869:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffff80; valaddr_reg:x3; val_offset:71607*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71607*0 + 3*61*FLEN/8, x4, x1, x2)

inst_23870:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffffc0; valaddr_reg:x3; val_offset:71610*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71610*0 + 3*62*FLEN/8, x4, x1, x2)

inst_23871:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffffe0; valaddr_reg:x3; val_offset:71613*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71613*0 + 3*63*FLEN/8, x4, x1, x2)

inst_23872:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fffff0; valaddr_reg:x3; val_offset:71616*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71616*0 + 3*64*FLEN/8, x4, x1, x2)

inst_23873:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fffff8; valaddr_reg:x3; val_offset:71619*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71619*0 + 3*65*FLEN/8, x4, x1, x2)

inst_23874:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fffffc; valaddr_reg:x3; val_offset:71622*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71622*0 + 3*66*FLEN/8, x4, x1, x2)

inst_23875:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7fffffe; valaddr_reg:x3; val_offset:71625*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71625*0 + 3*67*FLEN/8, x4, x1, x2)

inst_23876:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d14ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed14ed; op2val:0x0;
op3val:0x7ffffff; valaddr_reg:x3; val_offset:71628*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71628*0 + 3*68*FLEN/8, x4, x1, x2)

inst_23877:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb000000; valaddr_reg:x3; val_offset:71631*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71631*0 + 3*69*FLEN/8, x4, x1, x2)

inst_23878:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb000001; valaddr_reg:x3; val_offset:71634*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71634*0 + 3*70*FLEN/8, x4, x1, x2)

inst_23879:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb000003; valaddr_reg:x3; val_offset:71637*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71637*0 + 3*71*FLEN/8, x4, x1, x2)

inst_23880:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb000007; valaddr_reg:x3; val_offset:71640*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71640*0 + 3*72*FLEN/8, x4, x1, x2)

inst_23881:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb00000f; valaddr_reg:x3; val_offset:71643*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71643*0 + 3*73*FLEN/8, x4, x1, x2)

inst_23882:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb00001f; valaddr_reg:x3; val_offset:71646*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71646*0 + 3*74*FLEN/8, x4, x1, x2)

inst_23883:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb00003f; valaddr_reg:x3; val_offset:71649*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71649*0 + 3*75*FLEN/8, x4, x1, x2)

inst_23884:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb00007f; valaddr_reg:x3; val_offset:71652*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71652*0 + 3*76*FLEN/8, x4, x1, x2)

inst_23885:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb0000ff; valaddr_reg:x3; val_offset:71655*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71655*0 + 3*77*FLEN/8, x4, x1, x2)

inst_23886:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb0001ff; valaddr_reg:x3; val_offset:71658*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71658*0 + 3*78*FLEN/8, x4, x1, x2)

inst_23887:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb0003ff; valaddr_reg:x3; val_offset:71661*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71661*0 + 3*79*FLEN/8, x4, x1, x2)

inst_23888:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb0007ff; valaddr_reg:x3; val_offset:71664*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71664*0 + 3*80*FLEN/8, x4, x1, x2)

inst_23889:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb000fff; valaddr_reg:x3; val_offset:71667*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71667*0 + 3*81*FLEN/8, x4, x1, x2)

inst_23890:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb001fff; valaddr_reg:x3; val_offset:71670*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71670*0 + 3*82*FLEN/8, x4, x1, x2)

inst_23891:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb003fff; valaddr_reg:x3; val_offset:71673*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71673*0 + 3*83*FLEN/8, x4, x1, x2)

inst_23892:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb007fff; valaddr_reg:x3; val_offset:71676*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71676*0 + 3*84*FLEN/8, x4, x1, x2)

inst_23893:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb00ffff; valaddr_reg:x3; val_offset:71679*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71679*0 + 3*85*FLEN/8, x4, x1, x2)

inst_23894:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb01ffff; valaddr_reg:x3; val_offset:71682*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71682*0 + 3*86*FLEN/8, x4, x1, x2)

inst_23895:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb03ffff; valaddr_reg:x3; val_offset:71685*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71685*0 + 3*87*FLEN/8, x4, x1, x2)

inst_23896:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb07ffff; valaddr_reg:x3; val_offset:71688*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71688*0 + 3*88*FLEN/8, x4, x1, x2)

inst_23897:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb0fffff; valaddr_reg:x3; val_offset:71691*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71691*0 + 3*89*FLEN/8, x4, x1, x2)

inst_23898:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb1fffff; valaddr_reg:x3; val_offset:71694*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71694*0 + 3*90*FLEN/8, x4, x1, x2)

inst_23899:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb3fffff; valaddr_reg:x3; val_offset:71697*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71697*0 + 3*91*FLEN/8, x4, x1, x2)

inst_23900:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb400000; valaddr_reg:x3; val_offset:71700*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71700*0 + 3*92*FLEN/8, x4, x1, x2)

inst_23901:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb600000; valaddr_reg:x3; val_offset:71703*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71703*0 + 3*93*FLEN/8, x4, x1, x2)

inst_23902:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb700000; valaddr_reg:x3; val_offset:71706*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71706*0 + 3*94*FLEN/8, x4, x1, x2)

inst_23903:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb780000; valaddr_reg:x3; val_offset:71709*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71709*0 + 3*95*FLEN/8, x4, x1, x2)

inst_23904:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7c0000; valaddr_reg:x3; val_offset:71712*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71712*0 + 3*96*FLEN/8, x4, x1, x2)

inst_23905:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7e0000; valaddr_reg:x3; val_offset:71715*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71715*0 + 3*97*FLEN/8, x4, x1, x2)

inst_23906:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7f0000; valaddr_reg:x3; val_offset:71718*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71718*0 + 3*98*FLEN/8, x4, x1, x2)

inst_23907:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7f8000; valaddr_reg:x3; val_offset:71721*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71721*0 + 3*99*FLEN/8, x4, x1, x2)

inst_23908:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fc000; valaddr_reg:x3; val_offset:71724*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71724*0 + 3*100*FLEN/8, x4, x1, x2)

inst_23909:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fe000; valaddr_reg:x3; val_offset:71727*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71727*0 + 3*101*FLEN/8, x4, x1, x2)

inst_23910:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ff000; valaddr_reg:x3; val_offset:71730*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71730*0 + 3*102*FLEN/8, x4, x1, x2)

inst_23911:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ff800; valaddr_reg:x3; val_offset:71733*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71733*0 + 3*103*FLEN/8, x4, x1, x2)

inst_23912:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ffc00; valaddr_reg:x3; val_offset:71736*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71736*0 + 3*104*FLEN/8, x4, x1, x2)

inst_23913:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ffe00; valaddr_reg:x3; val_offset:71739*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71739*0 + 3*105*FLEN/8, x4, x1, x2)

inst_23914:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fff00; valaddr_reg:x3; val_offset:71742*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71742*0 + 3*106*FLEN/8, x4, x1, x2)

inst_23915:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fff80; valaddr_reg:x3; val_offset:71745*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71745*0 + 3*107*FLEN/8, x4, x1, x2)

inst_23916:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fffc0; valaddr_reg:x3; val_offset:71748*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71748*0 + 3*108*FLEN/8, x4, x1, x2)

inst_23917:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fffe0; valaddr_reg:x3; val_offset:71751*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71751*0 + 3*109*FLEN/8, x4, x1, x2)

inst_23918:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ffff0; valaddr_reg:x3; val_offset:71754*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71754*0 + 3*110*FLEN/8, x4, x1, x2)

inst_23919:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ffff8; valaddr_reg:x3; val_offset:71757*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71757*0 + 3*111*FLEN/8, x4, x1, x2)

inst_23920:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ffffc; valaddr_reg:x3; val_offset:71760*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71760*0 + 3*112*FLEN/8, x4, x1, x2)

inst_23921:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7ffffe; valaddr_reg:x3; val_offset:71763*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71763*0 + 3*113*FLEN/8, x4, x1, x2)

inst_23922:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xd6 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xeb7fffff; valaddr_reg:x3; val_offset:71766*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71766*0 + 3*114*FLEN/8, x4, x1, x2)

inst_23923:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff000001; valaddr_reg:x3; val_offset:71769*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71769*0 + 3*115*FLEN/8, x4, x1, x2)

inst_23924:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff000003; valaddr_reg:x3; val_offset:71772*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71772*0 + 3*116*FLEN/8, x4, x1, x2)

inst_23925:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff000007; valaddr_reg:x3; val_offset:71775*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71775*0 + 3*117*FLEN/8, x4, x1, x2)

inst_23926:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff199999; valaddr_reg:x3; val_offset:71778*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71778*0 + 3*118*FLEN/8, x4, x1, x2)

inst_23927:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff249249; valaddr_reg:x3; val_offset:71781*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71781*0 + 3*119*FLEN/8, x4, x1, x2)

inst_23928:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff333333; valaddr_reg:x3; val_offset:71784*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71784*0 + 3*120*FLEN/8, x4, x1, x2)

inst_23929:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:71787*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71787*0 + 3*121*FLEN/8, x4, x1, x2)

inst_23930:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:71790*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71790*0 + 3*122*FLEN/8, x4, x1, x2)

inst_23931:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff444444; valaddr_reg:x3; val_offset:71793*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71793*0 + 3*123*FLEN/8, x4, x1, x2)

inst_23932:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:71796*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71796*0 + 3*124*FLEN/8, x4, x1, x2)

inst_23933:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:71799*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71799*0 + 3*125*FLEN/8, x4, x1, x2)

inst_23934:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff666666; valaddr_reg:x3; val_offset:71802*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71802*0 + 3*126*FLEN/8, x4, x1, x2)

inst_23935:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:71805*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71805*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_23936:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:71808*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71808*0 + 3*128*FLEN/8, x4, x1, x2)

inst_23937:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:71811*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71811*0 + 3*129*FLEN/8, x4, x1, x2)

inst_23938:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d982c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x09ea6a and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed982c; op2val:0xc009ea6a;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:71814*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71814*0 + 3*130*FLEN/8, x4, x1, x2)

inst_23939:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c800000; valaddr_reg:x3; val_offset:71817*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71817*0 + 3*131*FLEN/8, x4, x1, x2)

inst_23940:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c800001; valaddr_reg:x3; val_offset:71820*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71820*0 + 3*132*FLEN/8, x4, x1, x2)

inst_23941:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c800003; valaddr_reg:x3; val_offset:71823*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71823*0 + 3*133*FLEN/8, x4, x1, x2)

inst_23942:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c800007; valaddr_reg:x3; val_offset:71826*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71826*0 + 3*134*FLEN/8, x4, x1, x2)

inst_23943:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c80000f; valaddr_reg:x3; val_offset:71829*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71829*0 + 3*135*FLEN/8, x4, x1, x2)

inst_23944:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c80001f; valaddr_reg:x3; val_offset:71832*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71832*0 + 3*136*FLEN/8, x4, x1, x2)

inst_23945:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c80003f; valaddr_reg:x3; val_offset:71835*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71835*0 + 3*137*FLEN/8, x4, x1, x2)

inst_23946:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c80007f; valaddr_reg:x3; val_offset:71838*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71838*0 + 3*138*FLEN/8, x4, x1, x2)

inst_23947:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c8000ff; valaddr_reg:x3; val_offset:71841*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71841*0 + 3*139*FLEN/8, x4, x1, x2)

inst_23948:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c8001ff; valaddr_reg:x3; val_offset:71844*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71844*0 + 3*140*FLEN/8, x4, x1, x2)

inst_23949:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c8003ff; valaddr_reg:x3; val_offset:71847*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71847*0 + 3*141*FLEN/8, x4, x1, x2)

inst_23950:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c8007ff; valaddr_reg:x3; val_offset:71850*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71850*0 + 3*142*FLEN/8, x4, x1, x2)

inst_23951:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c800fff; valaddr_reg:x3; val_offset:71853*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71853*0 + 3*143*FLEN/8, x4, x1, x2)

inst_23952:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c801fff; valaddr_reg:x3; val_offset:71856*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71856*0 + 3*144*FLEN/8, x4, x1, x2)

inst_23953:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c803fff; valaddr_reg:x3; val_offset:71859*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71859*0 + 3*145*FLEN/8, x4, x1, x2)

inst_23954:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c807fff; valaddr_reg:x3; val_offset:71862*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71862*0 + 3*146*FLEN/8, x4, x1, x2)

inst_23955:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c80ffff; valaddr_reg:x3; val_offset:71865*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71865*0 + 3*147*FLEN/8, x4, x1, x2)

inst_23956:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c81ffff; valaddr_reg:x3; val_offset:71868*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71868*0 + 3*148*FLEN/8, x4, x1, x2)

inst_23957:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c83ffff; valaddr_reg:x3; val_offset:71871*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71871*0 + 3*149*FLEN/8, x4, x1, x2)

inst_23958:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c87ffff; valaddr_reg:x3; val_offset:71874*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71874*0 + 3*150*FLEN/8, x4, x1, x2)

inst_23959:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c8fffff; valaddr_reg:x3; val_offset:71877*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71877*0 + 3*151*FLEN/8, x4, x1, x2)

inst_23960:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3c9fffff; valaddr_reg:x3; val_offset:71880*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71880*0 + 3*152*FLEN/8, x4, x1, x2)

inst_23961:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cbfffff; valaddr_reg:x3; val_offset:71883*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71883*0 + 3*153*FLEN/8, x4, x1, x2)

inst_23962:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cc00000; valaddr_reg:x3; val_offset:71886*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71886*0 + 3*154*FLEN/8, x4, x1, x2)

inst_23963:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3ce00000; valaddr_reg:x3; val_offset:71889*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71889*0 + 3*155*FLEN/8, x4, x1, x2)

inst_23964:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cf00000; valaddr_reg:x3; val_offset:71892*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71892*0 + 3*156*FLEN/8, x4, x1, x2)

inst_23965:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cf80000; valaddr_reg:x3; val_offset:71895*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71895*0 + 3*157*FLEN/8, x4, x1, x2)

inst_23966:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfc0000; valaddr_reg:x3; val_offset:71898*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71898*0 + 3*158*FLEN/8, x4, x1, x2)

inst_23967:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfe0000; valaddr_reg:x3; val_offset:71901*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71901*0 + 3*159*FLEN/8, x4, x1, x2)

inst_23968:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cff0000; valaddr_reg:x3; val_offset:71904*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71904*0 + 3*160*FLEN/8, x4, x1, x2)

inst_23969:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cff8000; valaddr_reg:x3; val_offset:71907*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71907*0 + 3*161*FLEN/8, x4, x1, x2)

inst_23970:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffc000; valaddr_reg:x3; val_offset:71910*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71910*0 + 3*162*FLEN/8, x4, x1, x2)

inst_23971:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffe000; valaddr_reg:x3; val_offset:71913*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71913*0 + 3*163*FLEN/8, x4, x1, x2)

inst_23972:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfff000; valaddr_reg:x3; val_offset:71916*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71916*0 + 3*164*FLEN/8, x4, x1, x2)

inst_23973:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfff800; valaddr_reg:x3; val_offset:71919*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71919*0 + 3*165*FLEN/8, x4, x1, x2)

inst_23974:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfffc00; valaddr_reg:x3; val_offset:71922*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71922*0 + 3*166*FLEN/8, x4, x1, x2)

inst_23975:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfffe00; valaddr_reg:x3; val_offset:71925*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71925*0 + 3*167*FLEN/8, x4, x1, x2)

inst_23976:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffff00; valaddr_reg:x3; val_offset:71928*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71928*0 + 3*168*FLEN/8, x4, x1, x2)

inst_23977:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffff80; valaddr_reg:x3; val_offset:71931*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71931*0 + 3*169*FLEN/8, x4, x1, x2)

inst_23978:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffffc0; valaddr_reg:x3; val_offset:71934*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71934*0 + 3*170*FLEN/8, x4, x1, x2)

inst_23979:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffffe0; valaddr_reg:x3; val_offset:71937*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71937*0 + 3*171*FLEN/8, x4, x1, x2)

inst_23980:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfffff0; valaddr_reg:x3; val_offset:71940*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71940*0 + 3*172*FLEN/8, x4, x1, x2)

inst_23981:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfffff8; valaddr_reg:x3; val_offset:71943*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71943*0 + 3*173*FLEN/8, x4, x1, x2)

inst_23982:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfffffc; valaddr_reg:x3; val_offset:71946*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71946*0 + 3*174*FLEN/8, x4, x1, x2)

inst_23983:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cfffffe; valaddr_reg:x3; val_offset:71949*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71949*0 + 3*175*FLEN/8, x4, x1, x2)

inst_23984:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3cffffff; valaddr_reg:x3; val_offset:71952*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71952*0 + 3*176*FLEN/8, x4, x1, x2)

inst_23985:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3f800001; valaddr_reg:x3; val_offset:71955*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71955*0 + 3*177*FLEN/8, x4, x1, x2)

inst_23986:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3f800003; valaddr_reg:x3; val_offset:71958*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71958*0 + 3*178*FLEN/8, x4, x1, x2)

inst_23987:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3f800007; valaddr_reg:x3; val_offset:71961*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71961*0 + 3*179*FLEN/8, x4, x1, x2)

inst_23988:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3f999999; valaddr_reg:x3; val_offset:71964*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71964*0 + 3*180*FLEN/8, x4, x1, x2)

inst_23989:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:71967*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71967*0 + 3*181*FLEN/8, x4, x1, x2)

inst_23990:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:71970*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71970*0 + 3*182*FLEN/8, x4, x1, x2)

inst_23991:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:71973*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71973*0 + 3*183*FLEN/8, x4, x1, x2)

inst_23992:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:71976*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71976*0 + 3*184*FLEN/8, x4, x1, x2)

inst_23993:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:71979*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71979*0 + 3*185*FLEN/8, x4, x1, x2)

inst_23994:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:71982*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71982*0 + 3*186*FLEN/8, x4, x1, x2)

inst_23995:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:71985*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71985*0 + 3*187*FLEN/8, x4, x1, x2)

inst_23996:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:71988*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71988*0 + 3*188*FLEN/8, x4, x1, x2)

inst_23997:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:71991*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71991*0 + 3*189*FLEN/8, x4, x1, x2)

inst_23998:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:71994*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71994*0 + 3*190*FLEN/8, x4, x1, x2)

inst_23999:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:71997*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 71997*0 + 3*191*FLEN/8, x4, x1, x2)

inst_24000:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e4f75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x44c02c and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee4f75; op2val:0x44c02c;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:72000*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72000*0 + 3*192*FLEN/8, x4, x1, x2)

inst_24001:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:72003*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72003*0 + 3*193*FLEN/8, x4, x1, x2)

inst_24002:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:72006*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72006*0 + 3*194*FLEN/8, x4, x1, x2)

inst_24003:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:72009*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72009*0 + 3*195*FLEN/8, x4, x1, x2)

inst_24004:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:72012*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72012*0 + 3*196*FLEN/8, x4, x1, x2)

inst_24005:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:72015*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72015*0 + 3*197*FLEN/8, x4, x1, x2)

inst_24006:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:72018*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72018*0 + 3*198*FLEN/8, x4, x1, x2)

inst_24007:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:72021*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72021*0 + 3*199*FLEN/8, x4, x1, x2)

inst_24008:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:72024*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72024*0 + 3*200*FLEN/8, x4, x1, x2)

inst_24009:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:72027*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72027*0 + 3*201*FLEN/8, x4, x1, x2)

inst_24010:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:72030*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72030*0 + 3*202*FLEN/8, x4, x1, x2)

inst_24011:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:72033*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72033*0 + 3*203*FLEN/8, x4, x1, x2)

inst_24012:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:72036*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72036*0 + 3*204*FLEN/8, x4, x1, x2)

inst_24013:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:72039*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72039*0 + 3*205*FLEN/8, x4, x1, x2)

inst_24014:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:72042*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72042*0 + 3*206*FLEN/8, x4, x1, x2)

inst_24015:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:72045*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72045*0 + 3*207*FLEN/8, x4, x1, x2)

inst_24016:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:72048*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72048*0 + 3*208*FLEN/8, x4, x1, x2)

inst_24017:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf000000; valaddr_reg:x3; val_offset:72051*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72051*0 + 3*209*FLEN/8, x4, x1, x2)

inst_24018:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf000001; valaddr_reg:x3; val_offset:72054*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72054*0 + 3*210*FLEN/8, x4, x1, x2)

inst_24019:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf000003; valaddr_reg:x3; val_offset:72057*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72057*0 + 3*211*FLEN/8, x4, x1, x2)

inst_24020:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf000007; valaddr_reg:x3; val_offset:72060*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72060*0 + 3*212*FLEN/8, x4, x1, x2)

inst_24021:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf00000f; valaddr_reg:x3; val_offset:72063*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72063*0 + 3*213*FLEN/8, x4, x1, x2)

inst_24022:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf00001f; valaddr_reg:x3; val_offset:72066*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72066*0 + 3*214*FLEN/8, x4, x1, x2)

inst_24023:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf00003f; valaddr_reg:x3; val_offset:72069*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72069*0 + 3*215*FLEN/8, x4, x1, x2)

inst_24024:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf00007f; valaddr_reg:x3; val_offset:72072*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72072*0 + 3*216*FLEN/8, x4, x1, x2)

inst_24025:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf0000ff; valaddr_reg:x3; val_offset:72075*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72075*0 + 3*217*FLEN/8, x4, x1, x2)

inst_24026:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf0001ff; valaddr_reg:x3; val_offset:72078*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72078*0 + 3*218*FLEN/8, x4, x1, x2)

inst_24027:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf0003ff; valaddr_reg:x3; val_offset:72081*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72081*0 + 3*219*FLEN/8, x4, x1, x2)

inst_24028:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf0007ff; valaddr_reg:x3; val_offset:72084*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72084*0 + 3*220*FLEN/8, x4, x1, x2)

inst_24029:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf000fff; valaddr_reg:x3; val_offset:72087*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72087*0 + 3*221*FLEN/8, x4, x1, x2)

inst_24030:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf001fff; valaddr_reg:x3; val_offset:72090*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72090*0 + 3*222*FLEN/8, x4, x1, x2)

inst_24031:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf003fff; valaddr_reg:x3; val_offset:72093*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72093*0 + 3*223*FLEN/8, x4, x1, x2)

inst_24032:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf007fff; valaddr_reg:x3; val_offset:72096*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72096*0 + 3*224*FLEN/8, x4, x1, x2)

inst_24033:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf00ffff; valaddr_reg:x3; val_offset:72099*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72099*0 + 3*225*FLEN/8, x4, x1, x2)

inst_24034:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf01ffff; valaddr_reg:x3; val_offset:72102*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72102*0 + 3*226*FLEN/8, x4, x1, x2)

inst_24035:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf03ffff; valaddr_reg:x3; val_offset:72105*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72105*0 + 3*227*FLEN/8, x4, x1, x2)

inst_24036:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf07ffff; valaddr_reg:x3; val_offset:72108*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72108*0 + 3*228*FLEN/8, x4, x1, x2)

inst_24037:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf0fffff; valaddr_reg:x3; val_offset:72111*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72111*0 + 3*229*FLEN/8, x4, x1, x2)

inst_24038:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf1fffff; valaddr_reg:x3; val_offset:72114*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72114*0 + 3*230*FLEN/8, x4, x1, x2)

inst_24039:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf3fffff; valaddr_reg:x3; val_offset:72117*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72117*0 + 3*231*FLEN/8, x4, x1, x2)

inst_24040:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf400000; valaddr_reg:x3; val_offset:72120*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72120*0 + 3*232*FLEN/8, x4, x1, x2)

inst_24041:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf600000; valaddr_reg:x3; val_offset:72123*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72123*0 + 3*233*FLEN/8, x4, x1, x2)

inst_24042:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf700000; valaddr_reg:x3; val_offset:72126*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72126*0 + 3*234*FLEN/8, x4, x1, x2)

inst_24043:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf780000; valaddr_reg:x3; val_offset:72129*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72129*0 + 3*235*FLEN/8, x4, x1, x2)

inst_24044:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7c0000; valaddr_reg:x3; val_offset:72132*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72132*0 + 3*236*FLEN/8, x4, x1, x2)

inst_24045:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7e0000; valaddr_reg:x3; val_offset:72135*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72135*0 + 3*237*FLEN/8, x4, x1, x2)

inst_24046:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7f0000; valaddr_reg:x3; val_offset:72138*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72138*0 + 3*238*FLEN/8, x4, x1, x2)

inst_24047:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7f8000; valaddr_reg:x3; val_offset:72141*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72141*0 + 3*239*FLEN/8, x4, x1, x2)

inst_24048:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fc000; valaddr_reg:x3; val_offset:72144*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72144*0 + 3*240*FLEN/8, x4, x1, x2)

inst_24049:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fe000; valaddr_reg:x3; val_offset:72147*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72147*0 + 3*241*FLEN/8, x4, x1, x2)

inst_24050:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ff000; valaddr_reg:x3; val_offset:72150*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72150*0 + 3*242*FLEN/8, x4, x1, x2)

inst_24051:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ff800; valaddr_reg:x3; val_offset:72153*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72153*0 + 3*243*FLEN/8, x4, x1, x2)

inst_24052:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ffc00; valaddr_reg:x3; val_offset:72156*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72156*0 + 3*244*FLEN/8, x4, x1, x2)

inst_24053:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ffe00; valaddr_reg:x3; val_offset:72159*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72159*0 + 3*245*FLEN/8, x4, x1, x2)

inst_24054:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fff00; valaddr_reg:x3; val_offset:72162*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72162*0 + 3*246*FLEN/8, x4, x1, x2)

inst_24055:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fff80; valaddr_reg:x3; val_offset:72165*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72165*0 + 3*247*FLEN/8, x4, x1, x2)

inst_24056:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fffc0; valaddr_reg:x3; val_offset:72168*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72168*0 + 3*248*FLEN/8, x4, x1, x2)

inst_24057:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fffe0; valaddr_reg:x3; val_offset:72171*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72171*0 + 3*249*FLEN/8, x4, x1, x2)

inst_24058:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ffff0; valaddr_reg:x3; val_offset:72174*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72174*0 + 3*250*FLEN/8, x4, x1, x2)

inst_24059:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ffff8; valaddr_reg:x3; val_offset:72177*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72177*0 + 3*251*FLEN/8, x4, x1, x2)

inst_24060:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ffffc; valaddr_reg:x3; val_offset:72180*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72180*0 + 3*252*FLEN/8, x4, x1, x2)

inst_24061:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7ffffe; valaddr_reg:x3; val_offset:72183*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72183*0 + 3*253*FLEN/8, x4, x1, x2)

inst_24062:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6edcc4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeedcc4; op2val:0x0;
op3val:0xf7fffff; valaddr_reg:x3; val_offset:72186*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72186*0 + 3*254*FLEN/8, x4, x1, x2)

inst_24063:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:72189*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72189*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_24064:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:72192*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72192*0 + 3*256*FLEN/8, x4, x1, x2)

inst_24065:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:72195*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72195*0 + 3*257*FLEN/8, x4, x1, x2)

inst_24066:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:72198*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72198*0 + 3*258*FLEN/8, x4, x1, x2)

inst_24067:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:72201*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72201*0 + 3*259*FLEN/8, x4, x1, x2)

inst_24068:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:72204*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72204*0 + 3*260*FLEN/8, x4, x1, x2)

inst_24069:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:72207*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72207*0 + 3*261*FLEN/8, x4, x1, x2)

inst_24070:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:72210*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72210*0 + 3*262*FLEN/8, x4, x1, x2)

inst_24071:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:72213*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72213*0 + 3*263*FLEN/8, x4, x1, x2)

inst_24072:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:72216*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72216*0 + 3*264*FLEN/8, x4, x1, x2)

inst_24073:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:72219*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72219*0 + 3*265*FLEN/8, x4, x1, x2)

inst_24074:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:72222*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72222*0 + 3*266*FLEN/8, x4, x1, x2)

inst_24075:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:72225*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72225*0 + 3*267*FLEN/8, x4, x1, x2)

inst_24076:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:72228*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72228*0 + 3*268*FLEN/8, x4, x1, x2)

inst_24077:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:72231*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72231*0 + 3*269*FLEN/8, x4, x1, x2)

inst_24078:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:72234*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72234*0 + 3*270*FLEN/8, x4, x1, x2)

inst_24079:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c000000; valaddr_reg:x3; val_offset:72237*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72237*0 + 3*271*FLEN/8, x4, x1, x2)

inst_24080:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c000001; valaddr_reg:x3; val_offset:72240*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72240*0 + 3*272*FLEN/8, x4, x1, x2)

inst_24081:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c000003; valaddr_reg:x3; val_offset:72243*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72243*0 + 3*273*FLEN/8, x4, x1, x2)

inst_24082:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c000007; valaddr_reg:x3; val_offset:72246*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72246*0 + 3*274*FLEN/8, x4, x1, x2)

inst_24083:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c00000f; valaddr_reg:x3; val_offset:72249*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72249*0 + 3*275*FLEN/8, x4, x1, x2)

inst_24084:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c00001f; valaddr_reg:x3; val_offset:72252*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72252*0 + 3*276*FLEN/8, x4, x1, x2)

inst_24085:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c00003f; valaddr_reg:x3; val_offset:72255*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72255*0 + 3*277*FLEN/8, x4, x1, x2)

inst_24086:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c00007f; valaddr_reg:x3; val_offset:72258*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72258*0 + 3*278*FLEN/8, x4, x1, x2)

inst_24087:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c0000ff; valaddr_reg:x3; val_offset:72261*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72261*0 + 3*279*FLEN/8, x4, x1, x2)

inst_24088:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c0001ff; valaddr_reg:x3; val_offset:72264*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72264*0 + 3*280*FLEN/8, x4, x1, x2)

inst_24089:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c0003ff; valaddr_reg:x3; val_offset:72267*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72267*0 + 3*281*FLEN/8, x4, x1, x2)

inst_24090:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c0007ff; valaddr_reg:x3; val_offset:72270*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72270*0 + 3*282*FLEN/8, x4, x1, x2)

inst_24091:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c000fff; valaddr_reg:x3; val_offset:72273*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72273*0 + 3*283*FLEN/8, x4, x1, x2)

inst_24092:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c001fff; valaddr_reg:x3; val_offset:72276*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72276*0 + 3*284*FLEN/8, x4, x1, x2)

inst_24093:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c003fff; valaddr_reg:x3; val_offset:72279*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72279*0 + 3*285*FLEN/8, x4, x1, x2)

inst_24094:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c007fff; valaddr_reg:x3; val_offset:72282*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72282*0 + 3*286*FLEN/8, x4, x1, x2)

inst_24095:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c00ffff; valaddr_reg:x3; val_offset:72285*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72285*0 + 3*287*FLEN/8, x4, x1, x2)

inst_24096:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c01ffff; valaddr_reg:x3; val_offset:72288*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72288*0 + 3*288*FLEN/8, x4, x1, x2)

inst_24097:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c03ffff; valaddr_reg:x3; val_offset:72291*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72291*0 + 3*289*FLEN/8, x4, x1, x2)

inst_24098:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c07ffff; valaddr_reg:x3; val_offset:72294*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72294*0 + 3*290*FLEN/8, x4, x1, x2)

inst_24099:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c0fffff; valaddr_reg:x3; val_offset:72297*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72297*0 + 3*291*FLEN/8, x4, x1, x2)

inst_24100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c1fffff; valaddr_reg:x3; val_offset:72300*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72300*0 + 3*292*FLEN/8, x4, x1, x2)

inst_24101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c3fffff; valaddr_reg:x3; val_offset:72303*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72303*0 + 3*293*FLEN/8, x4, x1, x2)

inst_24102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c400000; valaddr_reg:x3; val_offset:72306*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72306*0 + 3*294*FLEN/8, x4, x1, x2)

inst_24103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c600000; valaddr_reg:x3; val_offset:72309*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72309*0 + 3*295*FLEN/8, x4, x1, x2)

inst_24104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c700000; valaddr_reg:x3; val_offset:72312*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72312*0 + 3*296*FLEN/8, x4, x1, x2)

inst_24105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c780000; valaddr_reg:x3; val_offset:72315*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72315*0 + 3*297*FLEN/8, x4, x1, x2)

inst_24106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7c0000; valaddr_reg:x3; val_offset:72318*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72318*0 + 3*298*FLEN/8, x4, x1, x2)

inst_24107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7e0000; valaddr_reg:x3; val_offset:72321*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72321*0 + 3*299*FLEN/8, x4, x1, x2)

inst_24108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7f0000; valaddr_reg:x3; val_offset:72324*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72324*0 + 3*300*FLEN/8, x4, x1, x2)

inst_24109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7f8000; valaddr_reg:x3; val_offset:72327*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72327*0 + 3*301*FLEN/8, x4, x1, x2)

inst_24110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fc000; valaddr_reg:x3; val_offset:72330*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72330*0 + 3*302*FLEN/8, x4, x1, x2)

inst_24111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fe000; valaddr_reg:x3; val_offset:72333*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72333*0 + 3*303*FLEN/8, x4, x1, x2)

inst_24112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ff000; valaddr_reg:x3; val_offset:72336*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72336*0 + 3*304*FLEN/8, x4, x1, x2)

inst_24113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ff800; valaddr_reg:x3; val_offset:72339*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72339*0 + 3*305*FLEN/8, x4, x1, x2)

inst_24114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ffc00; valaddr_reg:x3; val_offset:72342*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72342*0 + 3*306*FLEN/8, x4, x1, x2)

inst_24115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ffe00; valaddr_reg:x3; val_offset:72345*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72345*0 + 3*307*FLEN/8, x4, x1, x2)

inst_24116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fff00; valaddr_reg:x3; val_offset:72348*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72348*0 + 3*308*FLEN/8, x4, x1, x2)

inst_24117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fff80; valaddr_reg:x3; val_offset:72351*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72351*0 + 3*309*FLEN/8, x4, x1, x2)

inst_24118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fffc0; valaddr_reg:x3; val_offset:72354*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72354*0 + 3*310*FLEN/8, x4, x1, x2)

inst_24119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fffe0; valaddr_reg:x3; val_offset:72357*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72357*0 + 3*311*FLEN/8, x4, x1, x2)

inst_24120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ffff0; valaddr_reg:x3; val_offset:72360*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72360*0 + 3*312*FLEN/8, x4, x1, x2)

inst_24121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ffff8; valaddr_reg:x3; val_offset:72363*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72363*0 + 3*313*FLEN/8, x4, x1, x2)

inst_24122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ffffc; valaddr_reg:x3; val_offset:72366*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72366*0 + 3*314*FLEN/8, x4, x1, x2)

inst_24123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7ffffe; valaddr_reg:x3; val_offset:72369*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72369*0 + 3*315*FLEN/8, x4, x1, x2)

inst_24124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f6431 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef6431; op2val:0x80000000;
op3val:0x8c7fffff; valaddr_reg:x3; val_offset:72372*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72372*0 + 3*316*FLEN/8, x4, x1, x2)

inst_24125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:72375*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72375*0 + 3*317*FLEN/8, x4, x1, x2)

inst_24126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:72378*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72378*0 + 3*318*FLEN/8, x4, x1, x2)

inst_24127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:72381*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72381*0 + 3*319*FLEN/8, x4, x1, x2)

inst_24128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:72384*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72384*0 + 3*320*FLEN/8, x4, x1, x2)

inst_24129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:72387*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72387*0 + 3*321*FLEN/8, x4, x1, x2)

inst_24130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:72390*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72390*0 + 3*322*FLEN/8, x4, x1, x2)

inst_24131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:72393*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72393*0 + 3*323*FLEN/8, x4, x1, x2)

inst_24132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:72396*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72396*0 + 3*324*FLEN/8, x4, x1, x2)

inst_24133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:72399*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72399*0 + 3*325*FLEN/8, x4, x1, x2)

inst_24134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:72402*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72402*0 + 3*326*FLEN/8, x4, x1, x2)

inst_24135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:72405*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72405*0 + 3*327*FLEN/8, x4, x1, x2)

inst_24136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:72408*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72408*0 + 3*328*FLEN/8, x4, x1, x2)

inst_24137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:72411*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72411*0 + 3*329*FLEN/8, x4, x1, x2)

inst_24138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:72414*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72414*0 + 3*330*FLEN/8, x4, x1, x2)

inst_24139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:72417*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72417*0 + 3*331*FLEN/8, x4, x1, x2)

inst_24140:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:72420*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72420*0 + 3*332*FLEN/8, x4, x1, x2)

inst_24141:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd000000; valaddr_reg:x3; val_offset:72423*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72423*0 + 3*333*FLEN/8, x4, x1, x2)

inst_24142:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd000001; valaddr_reg:x3; val_offset:72426*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72426*0 + 3*334*FLEN/8, x4, x1, x2)

inst_24143:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd000003; valaddr_reg:x3; val_offset:72429*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72429*0 + 3*335*FLEN/8, x4, x1, x2)

inst_24144:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd000007; valaddr_reg:x3; val_offset:72432*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72432*0 + 3*336*FLEN/8, x4, x1, x2)

inst_24145:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd00000f; valaddr_reg:x3; val_offset:72435*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72435*0 + 3*337*FLEN/8, x4, x1, x2)

inst_24146:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd00001f; valaddr_reg:x3; val_offset:72438*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72438*0 + 3*338*FLEN/8, x4, x1, x2)

inst_24147:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd00003f; valaddr_reg:x3; val_offset:72441*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72441*0 + 3*339*FLEN/8, x4, x1, x2)

inst_24148:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd00007f; valaddr_reg:x3; val_offset:72444*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72444*0 + 3*340*FLEN/8, x4, x1, x2)

inst_24149:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd0000ff; valaddr_reg:x3; val_offset:72447*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72447*0 + 3*341*FLEN/8, x4, x1, x2)

inst_24150:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd0001ff; valaddr_reg:x3; val_offset:72450*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72450*0 + 3*342*FLEN/8, x4, x1, x2)

inst_24151:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd0003ff; valaddr_reg:x3; val_offset:72453*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72453*0 + 3*343*FLEN/8, x4, x1, x2)

inst_24152:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd0007ff; valaddr_reg:x3; val_offset:72456*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72456*0 + 3*344*FLEN/8, x4, x1, x2)

inst_24153:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd000fff; valaddr_reg:x3; val_offset:72459*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72459*0 + 3*345*FLEN/8, x4, x1, x2)

inst_24154:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd001fff; valaddr_reg:x3; val_offset:72462*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72462*0 + 3*346*FLEN/8, x4, x1, x2)

inst_24155:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd003fff; valaddr_reg:x3; val_offset:72465*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72465*0 + 3*347*FLEN/8, x4, x1, x2)

inst_24156:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd007fff; valaddr_reg:x3; val_offset:72468*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72468*0 + 3*348*FLEN/8, x4, x1, x2)

inst_24157:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd00ffff; valaddr_reg:x3; val_offset:72471*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72471*0 + 3*349*FLEN/8, x4, x1, x2)

inst_24158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd01ffff; valaddr_reg:x3; val_offset:72474*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72474*0 + 3*350*FLEN/8, x4, x1, x2)

inst_24159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd03ffff; valaddr_reg:x3; val_offset:72477*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72477*0 + 3*351*FLEN/8, x4, x1, x2)

inst_24160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd07ffff; valaddr_reg:x3; val_offset:72480*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72480*0 + 3*352*FLEN/8, x4, x1, x2)

inst_24161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd0fffff; valaddr_reg:x3; val_offset:72483*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72483*0 + 3*353*FLEN/8, x4, x1, x2)

inst_24162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd1fffff; valaddr_reg:x3; val_offset:72486*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72486*0 + 3*354*FLEN/8, x4, x1, x2)

inst_24163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd3fffff; valaddr_reg:x3; val_offset:72489*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72489*0 + 3*355*FLEN/8, x4, x1, x2)

inst_24164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd400000; valaddr_reg:x3; val_offset:72492*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72492*0 + 3*356*FLEN/8, x4, x1, x2)

inst_24165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd600000; valaddr_reg:x3; val_offset:72495*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72495*0 + 3*357*FLEN/8, x4, x1, x2)

inst_24166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd700000; valaddr_reg:x3; val_offset:72498*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72498*0 + 3*358*FLEN/8, x4, x1, x2)

inst_24167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd780000; valaddr_reg:x3; val_offset:72501*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72501*0 + 3*359*FLEN/8, x4, x1, x2)

inst_24168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7c0000; valaddr_reg:x3; val_offset:72504*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72504*0 + 3*360*FLEN/8, x4, x1, x2)

inst_24169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7e0000; valaddr_reg:x3; val_offset:72507*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72507*0 + 3*361*FLEN/8, x4, x1, x2)

inst_24170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7f0000; valaddr_reg:x3; val_offset:72510*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72510*0 + 3*362*FLEN/8, x4, x1, x2)

inst_24171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7f8000; valaddr_reg:x3; val_offset:72513*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72513*0 + 3*363*FLEN/8, x4, x1, x2)

inst_24172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fc000; valaddr_reg:x3; val_offset:72516*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72516*0 + 3*364*FLEN/8, x4, x1, x2)

inst_24173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fe000; valaddr_reg:x3; val_offset:72519*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72519*0 + 3*365*FLEN/8, x4, x1, x2)

inst_24174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ff000; valaddr_reg:x3; val_offset:72522*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72522*0 + 3*366*FLEN/8, x4, x1, x2)

inst_24175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ff800; valaddr_reg:x3; val_offset:72525*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72525*0 + 3*367*FLEN/8, x4, x1, x2)

inst_24176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ffc00; valaddr_reg:x3; val_offset:72528*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72528*0 + 3*368*FLEN/8, x4, x1, x2)

inst_24177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ffe00; valaddr_reg:x3; val_offset:72531*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72531*0 + 3*369*FLEN/8, x4, x1, x2)

inst_24178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fff00; valaddr_reg:x3; val_offset:72534*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72534*0 + 3*370*FLEN/8, x4, x1, x2)

inst_24179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fff80; valaddr_reg:x3; val_offset:72537*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72537*0 + 3*371*FLEN/8, x4, x1, x2)

inst_24180:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fffc0; valaddr_reg:x3; val_offset:72540*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72540*0 + 3*372*FLEN/8, x4, x1, x2)

inst_24181:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fffe0; valaddr_reg:x3; val_offset:72543*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72543*0 + 3*373*FLEN/8, x4, x1, x2)

inst_24182:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ffff0; valaddr_reg:x3; val_offset:72546*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72546*0 + 3*374*FLEN/8, x4, x1, x2)

inst_24183:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ffff8; valaddr_reg:x3; val_offset:72549*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72549*0 + 3*375*FLEN/8, x4, x1, x2)

inst_24184:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ffffc; valaddr_reg:x3; val_offset:72552*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72552*0 + 3*376*FLEN/8, x4, x1, x2)

inst_24185:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7ffffe; valaddr_reg:x3; val_offset:72555*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72555*0 + 3*377*FLEN/8, x4, x1, x2)

inst_24186:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70ab3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0ab3f; op2val:0x0;
op3val:0xd7fffff; valaddr_reg:x3; val_offset:72558*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72558*0 + 3*378*FLEN/8, x4, x1, x2)

inst_24187:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff000000; valaddr_reg:x3; val_offset:72561*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72561*0 + 3*379*FLEN/8, x4, x1, x2)

inst_24188:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff000001; valaddr_reg:x3; val_offset:72564*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72564*0 + 3*380*FLEN/8, x4, x1, x2)

inst_24189:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff000003; valaddr_reg:x3; val_offset:72567*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72567*0 + 3*381*FLEN/8, x4, x1, x2)

inst_24190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff000007; valaddr_reg:x3; val_offset:72570*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72570*0 + 3*382*FLEN/8, x4, x1, x2)

inst_24191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff00000f; valaddr_reg:x3; val_offset:72573*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72573*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_24192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff00001f; valaddr_reg:x3; val_offset:72576*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72576*0 + 3*384*FLEN/8, x4, x1, x2)

inst_24193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff00003f; valaddr_reg:x3; val_offset:72579*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72579*0 + 3*385*FLEN/8, x4, x1, x2)

inst_24194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff00007f; valaddr_reg:x3; val_offset:72582*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72582*0 + 3*386*FLEN/8, x4, x1, x2)

inst_24195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff0000ff; valaddr_reg:x3; val_offset:72585*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72585*0 + 3*387*FLEN/8, x4, x1, x2)

inst_24196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff0001ff; valaddr_reg:x3; val_offset:72588*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72588*0 + 3*388*FLEN/8, x4, x1, x2)

inst_24197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff0003ff; valaddr_reg:x3; val_offset:72591*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72591*0 + 3*389*FLEN/8, x4, x1, x2)

inst_24198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff0007ff; valaddr_reg:x3; val_offset:72594*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72594*0 + 3*390*FLEN/8, x4, x1, x2)

inst_24199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff000fff; valaddr_reg:x3; val_offset:72597*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72597*0 + 3*391*FLEN/8, x4, x1, x2)

inst_24200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff001fff; valaddr_reg:x3; val_offset:72600*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72600*0 + 3*392*FLEN/8, x4, x1, x2)

inst_24201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff003fff; valaddr_reg:x3; val_offset:72603*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72603*0 + 3*393*FLEN/8, x4, x1, x2)

inst_24202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff007fff; valaddr_reg:x3; val_offset:72606*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72606*0 + 3*394*FLEN/8, x4, x1, x2)

inst_24203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff00ffff; valaddr_reg:x3; val_offset:72609*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72609*0 + 3*395*FLEN/8, x4, x1, x2)

inst_24204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff01ffff; valaddr_reg:x3; val_offset:72612*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72612*0 + 3*396*FLEN/8, x4, x1, x2)

inst_24205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff03ffff; valaddr_reg:x3; val_offset:72615*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72615*0 + 3*397*FLEN/8, x4, x1, x2)

inst_24206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff07ffff; valaddr_reg:x3; val_offset:72618*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72618*0 + 3*398*FLEN/8, x4, x1, x2)

inst_24207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff0fffff; valaddr_reg:x3; val_offset:72621*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72621*0 + 3*399*FLEN/8, x4, x1, x2)

inst_24208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff199999; valaddr_reg:x3; val_offset:72624*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72624*0 + 3*400*FLEN/8, x4, x1, x2)

inst_24209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff1fffff; valaddr_reg:x3; val_offset:72627*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72627*0 + 3*401*FLEN/8, x4, x1, x2)

inst_24210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff249249; valaddr_reg:x3; val_offset:72630*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72630*0 + 3*402*FLEN/8, x4, x1, x2)

inst_24211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff333333; valaddr_reg:x3; val_offset:72633*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72633*0 + 3*403*FLEN/8, x4, x1, x2)

inst_24212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:72636*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72636*0 + 3*404*FLEN/8, x4, x1, x2)

inst_24213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:72639*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72639*0 + 3*405*FLEN/8, x4, x1, x2)

inst_24214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:72642*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72642*0 + 3*406*FLEN/8, x4, x1, x2)

inst_24215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff400000; valaddr_reg:x3; val_offset:72645*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72645*0 + 3*407*FLEN/8, x4, x1, x2)

inst_24216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff444444; valaddr_reg:x3; val_offset:72648*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72648*0 + 3*408*FLEN/8, x4, x1, x2)

inst_24217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:72651*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72651*0 + 3*409*FLEN/8, x4, x1, x2)

inst_24218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:72654*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72654*0 + 3*410*FLEN/8, x4, x1, x2)

inst_24219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff600000; valaddr_reg:x3; val_offset:72657*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72657*0 + 3*411*FLEN/8, x4, x1, x2)

inst_24220:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff666666; valaddr_reg:x3; val_offset:72660*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72660*0 + 3*412*FLEN/8, x4, x1, x2)

inst_24221:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:72663*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72663*0 + 3*413*FLEN/8, x4, x1, x2)

inst_24222:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff700000; valaddr_reg:x3; val_offset:72666*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72666*0 + 3*414*FLEN/8, x4, x1, x2)

inst_24223:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff780000; valaddr_reg:x3; val_offset:72669*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72669*0 + 3*415*FLEN/8, x4, x1, x2)

inst_24224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7c0000; valaddr_reg:x3; val_offset:72672*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72672*0 + 3*416*FLEN/8, x4, x1, x2)

inst_24225:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7e0000; valaddr_reg:x3; val_offset:72675*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72675*0 + 3*417*FLEN/8, x4, x1, x2)

inst_24226:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7f0000; valaddr_reg:x3; val_offset:72678*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72678*0 + 3*418*FLEN/8, x4, x1, x2)

inst_24227:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7f8000; valaddr_reg:x3; val_offset:72681*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72681*0 + 3*419*FLEN/8, x4, x1, x2)

inst_24228:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fc000; valaddr_reg:x3; val_offset:72684*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72684*0 + 3*420*FLEN/8, x4, x1, x2)

inst_24229:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fe000; valaddr_reg:x3; val_offset:72687*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72687*0 + 3*421*FLEN/8, x4, x1, x2)

inst_24230:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ff000; valaddr_reg:x3; val_offset:72690*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72690*0 + 3*422*FLEN/8, x4, x1, x2)

inst_24231:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ff800; valaddr_reg:x3; val_offset:72693*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72693*0 + 3*423*FLEN/8, x4, x1, x2)

inst_24232:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ffc00; valaddr_reg:x3; val_offset:72696*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72696*0 + 3*424*FLEN/8, x4, x1, x2)

inst_24233:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ffe00; valaddr_reg:x3; val_offset:72699*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72699*0 + 3*425*FLEN/8, x4, x1, x2)

inst_24234:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fff00; valaddr_reg:x3; val_offset:72702*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72702*0 + 3*426*FLEN/8, x4, x1, x2)

inst_24235:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fff80; valaddr_reg:x3; val_offset:72705*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72705*0 + 3*427*FLEN/8, x4, x1, x2)

inst_24236:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fffc0; valaddr_reg:x3; val_offset:72708*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72708*0 + 3*428*FLEN/8, x4, x1, x2)

inst_24237:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fffe0; valaddr_reg:x3; val_offset:72711*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72711*0 + 3*429*FLEN/8, x4, x1, x2)

inst_24238:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ffff0; valaddr_reg:x3; val_offset:72714*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72714*0 + 3*430*FLEN/8, x4, x1, x2)

inst_24239:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:72717*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72717*0 + 3*431*FLEN/8, x4, x1, x2)

inst_24240:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:72720*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72720*0 + 3*432*FLEN/8, x4, x1, x2)

inst_24241:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:72723*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72723*0 + 3*433*FLEN/8, x4, x1, x2)

inst_24242:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x70d256 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x081147 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef0d256; op2val:0xc0081147;
op3val:0xff7fffff; valaddr_reg:x3; val_offset:72726*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72726*0 + 3*434*FLEN/8, x4, x1, x2)

inst_24243:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd800000; valaddr_reg:x3; val_offset:72729*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72729*0 + 3*435*FLEN/8, x4, x1, x2)

inst_24244:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd800001; valaddr_reg:x3; val_offset:72732*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72732*0 + 3*436*FLEN/8, x4, x1, x2)

inst_24245:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd800003; valaddr_reg:x3; val_offset:72735*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72735*0 + 3*437*FLEN/8, x4, x1, x2)

inst_24246:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd800007; valaddr_reg:x3; val_offset:72738*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72738*0 + 3*438*FLEN/8, x4, x1, x2)

inst_24247:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd80000f; valaddr_reg:x3; val_offset:72741*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72741*0 + 3*439*FLEN/8, x4, x1, x2)

inst_24248:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd80001f; valaddr_reg:x3; val_offset:72744*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72744*0 + 3*440*FLEN/8, x4, x1, x2)

inst_24249:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd80003f; valaddr_reg:x3; val_offset:72747*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72747*0 + 3*441*FLEN/8, x4, x1, x2)

inst_24250:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd80007f; valaddr_reg:x3; val_offset:72750*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72750*0 + 3*442*FLEN/8, x4, x1, x2)

inst_24251:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd8000ff; valaddr_reg:x3; val_offset:72753*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72753*0 + 3*443*FLEN/8, x4, x1, x2)

inst_24252:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd8001ff; valaddr_reg:x3; val_offset:72756*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72756*0 + 3*444*FLEN/8, x4, x1, x2)

inst_24253:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd8003ff; valaddr_reg:x3; val_offset:72759*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72759*0 + 3*445*FLEN/8, x4, x1, x2)

inst_24254:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd8007ff; valaddr_reg:x3; val_offset:72762*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72762*0 + 3*446*FLEN/8, x4, x1, x2)

inst_24255:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd800fff; valaddr_reg:x3; val_offset:72765*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72765*0 + 3*447*FLEN/8, x4, x1, x2)

inst_24256:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd801fff; valaddr_reg:x3; val_offset:72768*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72768*0 + 3*448*FLEN/8, x4, x1, x2)

inst_24257:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd803fff; valaddr_reg:x3; val_offset:72771*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72771*0 + 3*449*FLEN/8, x4, x1, x2)

inst_24258:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd807fff; valaddr_reg:x3; val_offset:72774*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72774*0 + 3*450*FLEN/8, x4, x1, x2)

inst_24259:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd80ffff; valaddr_reg:x3; val_offset:72777*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72777*0 + 3*451*FLEN/8, x4, x1, x2)

inst_24260:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd81ffff; valaddr_reg:x3; val_offset:72780*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72780*0 + 3*452*FLEN/8, x4, x1, x2)

inst_24261:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd83ffff; valaddr_reg:x3; val_offset:72783*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72783*0 + 3*453*FLEN/8, x4, x1, x2)

inst_24262:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd87ffff; valaddr_reg:x3; val_offset:72786*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72786*0 + 3*454*FLEN/8, x4, x1, x2)

inst_24263:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd8fffff; valaddr_reg:x3; val_offset:72789*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72789*0 + 3*455*FLEN/8, x4, x1, x2)

inst_24264:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbd9fffff; valaddr_reg:x3; val_offset:72792*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72792*0 + 3*456*FLEN/8, x4, x1, x2)

inst_24265:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdbfffff; valaddr_reg:x3; val_offset:72795*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72795*0 + 3*457*FLEN/8, x4, x1, x2)

inst_24266:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdc00000; valaddr_reg:x3; val_offset:72798*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72798*0 + 3*458*FLEN/8, x4, x1, x2)

inst_24267:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbde00000; valaddr_reg:x3; val_offset:72801*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72801*0 + 3*459*FLEN/8, x4, x1, x2)

inst_24268:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdf00000; valaddr_reg:x3; val_offset:72804*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72804*0 + 3*460*FLEN/8, x4, x1, x2)

inst_24269:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdf80000; valaddr_reg:x3; val_offset:72807*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72807*0 + 3*461*FLEN/8, x4, x1, x2)

inst_24270:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfc0000; valaddr_reg:x3; val_offset:72810*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72810*0 + 3*462*FLEN/8, x4, x1, x2)

inst_24271:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfe0000; valaddr_reg:x3; val_offset:72813*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72813*0 + 3*463*FLEN/8, x4, x1, x2)

inst_24272:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdff0000; valaddr_reg:x3; val_offset:72816*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72816*0 + 3*464*FLEN/8, x4, x1, x2)

inst_24273:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdff8000; valaddr_reg:x3; val_offset:72819*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72819*0 + 3*465*FLEN/8, x4, x1, x2)

inst_24274:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffc000; valaddr_reg:x3; val_offset:72822*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72822*0 + 3*466*FLEN/8, x4, x1, x2)

inst_24275:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffe000; valaddr_reg:x3; val_offset:72825*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72825*0 + 3*467*FLEN/8, x4, x1, x2)

inst_24276:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfff000; valaddr_reg:x3; val_offset:72828*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72828*0 + 3*468*FLEN/8, x4, x1, x2)

inst_24277:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfff800; valaddr_reg:x3; val_offset:72831*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72831*0 + 3*469*FLEN/8, x4, x1, x2)

inst_24278:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfffc00; valaddr_reg:x3; val_offset:72834*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72834*0 + 3*470*FLEN/8, x4, x1, x2)

inst_24279:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfffe00; valaddr_reg:x3; val_offset:72837*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72837*0 + 3*471*FLEN/8, x4, x1, x2)

inst_24280:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffff00; valaddr_reg:x3; val_offset:72840*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72840*0 + 3*472*FLEN/8, x4, x1, x2)

inst_24281:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffff80; valaddr_reg:x3; val_offset:72843*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72843*0 + 3*473*FLEN/8, x4, x1, x2)

inst_24282:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffffc0; valaddr_reg:x3; val_offset:72846*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72846*0 + 3*474*FLEN/8, x4, x1, x2)

inst_24283:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffffe0; valaddr_reg:x3; val_offset:72849*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72849*0 + 3*475*FLEN/8, x4, x1, x2)

inst_24284:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfffff0; valaddr_reg:x3; val_offset:72852*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72852*0 + 3*476*FLEN/8, x4, x1, x2)

inst_24285:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfffff8; valaddr_reg:x3; val_offset:72855*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72855*0 + 3*477*FLEN/8, x4, x1, x2)

inst_24286:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfffffc; valaddr_reg:x3; val_offset:72858*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72858*0 + 3*478*FLEN/8, x4, x1, x2)

inst_24287:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdfffffe; valaddr_reg:x3; val_offset:72861*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72861*0 + 3*479*FLEN/8, x4, x1, x2)

inst_24288:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbdffffff; valaddr_reg:x3; val_offset:72864*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72864*0 + 3*480*FLEN/8, x4, x1, x2)

inst_24289:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbf800001; valaddr_reg:x3; val_offset:72867*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72867*0 + 3*481*FLEN/8, x4, x1, x2)

inst_24290:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbf800003; valaddr_reg:x3; val_offset:72870*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72870*0 + 3*482*FLEN/8, x4, x1, x2)

inst_24291:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbf800007; valaddr_reg:x3; val_offset:72873*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72873*0 + 3*483*FLEN/8, x4, x1, x2)

inst_24292:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbf999999; valaddr_reg:x3; val_offset:72876*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72876*0 + 3*484*FLEN/8, x4, x1, x2)

inst_24293:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:72879*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72879*0 + 3*485*FLEN/8, x4, x1, x2)

inst_24294:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:72882*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72882*0 + 3*486*FLEN/8, x4, x1, x2)

inst_24295:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:72885*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72885*0 + 3*487*FLEN/8, x4, x1, x2)

inst_24296:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:72888*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72888*0 + 3*488*FLEN/8, x4, x1, x2)

inst_24297:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:72891*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72891*0 + 3*489*FLEN/8, x4, x1, x2)

inst_24298:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:72894*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72894*0 + 3*490*FLEN/8, x4, x1, x2)

inst_24299:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:72897*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72897*0 + 3*491*FLEN/8, x4, x1, x2)

inst_24300:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:72900*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72900*0 + 3*492*FLEN/8, x4, x1, x2)

inst_24301:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:72903*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72903*0 + 3*493*FLEN/8, x4, x1, x2)

inst_24302:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:72906*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72906*0 + 3*494*FLEN/8, x4, x1, x2)

inst_24303:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:72909*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72909*0 + 3*495*FLEN/8, x4, x1, x2)

inst_24304:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71036e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43fac8 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1036e; op2val:0x8043fac8;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:72912*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72912*0 + 3*496*FLEN/8, x4, x1, x2)

inst_24305:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed000000; valaddr_reg:x3; val_offset:72915*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72915*0 + 3*497*FLEN/8, x4, x1, x2)

inst_24306:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed000001; valaddr_reg:x3; val_offset:72918*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72918*0 + 3*498*FLEN/8, x4, x1, x2)

inst_24307:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed000003; valaddr_reg:x3; val_offset:72921*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72921*0 + 3*499*FLEN/8, x4, x1, x2)

inst_24308:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed000007; valaddr_reg:x3; val_offset:72924*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72924*0 + 3*500*FLEN/8, x4, x1, x2)

inst_24309:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed00000f; valaddr_reg:x3; val_offset:72927*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72927*0 + 3*501*FLEN/8, x4, x1, x2)

inst_24310:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed00001f; valaddr_reg:x3; val_offset:72930*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72930*0 + 3*502*FLEN/8, x4, x1, x2)

inst_24311:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed00003f; valaddr_reg:x3; val_offset:72933*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72933*0 + 3*503*FLEN/8, x4, x1, x2)

inst_24312:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed00007f; valaddr_reg:x3; val_offset:72936*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72936*0 + 3*504*FLEN/8, x4, x1, x2)

inst_24313:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed0000ff; valaddr_reg:x3; val_offset:72939*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72939*0 + 3*505*FLEN/8, x4, x1, x2)

inst_24314:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed0001ff; valaddr_reg:x3; val_offset:72942*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72942*0 + 3*506*FLEN/8, x4, x1, x2)

inst_24315:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed0003ff; valaddr_reg:x3; val_offset:72945*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72945*0 + 3*507*FLEN/8, x4, x1, x2)

inst_24316:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed0007ff; valaddr_reg:x3; val_offset:72948*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72948*0 + 3*508*FLEN/8, x4, x1, x2)

inst_24317:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed000fff; valaddr_reg:x3; val_offset:72951*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72951*0 + 3*509*FLEN/8, x4, x1, x2)

inst_24318:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed001fff; valaddr_reg:x3; val_offset:72954*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72954*0 + 3*510*FLEN/8, x4, x1, x2)

inst_24319:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed003fff; valaddr_reg:x3; val_offset:72957*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72957*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_24320:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed007fff; valaddr_reg:x3; val_offset:72960*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72960*0 + 3*512*FLEN/8, x4, x1, x2)

inst_24321:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed00ffff; valaddr_reg:x3; val_offset:72963*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72963*0 + 3*513*FLEN/8, x4, x1, x2)

inst_24322:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed01ffff; valaddr_reg:x3; val_offset:72966*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72966*0 + 3*514*FLEN/8, x4, x1, x2)

inst_24323:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed03ffff; valaddr_reg:x3; val_offset:72969*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72969*0 + 3*515*FLEN/8, x4, x1, x2)

inst_24324:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed07ffff; valaddr_reg:x3; val_offset:72972*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72972*0 + 3*516*FLEN/8, x4, x1, x2)

inst_24325:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed0fffff; valaddr_reg:x3; val_offset:72975*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72975*0 + 3*517*FLEN/8, x4, x1, x2)

inst_24326:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed1fffff; valaddr_reg:x3; val_offset:72978*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72978*0 + 3*518*FLEN/8, x4, x1, x2)

inst_24327:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed3fffff; valaddr_reg:x3; val_offset:72981*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72981*0 + 3*519*FLEN/8, x4, x1, x2)

inst_24328:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed400000; valaddr_reg:x3; val_offset:72984*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72984*0 + 3*520*FLEN/8, x4, x1, x2)

inst_24329:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed600000; valaddr_reg:x3; val_offset:72987*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72987*0 + 3*521*FLEN/8, x4, x1, x2)

inst_24330:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed700000; valaddr_reg:x3; val_offset:72990*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72990*0 + 3*522*FLEN/8, x4, x1, x2)

inst_24331:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed780000; valaddr_reg:x3; val_offset:72993*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72993*0 + 3*523*FLEN/8, x4, x1, x2)

inst_24332:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7c0000; valaddr_reg:x3; val_offset:72996*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72996*0 + 3*524*FLEN/8, x4, x1, x2)

inst_24333:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7e0000; valaddr_reg:x3; val_offset:72999*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 72999*0 + 3*525*FLEN/8, x4, x1, x2)

inst_24334:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7f0000; valaddr_reg:x3; val_offset:73002*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73002*0 + 3*526*FLEN/8, x4, x1, x2)

inst_24335:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7f8000; valaddr_reg:x3; val_offset:73005*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73005*0 + 3*527*FLEN/8, x4, x1, x2)

inst_24336:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fc000; valaddr_reg:x3; val_offset:73008*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73008*0 + 3*528*FLEN/8, x4, x1, x2)

inst_24337:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fe000; valaddr_reg:x3; val_offset:73011*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73011*0 + 3*529*FLEN/8, x4, x1, x2)

inst_24338:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ff000; valaddr_reg:x3; val_offset:73014*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73014*0 + 3*530*FLEN/8, x4, x1, x2)

inst_24339:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ff800; valaddr_reg:x3; val_offset:73017*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73017*0 + 3*531*FLEN/8, x4, x1, x2)

inst_24340:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ffc00; valaddr_reg:x3; val_offset:73020*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73020*0 + 3*532*FLEN/8, x4, x1, x2)

inst_24341:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ffe00; valaddr_reg:x3; val_offset:73023*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73023*0 + 3*533*FLEN/8, x4, x1, x2)

inst_24342:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fff00; valaddr_reg:x3; val_offset:73026*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73026*0 + 3*534*FLEN/8, x4, x1, x2)

inst_24343:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fff80; valaddr_reg:x3; val_offset:73029*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73029*0 + 3*535*FLEN/8, x4, x1, x2)

inst_24344:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fffc0; valaddr_reg:x3; val_offset:73032*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73032*0 + 3*536*FLEN/8, x4, x1, x2)

inst_24345:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fffe0; valaddr_reg:x3; val_offset:73035*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73035*0 + 3*537*FLEN/8, x4, x1, x2)

inst_24346:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ffff0; valaddr_reg:x3; val_offset:73038*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73038*0 + 3*538*FLEN/8, x4, x1, x2)

inst_24347:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ffff8; valaddr_reg:x3; val_offset:73041*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73041*0 + 3*539*FLEN/8, x4, x1, x2)

inst_24348:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ffffc; valaddr_reg:x3; val_offset:73044*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73044*0 + 3*540*FLEN/8, x4, x1, x2)

inst_24349:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7ffffe; valaddr_reg:x3; val_offset:73047*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73047*0 + 3*541*FLEN/8, x4, x1, x2)

inst_24350:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xda and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xed7fffff; valaddr_reg:x3; val_offset:73050*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73050*0 + 3*542*FLEN/8, x4, x1, x2)

inst_24351:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff000001; valaddr_reg:x3; val_offset:73053*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73053*0 + 3*543*FLEN/8, x4, x1, x2)

inst_24352:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff000003; valaddr_reg:x3; val_offset:73056*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73056*0 + 3*544*FLEN/8, x4, x1, x2)

inst_24353:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff000007; valaddr_reg:x3; val_offset:73059*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73059*0 + 3*545*FLEN/8, x4, x1, x2)

inst_24354:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff199999; valaddr_reg:x3; val_offset:73062*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73062*0 + 3*546*FLEN/8, x4, x1, x2)

inst_24355:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff249249; valaddr_reg:x3; val_offset:73065*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73065*0 + 3*547*FLEN/8, x4, x1, x2)

inst_24356:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff333333; valaddr_reg:x3; val_offset:73068*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73068*0 + 3*548*FLEN/8, x4, x1, x2)

inst_24357:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:73071*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73071*0 + 3*549*FLEN/8, x4, x1, x2)

inst_24358:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:73074*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73074*0 + 3*550*FLEN/8, x4, x1, x2)

inst_24359:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff444444; valaddr_reg:x3; val_offset:73077*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73077*0 + 3*551*FLEN/8, x4, x1, x2)

inst_24360:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:73080*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73080*0 + 3*552*FLEN/8, x4, x1, x2)

inst_24361:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:73083*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73083*0 + 3*553*FLEN/8, x4, x1, x2)

inst_24362:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff666666; valaddr_reg:x3; val_offset:73086*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73086*0 + 3*554*FLEN/8, x4, x1, x2)

inst_24363:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:73089*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73089*0 + 3*555*FLEN/8, x4, x1, x2)

inst_24364:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:73092*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73092*0 + 3*556*FLEN/8, x4, x1, x2)

inst_24365:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:73095*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73095*0 + 3*557*FLEN/8, x4, x1, x2)

inst_24366:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x718162 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x07aea7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef18162; op2val:0xc007aea7;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:73098*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73098*0 + 3*558*FLEN/8, x4, x1, x2)

inst_24367:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:73101*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73101*0 + 3*559*FLEN/8, x4, x1, x2)

inst_24368:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:73104*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73104*0 + 3*560*FLEN/8, x4, x1, x2)

inst_24369:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:73107*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73107*0 + 3*561*FLEN/8, x4, x1, x2)

inst_24370:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:73110*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73110*0 + 3*562*FLEN/8, x4, x1, x2)

inst_24371:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:73113*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73113*0 + 3*563*FLEN/8, x4, x1, x2)

inst_24372:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:73116*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73116*0 + 3*564*FLEN/8, x4, x1, x2)

inst_24373:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:73119*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73119*0 + 3*565*FLEN/8, x4, x1, x2)

inst_24374:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:73122*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73122*0 + 3*566*FLEN/8, x4, x1, x2)

inst_24375:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:73125*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73125*0 + 3*567*FLEN/8, x4, x1, x2)

inst_24376:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:73128*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73128*0 + 3*568*FLEN/8, x4, x1, x2)

inst_24377:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:73131*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73131*0 + 3*569*FLEN/8, x4, x1, x2)

inst_24378:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:73134*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73134*0 + 3*570*FLEN/8, x4, x1, x2)

inst_24379:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:73137*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73137*0 + 3*571*FLEN/8, x4, x1, x2)

inst_24380:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:73140*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73140*0 + 3*572*FLEN/8, x4, x1, x2)

inst_24381:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:73143*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73143*0 + 3*573*FLEN/8, x4, x1, x2)

inst_24382:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:73146*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73146*0 + 3*574*FLEN/8, x4, x1, x2)

inst_24383:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8000000; valaddr_reg:x3; val_offset:73149*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73149*0 + 3*575*FLEN/8, x4, x1, x2)

inst_24384:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8000001; valaddr_reg:x3; val_offset:73152*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73152*0 + 3*576*FLEN/8, x4, x1, x2)

inst_24385:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8000003; valaddr_reg:x3; val_offset:73155*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73155*0 + 3*577*FLEN/8, x4, x1, x2)

inst_24386:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8000007; valaddr_reg:x3; val_offset:73158*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73158*0 + 3*578*FLEN/8, x4, x1, x2)

inst_24387:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800000f; valaddr_reg:x3; val_offset:73161*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73161*0 + 3*579*FLEN/8, x4, x1, x2)

inst_24388:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800001f; valaddr_reg:x3; val_offset:73164*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73164*0 + 3*580*FLEN/8, x4, x1, x2)

inst_24389:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800003f; valaddr_reg:x3; val_offset:73167*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73167*0 + 3*581*FLEN/8, x4, x1, x2)

inst_24390:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800007f; valaddr_reg:x3; val_offset:73170*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73170*0 + 3*582*FLEN/8, x4, x1, x2)

inst_24391:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x80000ff; valaddr_reg:x3; val_offset:73173*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73173*0 + 3*583*FLEN/8, x4, x1, x2)

inst_24392:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x80001ff; valaddr_reg:x3; val_offset:73176*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73176*0 + 3*584*FLEN/8, x4, x1, x2)

inst_24393:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x80003ff; valaddr_reg:x3; val_offset:73179*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73179*0 + 3*585*FLEN/8, x4, x1, x2)

inst_24394:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x80007ff; valaddr_reg:x3; val_offset:73182*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73182*0 + 3*586*FLEN/8, x4, x1, x2)

inst_24395:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8000fff; valaddr_reg:x3; val_offset:73185*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73185*0 + 3*587*FLEN/8, x4, x1, x2)

inst_24396:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8001fff; valaddr_reg:x3; val_offset:73188*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73188*0 + 3*588*FLEN/8, x4, x1, x2)

inst_24397:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8003fff; valaddr_reg:x3; val_offset:73191*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73191*0 + 3*589*FLEN/8, x4, x1, x2)

inst_24398:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8007fff; valaddr_reg:x3; val_offset:73194*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73194*0 + 3*590*FLEN/8, x4, x1, x2)

inst_24399:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x800ffff; valaddr_reg:x3; val_offset:73197*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73197*0 + 3*591*FLEN/8, x4, x1, x2)

inst_24400:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x801ffff; valaddr_reg:x3; val_offset:73200*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73200*0 + 3*592*FLEN/8, x4, x1, x2)

inst_24401:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x803ffff; valaddr_reg:x3; val_offset:73203*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73203*0 + 3*593*FLEN/8, x4, x1, x2)

inst_24402:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x807ffff; valaddr_reg:x3; val_offset:73206*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73206*0 + 3*594*FLEN/8, x4, x1, x2)

inst_24403:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x80fffff; valaddr_reg:x3; val_offset:73209*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73209*0 + 3*595*FLEN/8, x4, x1, x2)

inst_24404:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x81fffff; valaddr_reg:x3; val_offset:73212*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73212*0 + 3*596*FLEN/8, x4, x1, x2)

inst_24405:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x83fffff; valaddr_reg:x3; val_offset:73215*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73215*0 + 3*597*FLEN/8, x4, x1, x2)

inst_24406:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8400000; valaddr_reg:x3; val_offset:73218*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73218*0 + 3*598*FLEN/8, x4, x1, x2)

inst_24407:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8600000; valaddr_reg:x3; val_offset:73221*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73221*0 + 3*599*FLEN/8, x4, x1, x2)

inst_24408:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8700000; valaddr_reg:x3; val_offset:73224*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73224*0 + 3*600*FLEN/8, x4, x1, x2)

inst_24409:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x8780000; valaddr_reg:x3; val_offset:73227*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73227*0 + 3*601*FLEN/8, x4, x1, x2)

inst_24410:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87c0000; valaddr_reg:x3; val_offset:73230*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73230*0 + 3*602*FLEN/8, x4, x1, x2)

inst_24411:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87e0000; valaddr_reg:x3; val_offset:73233*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73233*0 + 3*603*FLEN/8, x4, x1, x2)

inst_24412:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87f0000; valaddr_reg:x3; val_offset:73236*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73236*0 + 3*604*FLEN/8, x4, x1, x2)

inst_24413:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87f8000; valaddr_reg:x3; val_offset:73239*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73239*0 + 3*605*FLEN/8, x4, x1, x2)

inst_24414:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fc000; valaddr_reg:x3; val_offset:73242*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73242*0 + 3*606*FLEN/8, x4, x1, x2)

inst_24415:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fe000; valaddr_reg:x3; val_offset:73245*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73245*0 + 3*607*FLEN/8, x4, x1, x2)

inst_24416:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ff000; valaddr_reg:x3; val_offset:73248*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73248*0 + 3*608*FLEN/8, x4, x1, x2)

inst_24417:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ff800; valaddr_reg:x3; val_offset:73251*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73251*0 + 3*609*FLEN/8, x4, x1, x2)

inst_24418:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ffc00; valaddr_reg:x3; val_offset:73254*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73254*0 + 3*610*FLEN/8, x4, x1, x2)

inst_24419:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ffe00; valaddr_reg:x3; val_offset:73257*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73257*0 + 3*611*FLEN/8, x4, x1, x2)

inst_24420:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fff00; valaddr_reg:x3; val_offset:73260*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73260*0 + 3*612*FLEN/8, x4, x1, x2)

inst_24421:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fff80; valaddr_reg:x3; val_offset:73263*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73263*0 + 3*613*FLEN/8, x4, x1, x2)

inst_24422:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fffc0; valaddr_reg:x3; val_offset:73266*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73266*0 + 3*614*FLEN/8, x4, x1, x2)

inst_24423:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fffe0; valaddr_reg:x3; val_offset:73269*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73269*0 + 3*615*FLEN/8, x4, x1, x2)

inst_24424:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ffff0; valaddr_reg:x3; val_offset:73272*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73272*0 + 3*616*FLEN/8, x4, x1, x2)

inst_24425:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ffff8; valaddr_reg:x3; val_offset:73275*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73275*0 + 3*617*FLEN/8, x4, x1, x2)

inst_24426:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ffffc; valaddr_reg:x3; val_offset:73278*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73278*0 + 3*618*FLEN/8, x4, x1, x2)

inst_24427:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87ffffe; valaddr_reg:x3; val_offset:73281*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73281*0 + 3*619*FLEN/8, x4, x1, x2)

inst_24428:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71e834 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1e834; op2val:0x0;
op3val:0x87fffff; valaddr_reg:x3; val_offset:73284*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73284*0 + 3*620*FLEN/8, x4, x1, x2)

inst_24429:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:73287*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73287*0 + 3*621*FLEN/8, x4, x1, x2)

inst_24430:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:73290*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73290*0 + 3*622*FLEN/8, x4, x1, x2)

inst_24431:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:73293*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73293*0 + 3*623*FLEN/8, x4, x1, x2)

inst_24432:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:73296*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73296*0 + 3*624*FLEN/8, x4, x1, x2)

inst_24433:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:73299*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73299*0 + 3*625*FLEN/8, x4, x1, x2)

inst_24434:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:73302*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73302*0 + 3*626*FLEN/8, x4, x1, x2)

inst_24435:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:73305*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73305*0 + 3*627*FLEN/8, x4, x1, x2)

inst_24436:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:73308*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73308*0 + 3*628*FLEN/8, x4, x1, x2)

inst_24437:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:73311*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73311*0 + 3*629*FLEN/8, x4, x1, x2)

inst_24438:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:73314*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73314*0 + 3*630*FLEN/8, x4, x1, x2)

inst_24439:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:73317*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73317*0 + 3*631*FLEN/8, x4, x1, x2)

inst_24440:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:73320*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73320*0 + 3*632*FLEN/8, x4, x1, x2)

inst_24441:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:73323*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73323*0 + 3*633*FLEN/8, x4, x1, x2)

inst_24442:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:73326*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73326*0 + 3*634*FLEN/8, x4, x1, x2)

inst_24443:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:73329*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73329*0 + 3*635*FLEN/8, x4, x1, x2)

inst_24444:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:73332*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73332*0 + 3*636*FLEN/8, x4, x1, x2)

inst_24445:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd000000; valaddr_reg:x3; val_offset:73335*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73335*0 + 3*637*FLEN/8, x4, x1, x2)

inst_24446:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd000001; valaddr_reg:x3; val_offset:73338*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73338*0 + 3*638*FLEN/8, x4, x1, x2)

inst_24447:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd000003; valaddr_reg:x3; val_offset:73341*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73341*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_24448:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd000007; valaddr_reg:x3; val_offset:73344*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73344*0 + 3*640*FLEN/8, x4, x1, x2)

inst_24449:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd00000f; valaddr_reg:x3; val_offset:73347*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73347*0 + 3*641*FLEN/8, x4, x1, x2)

inst_24450:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd00001f; valaddr_reg:x3; val_offset:73350*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73350*0 + 3*642*FLEN/8, x4, x1, x2)

inst_24451:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd00003f; valaddr_reg:x3; val_offset:73353*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73353*0 + 3*643*FLEN/8, x4, x1, x2)

inst_24452:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd00007f; valaddr_reg:x3; val_offset:73356*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73356*0 + 3*644*FLEN/8, x4, x1, x2)

inst_24453:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd0000ff; valaddr_reg:x3; val_offset:73359*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73359*0 + 3*645*FLEN/8, x4, x1, x2)

inst_24454:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd0001ff; valaddr_reg:x3; val_offset:73362*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73362*0 + 3*646*FLEN/8, x4, x1, x2)

inst_24455:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd0003ff; valaddr_reg:x3; val_offset:73365*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73365*0 + 3*647*FLEN/8, x4, x1, x2)

inst_24456:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd0007ff; valaddr_reg:x3; val_offset:73368*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73368*0 + 3*648*FLEN/8, x4, x1, x2)

inst_24457:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd000fff; valaddr_reg:x3; val_offset:73371*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73371*0 + 3*649*FLEN/8, x4, x1, x2)

inst_24458:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd001fff; valaddr_reg:x3; val_offset:73374*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73374*0 + 3*650*FLEN/8, x4, x1, x2)

inst_24459:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd003fff; valaddr_reg:x3; val_offset:73377*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73377*0 + 3*651*FLEN/8, x4, x1, x2)

inst_24460:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd007fff; valaddr_reg:x3; val_offset:73380*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73380*0 + 3*652*FLEN/8, x4, x1, x2)

inst_24461:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd00ffff; valaddr_reg:x3; val_offset:73383*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73383*0 + 3*653*FLEN/8, x4, x1, x2)

inst_24462:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd01ffff; valaddr_reg:x3; val_offset:73386*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73386*0 + 3*654*FLEN/8, x4, x1, x2)

inst_24463:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd03ffff; valaddr_reg:x3; val_offset:73389*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73389*0 + 3*655*FLEN/8, x4, x1, x2)

inst_24464:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd07ffff; valaddr_reg:x3; val_offset:73392*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73392*0 + 3*656*FLEN/8, x4, x1, x2)

inst_24465:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd0fffff; valaddr_reg:x3; val_offset:73395*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73395*0 + 3*657*FLEN/8, x4, x1, x2)

inst_24466:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd1fffff; valaddr_reg:x3; val_offset:73398*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73398*0 + 3*658*FLEN/8, x4, x1, x2)

inst_24467:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd3fffff; valaddr_reg:x3; val_offset:73401*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73401*0 + 3*659*FLEN/8, x4, x1, x2)

inst_24468:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd400000; valaddr_reg:x3; val_offset:73404*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73404*0 + 3*660*FLEN/8, x4, x1, x2)

inst_24469:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd600000; valaddr_reg:x3; val_offset:73407*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73407*0 + 3*661*FLEN/8, x4, x1, x2)

inst_24470:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd700000; valaddr_reg:x3; val_offset:73410*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73410*0 + 3*662*FLEN/8, x4, x1, x2)

inst_24471:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd780000; valaddr_reg:x3; val_offset:73413*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73413*0 + 3*663*FLEN/8, x4, x1, x2)

inst_24472:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7c0000; valaddr_reg:x3; val_offset:73416*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73416*0 + 3*664*FLEN/8, x4, x1, x2)

inst_24473:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7e0000; valaddr_reg:x3; val_offset:73419*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73419*0 + 3*665*FLEN/8, x4, x1, x2)

inst_24474:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7f0000; valaddr_reg:x3; val_offset:73422*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73422*0 + 3*666*FLEN/8, x4, x1, x2)

inst_24475:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7f8000; valaddr_reg:x3; val_offset:73425*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73425*0 + 3*667*FLEN/8, x4, x1, x2)

inst_24476:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fc000; valaddr_reg:x3; val_offset:73428*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73428*0 + 3*668*FLEN/8, x4, x1, x2)

inst_24477:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fe000; valaddr_reg:x3; val_offset:73431*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73431*0 + 3*669*FLEN/8, x4, x1, x2)

inst_24478:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ff000; valaddr_reg:x3; val_offset:73434*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73434*0 + 3*670*FLEN/8, x4, x1, x2)

inst_24479:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ff800; valaddr_reg:x3; val_offset:73437*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73437*0 + 3*671*FLEN/8, x4, x1, x2)

inst_24480:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ffc00; valaddr_reg:x3; val_offset:73440*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73440*0 + 3*672*FLEN/8, x4, x1, x2)

inst_24481:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ffe00; valaddr_reg:x3; val_offset:73443*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73443*0 + 3*673*FLEN/8, x4, x1, x2)

inst_24482:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fff00; valaddr_reg:x3; val_offset:73446*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73446*0 + 3*674*FLEN/8, x4, x1, x2)

inst_24483:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fff80; valaddr_reg:x3; val_offset:73449*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73449*0 + 3*675*FLEN/8, x4, x1, x2)

inst_24484:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fffc0; valaddr_reg:x3; val_offset:73452*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73452*0 + 3*676*FLEN/8, x4, x1, x2)

inst_24485:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fffe0; valaddr_reg:x3; val_offset:73455*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73455*0 + 3*677*FLEN/8, x4, x1, x2)

inst_24486:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ffff0; valaddr_reg:x3; val_offset:73458*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73458*0 + 3*678*FLEN/8, x4, x1, x2)

inst_24487:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ffff8; valaddr_reg:x3; val_offset:73461*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73461*0 + 3*679*FLEN/8, x4, x1, x2)

inst_24488:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ffffc; valaddr_reg:x3; val_offset:73464*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73464*0 + 3*680*FLEN/8, x4, x1, x2)

inst_24489:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7ffffe; valaddr_reg:x3; val_offset:73467*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73467*0 + 3*681*FLEN/8, x4, x1, x2)

inst_24490:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72cedb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2cedb; op2val:0x0;
op3val:0xd7fffff; valaddr_reg:x3; val_offset:73470*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73470*0 + 3*682*FLEN/8, x4, x1, x2)

inst_24491:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e000000; valaddr_reg:x3; val_offset:73473*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73473*0 + 3*683*FLEN/8, x4, x1, x2)

inst_24492:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e000001; valaddr_reg:x3; val_offset:73476*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73476*0 + 3*684*FLEN/8, x4, x1, x2)

inst_24493:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e000003; valaddr_reg:x3; val_offset:73479*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73479*0 + 3*685*FLEN/8, x4, x1, x2)

inst_24494:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e000007; valaddr_reg:x3; val_offset:73482*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73482*0 + 3*686*FLEN/8, x4, x1, x2)

inst_24495:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e00000f; valaddr_reg:x3; val_offset:73485*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73485*0 + 3*687*FLEN/8, x4, x1, x2)

inst_24496:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e00001f; valaddr_reg:x3; val_offset:73488*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73488*0 + 3*688*FLEN/8, x4, x1, x2)

inst_24497:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e00003f; valaddr_reg:x3; val_offset:73491*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73491*0 + 3*689*FLEN/8, x4, x1, x2)

inst_24498:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e00007f; valaddr_reg:x3; val_offset:73494*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73494*0 + 3*690*FLEN/8, x4, x1, x2)

inst_24499:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e0000ff; valaddr_reg:x3; val_offset:73497*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73497*0 + 3*691*FLEN/8, x4, x1, x2)

inst_24500:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e0001ff; valaddr_reg:x3; val_offset:73500*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73500*0 + 3*692*FLEN/8, x4, x1, x2)

inst_24501:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e0003ff; valaddr_reg:x3; val_offset:73503*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73503*0 + 3*693*FLEN/8, x4, x1, x2)

inst_24502:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e0007ff; valaddr_reg:x3; val_offset:73506*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73506*0 + 3*694*FLEN/8, x4, x1, x2)

inst_24503:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e000fff; valaddr_reg:x3; val_offset:73509*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73509*0 + 3*695*FLEN/8, x4, x1, x2)

inst_24504:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e001fff; valaddr_reg:x3; val_offset:73512*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73512*0 + 3*696*FLEN/8, x4, x1, x2)

inst_24505:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e003fff; valaddr_reg:x3; val_offset:73515*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73515*0 + 3*697*FLEN/8, x4, x1, x2)

inst_24506:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e007fff; valaddr_reg:x3; val_offset:73518*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73518*0 + 3*698*FLEN/8, x4, x1, x2)

inst_24507:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e00ffff; valaddr_reg:x3; val_offset:73521*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73521*0 + 3*699*FLEN/8, x4, x1, x2)

inst_24508:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e01ffff; valaddr_reg:x3; val_offset:73524*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73524*0 + 3*700*FLEN/8, x4, x1, x2)

inst_24509:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e03ffff; valaddr_reg:x3; val_offset:73527*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73527*0 + 3*701*FLEN/8, x4, x1, x2)

inst_24510:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e07ffff; valaddr_reg:x3; val_offset:73530*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73530*0 + 3*702*FLEN/8, x4, x1, x2)

inst_24511:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e0fffff; valaddr_reg:x3; val_offset:73533*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73533*0 + 3*703*FLEN/8, x4, x1, x2)

inst_24512:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e1fffff; valaddr_reg:x3; val_offset:73536*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73536*0 + 3*704*FLEN/8, x4, x1, x2)

inst_24513:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e3fffff; valaddr_reg:x3; val_offset:73539*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73539*0 + 3*705*FLEN/8, x4, x1, x2)

inst_24514:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e400000; valaddr_reg:x3; val_offset:73542*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73542*0 + 3*706*FLEN/8, x4, x1, x2)

inst_24515:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e600000; valaddr_reg:x3; val_offset:73545*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73545*0 + 3*707*FLEN/8, x4, x1, x2)

inst_24516:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e700000; valaddr_reg:x3; val_offset:73548*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73548*0 + 3*708*FLEN/8, x4, x1, x2)

inst_24517:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e780000; valaddr_reg:x3; val_offset:73551*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73551*0 + 3*709*FLEN/8, x4, x1, x2)

inst_24518:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7c0000; valaddr_reg:x3; val_offset:73554*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73554*0 + 3*710*FLEN/8, x4, x1, x2)

inst_24519:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7e0000; valaddr_reg:x3; val_offset:73557*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73557*0 + 3*711*FLEN/8, x4, x1, x2)

inst_24520:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7f0000; valaddr_reg:x3; val_offset:73560*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73560*0 + 3*712*FLEN/8, x4, x1, x2)

inst_24521:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7f8000; valaddr_reg:x3; val_offset:73563*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73563*0 + 3*713*FLEN/8, x4, x1, x2)

inst_24522:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fc000; valaddr_reg:x3; val_offset:73566*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73566*0 + 3*714*FLEN/8, x4, x1, x2)

inst_24523:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fe000; valaddr_reg:x3; val_offset:73569*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73569*0 + 3*715*FLEN/8, x4, x1, x2)

inst_24524:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ff000; valaddr_reg:x3; val_offset:73572*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73572*0 + 3*716*FLEN/8, x4, x1, x2)

inst_24525:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ff800; valaddr_reg:x3; val_offset:73575*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73575*0 + 3*717*FLEN/8, x4, x1, x2)

inst_24526:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ffc00; valaddr_reg:x3; val_offset:73578*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73578*0 + 3*718*FLEN/8, x4, x1, x2)

inst_24527:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ffe00; valaddr_reg:x3; val_offset:73581*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73581*0 + 3*719*FLEN/8, x4, x1, x2)

inst_24528:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fff00; valaddr_reg:x3; val_offset:73584*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73584*0 + 3*720*FLEN/8, x4, x1, x2)

inst_24529:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fff80; valaddr_reg:x3; val_offset:73587*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73587*0 + 3*721*FLEN/8, x4, x1, x2)

inst_24530:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fffc0; valaddr_reg:x3; val_offset:73590*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73590*0 + 3*722*FLEN/8, x4, x1, x2)

inst_24531:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fffe0; valaddr_reg:x3; val_offset:73593*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73593*0 + 3*723*FLEN/8, x4, x1, x2)

inst_24532:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ffff0; valaddr_reg:x3; val_offset:73596*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73596*0 + 3*724*FLEN/8, x4, x1, x2)

inst_24533:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ffff8; valaddr_reg:x3; val_offset:73599*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73599*0 + 3*725*FLEN/8, x4, x1, x2)

inst_24534:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ffffc; valaddr_reg:x3; val_offset:73602*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73602*0 + 3*726*FLEN/8, x4, x1, x2)

inst_24535:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7ffffe; valaddr_reg:x3; val_offset:73605*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73605*0 + 3*727*FLEN/8, x4, x1, x2)

inst_24536:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7e7fffff; valaddr_reg:x3; val_offset:73608*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73608*0 + 3*728*FLEN/8, x4, x1, x2)

inst_24537:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f000001; valaddr_reg:x3; val_offset:73611*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73611*0 + 3*729*FLEN/8, x4, x1, x2)

inst_24538:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f000003; valaddr_reg:x3; val_offset:73614*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73614*0 + 3*730*FLEN/8, x4, x1, x2)

inst_24539:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f000007; valaddr_reg:x3; val_offset:73617*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73617*0 + 3*731*FLEN/8, x4, x1, x2)

inst_24540:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f199999; valaddr_reg:x3; val_offset:73620*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73620*0 + 3*732*FLEN/8, x4, x1, x2)

inst_24541:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f249249; valaddr_reg:x3; val_offset:73623*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73623*0 + 3*733*FLEN/8, x4, x1, x2)

inst_24542:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f333333; valaddr_reg:x3; val_offset:73626*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73626*0 + 3*734*FLEN/8, x4, x1, x2)

inst_24543:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:73629*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73629*0 + 3*735*FLEN/8, x4, x1, x2)

inst_24544:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:73632*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73632*0 + 3*736*FLEN/8, x4, x1, x2)

inst_24545:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f444444; valaddr_reg:x3; val_offset:73635*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73635*0 + 3*737*FLEN/8, x4, x1, x2)

inst_24546:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:73638*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73638*0 + 3*738*FLEN/8, x4, x1, x2)

inst_24547:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:73641*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73641*0 + 3*739*FLEN/8, x4, x1, x2)

inst_24548:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f666666; valaddr_reg:x3; val_offset:73644*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73644*0 + 3*740*FLEN/8, x4, x1, x2)

inst_24549:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:73647*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73647*0 + 3*741*FLEN/8, x4, x1, x2)

inst_24550:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:73650*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73650*0 + 3*742*FLEN/8, x4, x1, x2)

inst_24551:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:73653*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73653*0 + 3*743*FLEN/8, x4, x1, x2)

inst_24552:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x72fcb4 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x06dad8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef2fcb4; op2val:0x4006dad8;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:73656*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73656*0 + 3*744*FLEN/8, x4, x1, x2)

inst_24553:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32800000; valaddr_reg:x3; val_offset:73659*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73659*0 + 3*745*FLEN/8, x4, x1, x2)

inst_24554:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32800001; valaddr_reg:x3; val_offset:73662*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73662*0 + 3*746*FLEN/8, x4, x1, x2)

inst_24555:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32800003; valaddr_reg:x3; val_offset:73665*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73665*0 + 3*747*FLEN/8, x4, x1, x2)

inst_24556:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32800007; valaddr_reg:x3; val_offset:73668*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73668*0 + 3*748*FLEN/8, x4, x1, x2)

inst_24557:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3280000f; valaddr_reg:x3; val_offset:73671*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73671*0 + 3*749*FLEN/8, x4, x1, x2)

inst_24558:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3280001f; valaddr_reg:x3; val_offset:73674*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73674*0 + 3*750*FLEN/8, x4, x1, x2)

inst_24559:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3280003f; valaddr_reg:x3; val_offset:73677*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73677*0 + 3*751*FLEN/8, x4, x1, x2)

inst_24560:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3280007f; valaddr_reg:x3; val_offset:73680*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73680*0 + 3*752*FLEN/8, x4, x1, x2)

inst_24561:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x328000ff; valaddr_reg:x3; val_offset:73683*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73683*0 + 3*753*FLEN/8, x4, x1, x2)

inst_24562:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x328001ff; valaddr_reg:x3; val_offset:73686*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73686*0 + 3*754*FLEN/8, x4, x1, x2)

inst_24563:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x328003ff; valaddr_reg:x3; val_offset:73689*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73689*0 + 3*755*FLEN/8, x4, x1, x2)

inst_24564:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x328007ff; valaddr_reg:x3; val_offset:73692*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73692*0 + 3*756*FLEN/8, x4, x1, x2)

inst_24565:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32800fff; valaddr_reg:x3; val_offset:73695*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73695*0 + 3*757*FLEN/8, x4, x1, x2)

inst_24566:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32801fff; valaddr_reg:x3; val_offset:73698*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73698*0 + 3*758*FLEN/8, x4, x1, x2)

inst_24567:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32803fff; valaddr_reg:x3; val_offset:73701*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73701*0 + 3*759*FLEN/8, x4, x1, x2)

inst_24568:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32807fff; valaddr_reg:x3; val_offset:73704*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73704*0 + 3*760*FLEN/8, x4, x1, x2)

inst_24569:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3280ffff; valaddr_reg:x3; val_offset:73707*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73707*0 + 3*761*FLEN/8, x4, x1, x2)

inst_24570:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3281ffff; valaddr_reg:x3; val_offset:73710*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73710*0 + 3*762*FLEN/8, x4, x1, x2)

inst_24571:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3283ffff; valaddr_reg:x3; val_offset:73713*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73713*0 + 3*763*FLEN/8, x4, x1, x2)

inst_24572:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x3287ffff; valaddr_reg:x3; val_offset:73716*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73716*0 + 3*764*FLEN/8, x4, x1, x2)

inst_24573:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x328fffff; valaddr_reg:x3; val_offset:73719*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73719*0 + 3*765*FLEN/8, x4, x1, x2)

inst_24574:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x329fffff; valaddr_reg:x3; val_offset:73722*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73722*0 + 3*766*FLEN/8, x4, x1, x2)

inst_24575:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x738906 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x434693 and fs3 == 0 and fe3 == 0x65 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef38906; op2val:0x434693;
op3val:0x32bfffff; valaddr_reg:x3; val_offset:73725*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 73725*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7eeb0823,32,FLEN)
NAN_BOXED(0x8045b5b0,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800001,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800003,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800007,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780000f,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780001f,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780003f,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780007f,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78000ff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78001ff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78003ff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78007ff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800fff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7801fff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7803fff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7807fff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780ffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x781ffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x783ffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x787ffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78fffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x79fffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7bfffff,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c00000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e00000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f00000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f80000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc0000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fe0000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff0000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff8000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffc000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffe000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff000,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff800,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffc00,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffe00,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff00,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff80,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc0,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe0,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff0,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff8,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffffc,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffffe,32,FLEN)
NAN_BOXED(0x7eed14ed,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb000000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb000001,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb000003,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb000007,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb00000f,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb00001f,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb00003f,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb00007f,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb0000ff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb0001ff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb0003ff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb0007ff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb000fff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb001fff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb003fff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb007fff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb00ffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb01ffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb03ffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb07ffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb0fffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb1fffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb3fffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb400000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb600000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb700000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb780000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7c0000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7e0000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7f0000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7f8000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fc000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fe000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ff000,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ff800,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ffc00,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ffe00,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fff00,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fff80,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fffc0,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fffe0,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ffff0,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ffff8,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ffffc,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7ffffe,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xeb7fffff,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7eed982c,32,FLEN)
NAN_BOXED(0xc009ea6a,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c800000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c800001,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c800003,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c800007,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c80000f,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c80001f,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c80003f,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c80007f,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c8000ff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c8001ff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c8003ff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c8007ff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c800fff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c801fff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c803fff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c807fff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c80ffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c81ffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c83ffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c87ffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c8fffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3c9fffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cbfffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cc00000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3ce00000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cf00000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cf80000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfc0000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfe0000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cff0000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cff8000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffc000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffe000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfff000,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfff800,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfffc00,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfffe00,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffff00,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffff80,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffffc0,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffffe0,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfffff0,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfffff8,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfffffc,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cfffffe,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3cffffff,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7eee4f75,32,FLEN)
NAN_BOXED(0x44c02c,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000001,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000003,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000007,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00000f,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00001f,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00003f,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00007f,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0000ff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0001ff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0003ff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0007ff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000fff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf001fff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf003fff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf007fff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00ffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf01ffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf03ffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf07ffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0fffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf1fffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf3fffff,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf400000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf600000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf700000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf780000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7c0000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7e0000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7f0000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7f8000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fc000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fe000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ff000,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ff800,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffc00,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffe00,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fff00,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fff80,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffc0,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffe0,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffff0,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffff8,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffffc,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffffe,32,FLEN)
NAN_BOXED(0x7eeedcc4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000001,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000003,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000007,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00000f,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00001f,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00003f,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00007f,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0000ff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0001ff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0003ff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0007ff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000fff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c001fff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c003fff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c007fff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00ffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c01ffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c03ffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c07ffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0fffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c1fffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c3fffff,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c400000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c600000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c700000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c780000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7c0000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7e0000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7f0000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7f8000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fc000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fe000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ff000,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ff800,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffc00,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffe00,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fff00,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fff80,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fffc0,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fffe0,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffff0,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffff8,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffffc,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffffe,32,FLEN)
NAN_BOXED(0x7eef6431,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000001,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000003,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000007,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00000f,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00001f,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00003f,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00007f,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0000ff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0001ff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0003ff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0007ff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000fff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd001fff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd003fff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd007fff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00ffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd01ffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd03ffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd07ffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0fffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd1fffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd3fffff,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd400000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd600000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd700000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd780000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7c0000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7e0000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7f0000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7f8000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fc000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fe000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ff000,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ff800,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffc00,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffe00,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fff00,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fff80,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fffc0,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fffe0,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffff0,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffff8,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffffc,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffffe,32,FLEN)
NAN_BOXED(0x7ef0ab3f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff000000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff00000f,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff00001f,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff00003f,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff00007f,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff0000ff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff0001ff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff0003ff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff0007ff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff000fff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff001fff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff003fff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff007fff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff00ffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff01ffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff03ffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff07ffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff0fffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff1fffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff3fffff,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff400000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff600000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff700000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff780000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7c0000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7e0000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7f0000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7f8000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fc000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fe000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ff000,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ff800,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ffc00,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ffe00,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fff00,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fff80,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fffc0,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fffe0,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ffff0,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7ef0d256,32,FLEN)
NAN_BOXED(0xc0081147,32,FLEN)
NAN_BOXED(0xff7fffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd800000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd800001,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd800003,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd800007,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd80000f,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd80001f,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd80003f,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd80007f,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd8000ff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd8001ff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd8003ff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd8007ff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd800fff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd801fff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd803fff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd807fff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd80ffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd81ffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd83ffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd87ffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd8fffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbd9fffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdbfffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdc00000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbde00000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdf00000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdf80000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfc0000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfe0000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdff0000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdff8000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffc000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffe000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfff000,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfff800,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfffc00,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfffe00,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffff00,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffff80,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffffc0,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffffe0,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfffff0,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfffff8,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfffffc,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdfffffe,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbdffffff,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7ef1036e,32,FLEN)
NAN_BOXED(0x8043fac8,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed000000,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed000001,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed000003,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed000007,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed00000f,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed00001f,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed00003f,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed00007f,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed0000ff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed0001ff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed0003ff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed0007ff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed000fff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed001fff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed003fff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed007fff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed00ffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed01ffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed03ffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed07ffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed0fffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed1fffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed3fffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed400000,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed600000,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7f8000,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7ffc00,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7fff00,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
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NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7fffc0,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7fffe0,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7ffff0,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7ffff8,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7ffffc,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7ffffe,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xed7fffff,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7ef18162,32,FLEN)
NAN_BOXED(0xc007aea7,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000001,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000003,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000007,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800000f,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001f,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003f,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007f,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000ff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80001ff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80003ff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80007ff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000fff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8001fff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8003fff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8007fff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800ffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x801ffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x803ffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807ffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80fffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x81fffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x83fffff,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8400000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8600000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8700000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8780000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87c0000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87e0000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f0000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f8000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fc000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fe000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff000,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff800,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffc00,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffe00,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff00,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff80,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffc0,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffe0,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff0,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff8,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffc,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffe,32,FLEN)
NAN_BOXED(0x7ef1e834,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000001,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000003,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000007,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00000f,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00001f,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00003f,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00007f,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0000ff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0001ff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0003ff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0007ff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd000fff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd001fff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd003fff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd007fff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd00ffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd01ffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd03ffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd07ffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd0fffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd1fffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd3fffff,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd400000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd600000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd700000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd780000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7c0000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7e0000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7f0000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7f8000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fc000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fe000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ff000,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ff800,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffc00,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffe00,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fff00,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fff80,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fffc0,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fffe0,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffff0,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffff8,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffffc,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7ffffe,32,FLEN)
NAN_BOXED(0x7ef2cedb,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd7fffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e000000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e000001,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e000003,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e000007,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e00000f,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e00001f,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e00003f,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e00007f,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e0000ff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e0001ff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e0003ff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e0007ff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e000fff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e001fff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e003fff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e007fff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e00ffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e01ffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e03ffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e07ffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e0fffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e1fffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e3fffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e400000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e600000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e700000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e780000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7c0000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7e0000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7f0000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7f8000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fc000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fe000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ff000,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ff800,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ffc00,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ffe00,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fff00,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fff80,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fffc0,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fffe0,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ffff0,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ffff8,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ffffc,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7ffffe,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7e7fffff,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7ef2fcb4,32,FLEN)
NAN_BOXED(0x4006dad8,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32800000,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32800001,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32800003,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32800007,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3280000f,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3280001f,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3280003f,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3280007f,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x328000ff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x328001ff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x328003ff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x328007ff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32800fff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32801fff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32803fff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32807fff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3280ffff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3281ffff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3283ffff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x3287ffff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x328fffff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x329fffff,32,FLEN)
NAN_BOXED(0x7ef38906,32,FLEN)
NAN_BOXED(0x434693,32,FLEN)
NAN_BOXED(0x32bfffff,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
