
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd == rs3 != rs2, rs1==f31, rs2==f30, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f31; dest:f31; op1val:0x2a; op2val:0x3800;
op3val:0x2a; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f30, rs2==f31, rs3==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f31; op3:f29; dest:f30; op1val:0x33; op2val:0x3ebe;
op3val:0x54; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f30, f30, f31, f29, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f28, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f29; op2:f28; op3:f28; dest:f28; op1val:0x7; op2val:0x4000;
op3val:0x4000; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f28, f29, f28, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f29, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0de and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f28; op2:f29; op3:f27; dest:f27; op1val:0x45; op2val:0x34de;
op3val:0xd; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f27, f28, f29, f27, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f26, rs3==f30, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f27; op2:f26; op3:f30; dest:f26; op1val:0x2f; op2val:0x3fbe;
op3val:0x4b; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f26, f27, f26, f30, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 == rs2 == rs3 == rd, rs1==f25, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x210 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f25; op2:f25; op3:f25; dest:f25; op1val:0x8; op2val:0x8;
op3val:0x8; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f25, f25, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f24, rs3==f24, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f26; op2:f24; op3:f24; dest:f29; op1val:0x1c; op2val:0x40ed;
op3val:0x40ed; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f29, f26, f24, f24, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f23, rs2==f23, rs3==f26, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f23; op2:f23; op3:f26; dest:f23; op1val:0xc; op2val:0xc;
op3val:0x38; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f23, f23, f23, f26, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f22; op2:f22; op3:f22; dest:f24; op1val:0x36; op2val:0x36;
op3val:0x36; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f24, f22, f22, f22, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f23, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x039 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f21; op2:f21; op3:f23; dest:f22; op1val:0x1f; op2val:0x1f;
op3val:0xc; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f22, f21, f21, f23, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f20, rs2==f27, rs3==f20, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f20; op2:f27; op3:f20; dest:f21; op1val:0x47; op2val:0x3a15;
op3val:0x47; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f21, f20, f27, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f24, rs2==f19, rs3==f21, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x070 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f24; op2:f19; op3:f21; dest:f20; op1val:0x8; op2val:0x4870;
op3val:0x49; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f20, f24, f19, f21, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x240 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x10; op2val:0x3e40;
op3val:0x1d; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x051 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x335 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x51; op2val:0x3b35;
op3val:0x51; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2d3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x4b; op2val:0xaed3;
op3val:0x8; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x4a; op2val:0x38a6;
op3val:0x4b; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x078 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x33; op2val:0xbc78;
op3val:0x7; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x034 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x006 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x1d; op2val:0xc434;
op3val:0x6; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x29c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x012 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x48; op2val:0xc29c;
op3val:0x12; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x026 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x26; op2val:0xca06;
op3val:0x36; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x013 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x010 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x3c13; op2val:0x4010;
op3val:0x3c46; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x010 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x3c10; op2val:0x4015;
op3val:0x3c4a; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fc and fs3 == 0 and fe3 == 0x0f and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x3c28; op2val:0x3ffc;
op3val:0x3c48; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x3c58; op2val:0x3f7b;
op3val:0x3c18; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x3c0e; op2val:0x401f;
op3val:0x3c4b; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x3c4a; op2val:0x3fe0;
op3val:0x3c52; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x01e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x3c19; op2val:0x401e;
op3val:0x3c30; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x3c0d; op2val:0x4055;
op3val:0x3c47; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x3c5c; op2val:0x4025;
op3val:0x3c09; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x049 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0f and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x3c49; op2val:0x40ae;
op3val:0x3c08; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x050 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x207 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x3c50; op2val:0x2607;
op3val:0x3c1b; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x3c40; op2val:0x2d0f;
op3val:0x3c58; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x3c45; op2val:0x29f8;
op3val:0x3c37; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x23f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x3c29; op2val:0x2a3f;
op3val:0x3c3c; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x3c4b; op2val:0x2902;
op3val:0x3c3b; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x07 and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c2f; op2val:0x1eb1;
op3val:0x3c27; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c20; op2val:0xa8d9;
op3val:0x3c18; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x183 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c5a; op2val:0xad83;
op3val:0x3c20; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c0b; op2val:0xb1a0;
op3val:0x3c4a; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ae and fs3 == 0 and fe3 == 0x0f and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c27; op2val:0xb6ae;
op3val:0x3c44; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x40; op2val:0x39a0;
op3val:0x2c; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x131 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5e; op2val:0x3931;
op3val:0x3a; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x07c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x25; op2val:0x407c;
op3val:0x4e; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x10 and fm2 == 0x100 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xa; op2val:0x4100;
op3val:0x10; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x04d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x42; op2val:0x3c4d;
op3val:0x36; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x061 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x16; op2val:0x45e8;
op3val:0x61; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c; op2val:0x3fba;
op3val:0x14; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1cf and fs3 == 0 and fe3 == 0x00 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3f; op2val:0x41cf;
op3val:0x36; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x325 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6; op2val:0x5325;
op3val:0x56; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x14 and fm2 == 0x3a3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xa; op2val:0x53a3;
op3val:0x62; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x00e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x48; op2val:0x3c0e;
op3val:0x4a; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29; op2val:0x3c00;
op3val:0x2c; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x330 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x59; op2val:0x3730;
op3val:0x2d; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x040 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d; op2val:0x39b6;
op3val:0x40; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x07a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4b; op2val:0x387a;
op3val:0x3b; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x9; op2val:0xc0aa;
op3val:0xc; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x350 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x23; op2val:0xaf50;
op3val:0x3d; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5a; op2val:0xb7a4;
op3val:0x56; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x00 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x9; op2val:0xceea;
op3val:0x8; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x080 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5e; op2val:0xc480;
op3val:0x5a; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x28; op2val:0x4ee8;
op3val:0x53; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x37e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4a; op2val:0x4b7e;
op3val:0x58; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x13 and fm2 == 0x08d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3a; op2val:0x4c8d;
op3val:0x25; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x032 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c; op2val:0x49c9;
op3val:0x32; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x21d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x56; op2val:0x4a1d;
op3val:0x2d; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x179 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3; op2val:0x5d79;
op3val:0x3c; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 0 and fe2 == 0x13 and fm2 == 0x154 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e; op2val:0x4d54;
op3val:0x16; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f; op2val:0x49c2;
op3val:0xf; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x20e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x40; op2val:0x4a0e;
op3val:0x8; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1c; op2val:0x4d72;
op3val:0x63; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2ca and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x25; op2val:0xceca;
op3val:0x11; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x12 and fm2 == 0x134 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5f; op2val:0xc934;
op3val:0x20; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0be and fs3 == 0 and fe3 == 0x00 and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x33; op2val:0xccbe;
op3val:0x33; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x040 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3d8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x40; op2val:0xcbd8;
op3val:0xb; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x164 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x16; op2val:0xd164;
op3val:0x3a; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34; op2val:0xcc6c;
op3val:0x47; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x288 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x012 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x24; op2val:0xce88;
op3val:0x12; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x35b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x38; op2val:0xcb5b;
op3val:0x47; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x24; op2val:0xccb1;
op3val:0x5b; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x04e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36; op2val:0xc84e;
op3val:0x2e; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38b and fs3 == 0 and fe3 == 0x01 and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x458; op2val:0x3f8b;
op3val:0x431; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3db and fs3 == 0 and fe3 == 0x01 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x41e; op2val:0x3fdb;
op3val:0x414; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x40b; op2val:0x4002;
op3val:0x417; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x414; op2val:0x3ffe;
op3val:0x41e; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x01e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x455; op2val:0x3f8d;
op3val:0x41e; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x402; op2val:0x402d;
op3val:0x43f; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44c; op2val:0x3fc4;
op3val:0x418; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x02e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x025 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x422; op2val:0x402e;
op3val:0x425; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x088 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x401; op2val:0x4088;
op3val:0x413; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x436; op2val:0x40e0;
op3val:0x445; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0a8 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x430; op2val:0x2ca8;
op3val:0x44f; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x08c and fs3 == 0 and fe3 == 0x01 and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x449; op2val:0x288c;
op3val:0x429; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x011 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x139 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x411; op2val:0x2d39;
op3val:0x459; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x03a and fs3 == 0 and fe3 == 0x01 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x442; op2val:0x2c3a;
op3val:0x450; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x054 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x019 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x057 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x454; op2val:0x2c19;
op3val:0x457; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x09 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x45f; op2val:0xa5b8;
op3val:0x407; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03b and fs2 == 0 and fe2 == 0x09 and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x01 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x43b; op2val:0x25ac;
op3val:0x458; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x07f and fs3 == 0 and fe3 == 0x01 and fm3 == 0x033 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x448; op2val:0xac7f;
op3val:0x433; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x212 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x433; op2val:0xb212;
op3val:0x434; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x369 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x433; op2val:0xb769;
op3val:0x40e; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1e and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783e; op2val:0x41ce;
op3val:0x7852; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1b8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7834; op2val:0x41b8;
op3val:0x7808; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7819; op2val:0x41dd;
op3val:0x7809; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x781b; op2val:0x41ef;
op3val:0x7839; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7815; op2val:0x41e0;
op3val:0x780f; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782c; op2val:0x41d5;
op3val:0x784d; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x007 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7807; op2val:0x41dc;
op3val:0x780e; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7801; op2val:0x41e2;
op3val:0x7849; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x186 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7814; op2val:0x4186;
op3val:0x7845; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x780d; op2val:0x4106;
op3val:0x782f; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x362 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x004 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x784f; op2val:0xbb62;
op3val:0x7804; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x780a; op2val:0xbbb0;
op3val:0x781b; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x309 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x031 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x784f; op2val:0xbb09;
op3val:0x7831; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x052 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7814; op2val:0xbb26;
op3val:0x7852; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x347 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7821; op2val:0xbb47;
op3val:0x782d; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2da and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x784e; op2val:0xbada;
op3val:0x782f; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2f3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783d; op2val:0xbaf3;
op3val:0x7810; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x267 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x780f; op2val:0xba67;
op3val:0x783f; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x133 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783c; op2val:0xb933;
op3val:0x783e; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783e; op2val:0xb6f0;
op3val:0x7828; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2a; op2val:0x3800;
op3val:0x14; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7; op2val:0x4000;
op3val:0xa; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x210 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x041 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8; op2val:0x4a10;
op3val:0x41; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1c; op2val:0x40ed;
op3val:0x5; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xc; op2val:0x4baa;
op3val:0x38; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0e8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x009 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36; op2val:0x44e8;
op3val:0x9; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x039 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1f; op2val:0x4c39;
op3val:0xc; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x215 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x037 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x47; op2val:0x3a15;
op3val:0x37; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(42,16,FLEN)
NAN_BOXED(14336,16,FLEN)
NAN_BOXED(42,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(16062,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(16384,16,FLEN)
NAN_BOXED(16384,16,FLEN)
NAN_BOXED(69,16,FLEN)
NAN_BOXED(13534,16,FLEN)
NAN_BOXED(13,16,FLEN)
NAN_BOXED(47,16,FLEN)
NAN_BOXED(16318,16,FLEN)
NAN_BOXED(75,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(28,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(56,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(31,16,FLEN)
NAN_BOXED(31,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(14869,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(18544,16,FLEN)
NAN_BOXED(73,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(15936,16,FLEN)
NAN_BOXED(29,16,FLEN)
NAN_BOXED(81,16,FLEN)
NAN_BOXED(15157,16,FLEN)
NAN_BOXED(81,16,FLEN)
NAN_BOXED(75,16,FLEN)
NAN_BOXED(44755,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(14502,16,FLEN)
NAN_BOXED(75,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(48248,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(29,16,FLEN)
NAN_BOXED(50228,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(72,16,FLEN)
NAN_BOXED(49820,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(38,16,FLEN)
NAN_BOXED(51718,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(15379,16,FLEN)
NAN_BOXED(16400,16,FLEN)
NAN_BOXED(15430,16,FLEN)
NAN_BOXED(15376,16,FLEN)
NAN_BOXED(16405,16,FLEN)
NAN_BOXED(15434,16,FLEN)
NAN_BOXED(15400,16,FLEN)
NAN_BOXED(16380,16,FLEN)
NAN_BOXED(15432,16,FLEN)
NAN_BOXED(15448,16,FLEN)
NAN_BOXED(16251,16,FLEN)
NAN_BOXED(15384,16,FLEN)
NAN_BOXED(15374,16,FLEN)
NAN_BOXED(16415,16,FLEN)
NAN_BOXED(15435,16,FLEN)
NAN_BOXED(15434,16,FLEN)
NAN_BOXED(16352,16,FLEN)
NAN_BOXED(15442,16,FLEN)
NAN_BOXED(15385,16,FLEN)
NAN_BOXED(16414,16,FLEN)
NAN_BOXED(15408,16,FLEN)
NAN_BOXED(15373,16,FLEN)
NAN_BOXED(16469,16,FLEN)
NAN_BOXED(15431,16,FLEN)
NAN_BOXED(15452,16,FLEN)
NAN_BOXED(16421,16,FLEN)
NAN_BOXED(15369,16,FLEN)
NAN_BOXED(15433,16,FLEN)
NAN_BOXED(16558,16,FLEN)
NAN_BOXED(15368,16,FLEN)
NAN_BOXED(15440,16,FLEN)
NAN_BOXED(9735,16,FLEN)
NAN_BOXED(15387,16,FLEN)
NAN_BOXED(15424,16,FLEN)
NAN_BOXED(11535,16,FLEN)
NAN_BOXED(15448,16,FLEN)
NAN_BOXED(15429,16,FLEN)
NAN_BOXED(10744,16,FLEN)
NAN_BOXED(15415,16,FLEN)
NAN_BOXED(15401,16,FLEN)
NAN_BOXED(10815,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(15435,16,FLEN)
NAN_BOXED(10498,16,FLEN)
NAN_BOXED(15419,16,FLEN)
NAN_BOXED(15407,16,FLEN)
NAN_BOXED(7857,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(15392,16,FLEN)
NAN_BOXED(43225,16,FLEN)
NAN_BOXED(15384,16,FLEN)
NAN_BOXED(15450,16,FLEN)
NAN_BOXED(44419,16,FLEN)
NAN_BOXED(15392,16,FLEN)
NAN_BOXED(15371,16,FLEN)
NAN_BOXED(45472,16,FLEN)
NAN_BOXED(15434,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(46766,16,FLEN)
NAN_BOXED(15428,16,FLEN)
NAN_BOXED(64,16,FLEN)
NAN_BOXED(14752,16,FLEN)
NAN_BOXED(44,16,FLEN)
NAN_BOXED(94,16,FLEN)
NAN_BOXED(14641,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(37,16,FLEN)
NAN_BOXED(16508,16,FLEN)
NAN_BOXED(78,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(16640,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(66,16,FLEN)
NAN_BOXED(15437,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(17896,16,FLEN)
NAN_BOXED(97,16,FLEN)
NAN_BOXED(44,16,FLEN)
NAN_BOXED(16314,16,FLEN)
NAN_BOXED(20,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(16847,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(21285,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(21411,16,FLEN)
NAN_BOXED(98,16,FLEN)
NAN_BOXED(72,16,FLEN)
NAN_BOXED(15374,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(41,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(44,16,FLEN)
NAN_BOXED(89,16,FLEN)
NAN_BOXED(14128,16,FLEN)
NAN_BOXED(45,16,FLEN)
NAN_BOXED(77,16,FLEN)
NAN_BOXED(14774,16,FLEN)
NAN_BOXED(64,16,FLEN)
NAN_BOXED(75,16,FLEN)
NAN_BOXED(14458,16,FLEN)
NAN_BOXED(59,16,FLEN)
NAN_BOXED(9,16,FLEN)
NAN_BOXED(49322,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(35,16,FLEN)
NAN_BOXED(44880,16,FLEN)
NAN_BOXED(61,16,FLEN)
NAN_BOXED(90,16,FLEN)
NAN_BOXED(47012,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(9,16,FLEN)
NAN_BOXED(52970,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(94,16,FLEN)
NAN_BOXED(50304,16,FLEN)
NAN_BOXED(90,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(20200,16,FLEN)
NAN_BOXED(83,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(19326,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(19597,16,FLEN)
NAN_BOXED(37,16,FLEN)
NAN_BOXED(92,16,FLEN)
NAN_BOXED(18889,16,FLEN)
NAN_BOXED(50,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(18973,16,FLEN)
NAN_BOXED(45,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(23929,16,FLEN)
NAN_BOXED(60,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(19796,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(18882,16,FLEN)
NAN_BOXED(15,16,FLEN)
NAN_BOXED(64,16,FLEN)
NAN_BOXED(18958,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(28,16,FLEN)
NAN_BOXED(19826,16,FLEN)
NAN_BOXED(99,16,FLEN)
NAN_BOXED(37,16,FLEN)
NAN_BOXED(52938,16,FLEN)
NAN_BOXED(17,16,FLEN)
NAN_BOXED(95,16,FLEN)
NAN_BOXED(51508,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(52414,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(64,16,FLEN)
NAN_BOXED(52184,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(53604,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(52,16,FLEN)
NAN_BOXED(52332,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(36,16,FLEN)
NAN_BOXED(52872,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(56,16,FLEN)
NAN_BOXED(52059,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(36,16,FLEN)
NAN_BOXED(52401,16,FLEN)
NAN_BOXED(91,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(51278,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(1112,16,FLEN)
NAN_BOXED(16267,16,FLEN)
NAN_BOXED(1073,16,FLEN)
NAN_BOXED(1054,16,FLEN)
NAN_BOXED(16347,16,FLEN)
NAN_BOXED(1044,16,FLEN)
NAN_BOXED(1035,16,FLEN)
NAN_BOXED(16386,16,FLEN)
NAN_BOXED(1047,16,FLEN)
NAN_BOXED(1044,16,FLEN)
NAN_BOXED(16382,16,FLEN)
NAN_BOXED(1054,16,FLEN)
NAN_BOXED(1109,16,FLEN)
NAN_BOXED(16269,16,FLEN)
NAN_BOXED(1054,16,FLEN)
NAN_BOXED(1026,16,FLEN)
NAN_BOXED(16429,16,FLEN)
NAN_BOXED(1087,16,FLEN)
NAN_BOXED(1100,16,FLEN)
NAN_BOXED(16324,16,FLEN)
NAN_BOXED(1048,16,FLEN)
NAN_BOXED(1058,16,FLEN)
NAN_BOXED(16430,16,FLEN)
NAN_BOXED(1061,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(16520,16,FLEN)
NAN_BOXED(1043,16,FLEN)
NAN_BOXED(1078,16,FLEN)
NAN_BOXED(16608,16,FLEN)
NAN_BOXED(1093,16,FLEN)
NAN_BOXED(1072,16,FLEN)
NAN_BOXED(11432,16,FLEN)
NAN_BOXED(1103,16,FLEN)
NAN_BOXED(1097,16,FLEN)
NAN_BOXED(10380,16,FLEN)
NAN_BOXED(1065,16,FLEN)
NAN_BOXED(1041,16,FLEN)
NAN_BOXED(11577,16,FLEN)
NAN_BOXED(1113,16,FLEN)
NAN_BOXED(1090,16,FLEN)
NAN_BOXED(11322,16,FLEN)
NAN_BOXED(1104,16,FLEN)
NAN_BOXED(1108,16,FLEN)
NAN_BOXED(11289,16,FLEN)
NAN_BOXED(1111,16,FLEN)
NAN_BOXED(1119,16,FLEN)
NAN_BOXED(42424,16,FLEN)
NAN_BOXED(1031,16,FLEN)
NAN_BOXED(1083,16,FLEN)
NAN_BOXED(9644,16,FLEN)
NAN_BOXED(1112,16,FLEN)
NAN_BOXED(1096,16,FLEN)
NAN_BOXED(44159,16,FLEN)
NAN_BOXED(1075,16,FLEN)
NAN_BOXED(1075,16,FLEN)
NAN_BOXED(45586,16,FLEN)
NAN_BOXED(1076,16,FLEN)
NAN_BOXED(1075,16,FLEN)
NAN_BOXED(46953,16,FLEN)
NAN_BOXED(1038,16,FLEN)
NAN_BOXED(30782,16,FLEN)
NAN_BOXED(16846,16,FLEN)
NAN_BOXED(30802,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(16824,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(30745,16,FLEN)
NAN_BOXED(16861,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(16879,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(30741,16,FLEN)
NAN_BOXED(16864,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(30764,16,FLEN)
NAN_BOXED(16853,16,FLEN)
NAN_BOXED(30797,16,FLEN)
NAN_BOXED(30727,16,FLEN)
NAN_BOXED(16860,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(16866,16,FLEN)
NAN_BOXED(30793,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(16774,16,FLEN)
NAN_BOXED(30789,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(16646,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(47970,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(48048,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(47881,16,FLEN)
NAN_BOXED(30769,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(47910,16,FLEN)
NAN_BOXED(30802,16,FLEN)
NAN_BOXED(30753,16,FLEN)
NAN_BOXED(47943,16,FLEN)
NAN_BOXED(30765,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(47834,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(30781,16,FLEN)
NAN_BOXED(47859,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(47719,16,FLEN)
NAN_BOXED(30783,16,FLEN)
NAN_BOXED(30780,16,FLEN)
NAN_BOXED(47411,16,FLEN)
NAN_BOXED(30782,16,FLEN)
NAN_BOXED(30782,16,FLEN)
NAN_BOXED(46832,16,FLEN)
NAN_BOXED(30760,16,FLEN)
NAN_BOXED(42,16,FLEN)
NAN_BOXED(14336,16,FLEN)
NAN_BOXED(20,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(16384,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(18960,16,FLEN)
NAN_BOXED(65,16,FLEN)
NAN_BOXED(28,16,FLEN)
NAN_BOXED(16621,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(19370,16,FLEN)
NAN_BOXED(56,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(17640,16,FLEN)
NAN_BOXED(9,16,FLEN)
NAN_BOXED(31,16,FLEN)
NAN_BOXED(19513,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(14869,16,FLEN)
NAN_BOXED(55,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
