
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b3 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b3)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rd == rs2 == rs3 != rs1, rs1==f19, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f19; op2:f25; op3:f25; dest:f25; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x44b76ad3; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f25, f19, f25, f25, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f23, rs2==f23, rs3==f5, rd==f24,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f23; op2:f23; op3:f5; dest:f24; op1val:0x79b19f1b; op2val:0x79b19f1b;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f24, f23, f23, f5, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f24, rs2==f8, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f24; op2:f8; op3:f31; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f24, f8, f31, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f31, rs2==f27, rs3==f27, rd==f13,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f31; op2:f27; op3:f27; dest:f13; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x44b76ad3; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f13, f31, f27, f27, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f5, rs2==f22, rs3==f29, rd==f5,fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f5; op2:f22; op3:f29; dest:f5; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f5, f5, f22, f29, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f18, rs2==f6, rs3==f30, rd==f4,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f18; op2:f6; op3:f30; dest:f4; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f4, f18, f6, f30, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f12, rs2==f10, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f12; op2:f10; op3:f8; dest:f10; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f10, f12, f10, f8, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rd != rs3, rs1==f15, rs2==f15, rs3==f16, rd==f15,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f15; op2:f15; op3:f16; dest:f15; op1val:0x7a96be52; op2val:0x7a96be52;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f15, f15, f15, f16, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f11, rs2==f1, rs3==f11, rd==f8,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f11; op2:f1; op3:f11; dest:f8; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7a96be52; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f8, f11, f1, f11, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rd == rs3 != rs2, rs1==f3, rs2==f29, rs3==f3, rd==f3,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f3; op2:f29; op3:f3; dest:f3; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7a96be52; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f3, f3, f29, f3, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs2 == rs3 != rd, rs1==f13, rs2==f13, rs3==f13, rd==f29,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f13; op2:f13; op3:f13; dest:f29; op1val:0x7c6d92ab; op2val:0x7c6d92ab;
op3val:0x7c6d92ab; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f29, f13, f13, f13, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rs2 == rs3 == rd, rs1==f21, rs2==f21, rs3==f21, rd==f21,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f21; op2:f21; op3:f21; dest:f21; op1val:0x7c6d92ab; op2val:0x7c6d92ab;
op3val:0x7c6d92ab; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f21, f21, f21, f21, dyn, 32, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f26, rs2==f12, rs3==f14, rd==f17,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f26; op2:f12; op3:f14; dest:f17; op1val:0x7c6d92ab; op2val:0x41dc039b;
op3val:0x7ecc2d63; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f17, f26, f12, f14, dyn, 64, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f1, rs2==f31, rs3==f26, rd==f6,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f1; op2:f31; op3:f26; dest:f6; op1val:0x7c6d92ab; op2val:0x41dc039b;
op3val:0x7ecc2d63; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f6, f1, f31, f26, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f29, rs2==f24, rs3==f18, rd==f28,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f29; op2:f24; op3:f18; dest:f28; op1val:0x7c6d92ab; op2val:0x41dc039b;
op3val:0x7ecc2d63; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f28, f29, f24, f18, dyn, 128, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f7, rs2==f17, rs3==f2, rd==f12,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2c1d45 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x038dbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x30e48e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f7; op2:f17; op3:f2; dest:f12; op1val:0x7cac1d45; op2val:0x42038dbf;
op3val:0x7f30e48e; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f12, f7, f17, f2, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f17, rs2==f30, rs3==f1, rd==f26,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2c1d45 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x038dbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x30e48e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f17; op2:f30; op3:f1; dest:f26; op1val:0x7cac1d45; op2val:0x42038dbf;
op3val:0x7f30e48e; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f26, f17, f30, f1, dyn, 32, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f20, rs2==f14, rs3==f7, rd==f27,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2c1d45 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x038dbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x30e48e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f20; op2:f14; op3:f7; dest:f27; op1val:0x7cac1d45; op2val:0x42038dbf;
op3val:0x7f30e48e; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f27, f20, f14, f7, dyn, 64, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f9, rs2==f26, rs3==f0, rd==f1,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2c1d45 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x038dbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x30e48e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f9; op2:f26; op3:f0; dest:f1; op1val:0x7cac1d45; op2val:0x42038dbf;
op3val:0x7f30e48e; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f1, f9, f26, f0, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f28, rs2==f16, rs3==f9, rd==f7,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2c1d45 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x038dbf and fs3 == 0 and fe3 == 0xfe and fm3 == 0x30e48e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f28; op2:f16; op3:f9; dest:f7; op1val:0x7cac1d45; op2val:0x42038dbf;
op3val:0x7f30e48e; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f7, f28, f16, f9, dyn, 128, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f25, rs2==f4, rs3==f19, rd==f0,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f25; op2:f4; op3:f19; dest:f0; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f0, f25, f4, f19, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f6, rs2==f19, rs3==f22, rd==f9,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f6; op2:f19; op3:f22; dest:f9; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f9, f6, f19, f22, dyn, 32, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f22, rs2==f11, rs3==f20, rd==f23,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f22; op2:f11; op3:f20; dest:f23; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f23, f22, f11, f20, dyn, 64, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f16, rs2==f28, rs3==f24, rd==f18,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f16; op2:f28; op3:f24; dest:f18; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f18, f16, f28, f24, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f4, rs2==f3, rs3==f15, rd==f22,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2e9fe8 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x4b6f55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0ac4bf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f4; op2:f3; op3:f15; dest:f22; op1val:0x7cae9fe8; op2val:0x414b6f55;
op3val:0x7e8ac4bf; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f22, f4, f3, f15, dyn, 128, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f30, rs2==f18, rs3==f6, rd==f16,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x378e9e and fs2 == 0 and fe2 == 0x84 and fm2 == 0x05090e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ec72e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f18; op3:f6; dest:f16; op1val:0x7cb78e9e; op2val:0x4205090e;
op3val:0x7f3ec72e; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f16, f30, f18, f6, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f10, rs2==f7, rs3==f4, rd==f2,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x378e9e and fs2 == 0 and fe2 == 0x84 and fm2 == 0x05090e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ec72e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f10; op2:f7; op3:f4; dest:f2; op1val:0x7cb78e9e; op2val:0x4205090e;
op3val:0x7f3ec72e; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f2, f10, f7, f4, dyn, 32, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f14, rs2==f5, rs3==f17, rd==f30,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x378e9e and fs2 == 0 and fe2 == 0x84 and fm2 == 0x05090e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ec72e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f14; op2:f5; op3:f17; dest:f30; op1val:0x7cb78e9e; op2val:0x4205090e;
op3val:0x7f3ec72e; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f30, f14, f5, f17, dyn, 64, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f8, rs2==f2, rs3==f12, rd==f11,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x378e9e and fs2 == 0 and fe2 == 0x84 and fm2 == 0x05090e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ec72e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f8; op2:f2; op3:f12; dest:f11; op1val:0x7cb78e9e; op2val:0x4205090e;
op3val:0x7f3ec72e; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f11, f8, f2, f12, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f27, rs2==f0, rs3==f23, rd==f20,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x378e9e and fs2 == 0 and fe2 == 0x84 and fm2 == 0x05090e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ec72e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f27; op2:f0; op3:f23; dest:f20; op1val:0x7cb78e9e; op2val:0x4205090e;
op3val:0x7f3ec72e; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f20, f27, f0, f23, dyn, 128, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f2, rs2==f20, rs3==f10, rd==f19,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x39031d and fs2 == 0 and fe2 == 0x83 and fm2 == 0x4d83ab and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1486a7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f2; op2:f20; op3:f10; dest:f19; op1val:0x7cb9031d; op2val:0x41cd83ab;
op3val:0x7f1486a7; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f19, f2, f20, f10, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f0, rs2==f9, rs3==f28, rd==f14,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x39031d and fs2 == 0 and fe2 == 0x83 and fm2 == 0x4d83ab and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1486a7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f0; op2:f9; op3:f28; dest:f14; op1val:0x7cb9031d; op2val:0x41cd83ab;
op3val:0x7f1486a7; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f14, f0, f9, f28, dyn, 32, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x39031d and fs2 == 0 and fe2 == 0x83 and fm2 == 0x4d83ab and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1486a7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cb9031d; op2val:0x41cd83ab;
op3val:0x7f1486a7; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x39031d and fs2 == 0 and fe2 == 0x83 and fm2 == 0x4d83ab and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1486a7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cb9031d; op2val:0x41cd83ab;
op3val:0x7f1486a7; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x39031d and fs2 == 0 and fe2 == 0x83 and fm2 == 0x4d83ab and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1486a7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cb9031d; op2val:0x41cd83ab;
op3val:0x7f1486a7; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x3b3e27 and fs2 == 0 and fe2 == 0x83 and fm2 == 0x09ecfa and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49c32f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cbb3e27; op2val:0x4189ecfa;
op3val:0x7ec9c32f; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x3b3e27 and fs2 == 0 and fe2 == 0x83 and fm2 == 0x09ecfa and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49c32f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cbb3e27; op2val:0x4189ecfa;
op3val:0x7ec9c32f; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x3b3e27 and fs2 == 0 and fe2 == 0x83 and fm2 == 0x09ecfa and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49c32f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cbb3e27; op2val:0x4189ecfa;
op3val:0x7ec9c32f; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x3b3e27 and fs2 == 0 and fe2 == 0x83 and fm2 == 0x09ecfa and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49c32f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cbb3e27; op2val:0x4189ecfa;
op3val:0x7ec9c32f; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x3b3e27 and fs2 == 0 and fe2 == 0x83 and fm2 == 0x09ecfa and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49c32f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cbb3e27; op2val:0x4189ecfa;
op3val:0x7ec9c32f; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x45b82c and fs2 == 0 and fe2 == 0x83 and fm2 == 0x06ed1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x506b12 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc5b82c; op2val:0x4186ed1d;
op3val:0x7ed06b12; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x45b82c and fs2 == 0 and fe2 == 0x83 and fm2 == 0x06ed1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x506b12 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc5b82c; op2val:0x4186ed1d;
op3val:0x7ed06b12; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x45b82c and fs2 == 0 and fe2 == 0x83 and fm2 == 0x06ed1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x506b12 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc5b82c; op2val:0x4186ed1d;
op3val:0x7ed06b12; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x45b82c and fs2 == 0 and fe2 == 0x83 and fm2 == 0x06ed1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x506b12 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc5b82c; op2val:0x4186ed1d;
op3val:0x7ed06b12; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x45b82c and fs2 == 0 and fe2 == 0x83 and fm2 == 0x06ed1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x506b12 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc5b82c; op2val:0x4186ed1d;
op3val:0x7ed06b12; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x48fcb3 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298476 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0516d1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc8fcb3; op2val:0x40a98476;
op3val:0x7e0516d1; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x48fcb3 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298476 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0516d1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc8fcb3; op2val:0x40a98476;
op3val:0x7e0516d1; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x48fcb3 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298476 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0516d1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc8fcb3; op2val:0x40a98476;
op3val:0x7e0516d1; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x48fcb3 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298476 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0516d1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc8fcb3; op2val:0x40a98476;
op3val:0x7e0516d1; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x48fcb3 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298476 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0516d1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc8fcb3; op2val:0x40a98476;
op3val:0x7e0516d1; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x49296d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x336a25 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0cfb60 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc9296d; op2val:0x41336a25;
op3val:0x7e8cfb60; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x49296d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x336a25 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0cfb60 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc9296d; op2val:0x41336a25;
op3val:0x7e8cfb60; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x49296d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x336a25 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0cfb60 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc9296d; op2val:0x41336a25;
op3val:0x7e8cfb60; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x49296d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x336a25 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0cfb60 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc9296d; op2val:0x41336a25;
op3val:0x7e8cfb60; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x49296d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x336a25 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0cfb60 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cc9296d; op2val:0x41336a25;
op3val:0x7e8cfb60; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x74f85a and fs2 == 0 and fe2 == 0x83 and fm2 == 0x184854 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11b8ad and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cf4f85a; op2val:0x41984854;
op3val:0x7f11b8ad; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x74f85a and fs2 == 0 and fe2 == 0x83 and fm2 == 0x184854 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11b8ad and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cf4f85a; op2val:0x41984854;
op3val:0x7f11b8ad; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x74f85a and fs2 == 0 and fe2 == 0x83 and fm2 == 0x184854 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11b8ad and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cf4f85a; op2val:0x41984854;
op3val:0x7f11b8ad; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x74f85a and fs2 == 0 and fe2 == 0x83 and fm2 == 0x184854 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11b8ad and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cf4f85a; op2val:0x41984854;
op3val:0x7f11b8ad; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x74f85a and fs2 == 0 and fe2 == 0x83 and fm2 == 0x184854 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11b8ad and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cf4f85a; op2val:0x41984854;
op3val:0x7f11b8ad; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x255773 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7b6dc7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2263a5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d255773; op2val:0x40fb6dc7;
op3val:0x7ea263a5; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x43983d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x491608 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a35e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d43983d; op2val:0x41491608;
op3val:0x7f19a35e; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x43983d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x491608 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a35e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d43983d; op2val:0x41491608;
op3val:0x7f19a35e; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x43983d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x491608 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a35e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d43983d; op2val:0x41491608;
op3val:0x7f19a35e; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x43983d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x491608 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a35e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d43983d; op2val:0x41491608;
op3val:0x7f19a35e; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x43983d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x491608 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a35e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d43983d; op2val:0x41491608;
op3val:0x7f19a35e; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4cf955 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7c4412 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x49fbf1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d4cf955; op2val:0x3ffc4412;
op3val:0x7dc9fbf1; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4cf955 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7c4412 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x49fbf1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d4cf955; op2val:0x3ffc4412;
op3val:0x7dc9fbf1; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4cf955 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7c4412 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x49fbf1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d4cf955; op2val:0x3ffc4412;
op3val:0x7dc9fbf1; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4cf955 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7c4412 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x49fbf1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d4cf955; op2val:0x3ffc4412;
op3val:0x7dc9fbf1; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4cf955 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7c4412 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x49fbf1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d4cf955; op2val:0x3ffc4412;
op3val:0x7dc9fbf1; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x512a61 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x1b3a11 and fs3 == 0 and fe3 == 0xf5 and fm3 == 0x7da835 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d512a61; op2val:0x3d1b3a11;
op3val:0x7afda835; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x512a61 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x1b3a11 and fs3 == 0 and fe3 == 0xf5 and fm3 == 0x7da835 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d512a61; op2val:0x3d1b3a11;
op3val:0x7afda835; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x512a61 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x1b3a11 and fs3 == 0 and fe3 == 0xf5 and fm3 == 0x7da835 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d512a61; op2val:0x3d1b3a11;
op3val:0x7afda835; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x512a61 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x1b3a11 and fs3 == 0 and fe3 == 0xf5 and fm3 == 0x7da835 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d512a61; op2val:0x3d1b3a11;
op3val:0x7afda835; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x512a61 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x1b3a11 and fs3 == 0 and fe3 == 0xf5 and fm3 == 0x7da835 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d512a61; op2val:0x3d1b3a11;
op3val:0x7afda835; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x583349 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5c315d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x39f5c4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d583349; op2val:0x3fdc315d;
op3val:0x7db9f5c4; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x583349 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5c315d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x39f5c4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d583349; op2val:0x3fdc315d;
op3val:0x7db9f5c4; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x583349 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5c315d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x39f5c4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d583349; op2val:0x3fdc315d;
op3val:0x7db9f5c4; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x583349 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5c315d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x39f5c4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d583349; op2val:0x3fdc315d;
op3val:0x7db9f5c4; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x583349 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5c315d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x39f5c4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d583349; op2val:0x3fdc315d;
op3val:0x7db9f5c4; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x633d35 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x611178 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x47c84e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d633d35; op2val:0x40e11178;
op3val:0x7ec7c84e; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x633d35 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x611178 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x47c84e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d633d35; op2val:0x40e11178;
op3val:0x7ec7c84e; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x633d35 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x611178 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x47c84e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d633d35; op2val:0x40e11178;
op3val:0x7ec7c84e; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x633d35 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x611178 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x47c84e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d633d35; op2val:0x40e11178;
op3val:0x7ec7c84e; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x633d35 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x611178 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x47c84e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d633d35; op2val:0x40e11178;
op3val:0x7ec7c84e; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0052ab and fs2 == 0 and fe2 == 0x81 and fm2 == 0x6cc2eb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6d5bd5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8052ab; op2val:0x40ecc2eb;
op3val:0x7eed5bd5; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0052ab and fs2 == 0 and fe2 == 0x81 and fm2 == 0x6cc2eb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6d5bd5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8052ab; op2val:0x40ecc2eb;
op3val:0x7eed5bd5; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0052ab and fs2 == 0 and fe2 == 0x81 and fm2 == 0x6cc2eb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6d5bd5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8052ab; op2val:0x40ecc2eb;
op3val:0x7eed5bd5; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0052ab and fs2 == 0 and fe2 == 0x81 and fm2 == 0x6cc2eb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6d5bd5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8052ab; op2val:0x40ecc2eb;
op3val:0x7eed5bd5; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0052ab and fs2 == 0 and fe2 == 0x81 and fm2 == 0x6cc2eb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6d5bd5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8052ab; op2val:0x40ecc2eb;
op3val:0x7eed5bd5; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x038c5d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1883f4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1cbe4b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d838c5d; op2val:0x411883f4;
op3val:0x7f1cbe4b; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x038c5d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1883f4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1cbe4b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d838c5d; op2val:0x411883f4;
op3val:0x7f1cbe4b; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x038c5d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1883f4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1cbe4b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d838c5d; op2val:0x411883f4;
op3val:0x7f1cbe4b; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x038c5d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1883f4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1cbe4b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d838c5d; op2val:0x411883f4;
op3val:0x7f1cbe4b; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x038c5d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1883f4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1cbe4b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d838c5d; op2val:0x411883f4;
op3val:0x7f1cbe4b; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x051fb7 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34eb67 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c296d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d851fb7; op2val:0x4134eb67;
op3val:0x7f3c296d; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x051fb7 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34eb67 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c296d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d851fb7; op2val:0x4134eb67;
op3val:0x7f3c296d; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x051fb7 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34eb67 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c296d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d851fb7; op2val:0x4134eb67;
op3val:0x7f3c296d; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x051fb7 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34eb67 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c296d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d851fb7; op2val:0x4134eb67;
op3val:0x7f3c296d; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x051fb7 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x34eb67 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c296d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d851fb7; op2val:0x4134eb67;
op3val:0x7f3c296d; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0f0e02 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x097bec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19a77e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8f0e02; op2val:0x41097bec;
op3val:0x7f19a77e; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0fe409 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4b5f3b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x649eb5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8fe409; op2val:0x40cb5f3b;
op3val:0x7ee49eb5; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0fe409 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4b5f3b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x649eb5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8fe409; op2val:0x40cb5f3b;
op3val:0x7ee49eb5; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0fe409 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4b5f3b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x649eb5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8fe409; op2val:0x40cb5f3b;
op3val:0x7ee49eb5; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0fe409 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4b5f3b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x649eb5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8fe409; op2val:0x40cb5f3b;
op3val:0x7ee49eb5; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0fe409 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4b5f3b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x649eb5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d8fe409; op2val:0x40cb5f3b;
op3val:0x7ee49eb5; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x100bf1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x068d67 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x176ba2 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d900bf1; op2val:0x40068d67;
op3val:0x7e176ba2; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6aee21 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0d2a0f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d31d; op2val:0x406aee21;
op3val:0x7e8d2a0f; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6aee21 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0d2a0f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d31d; op2val:0x406aee21;
op3val:0x7e8d2a0f; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6aee21 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0d2a0f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d31d; op2val:0x406aee21;
op3val:0x7e8d2a0f; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6aee21 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0d2a0f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d31d; op2val:0x406aee21;
op3val:0x7e8d2a0f; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6aee21 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0d2a0f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d31d; op2val:0x406aee21;
op3val:0x7e8d2a0f; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d68e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x674db3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0aff4b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d68e; op2val:0x40674db3;
op3val:0x7e8aff4b; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d68e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x674db3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0aff4b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d68e; op2val:0x40674db3;
op3val:0x7e8aff4b; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d68e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x674db3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0aff4b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d68e; op2val:0x40674db3;
op3val:0x7e8aff4b; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d68e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x674db3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0aff4b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d68e; op2val:0x40674db3;
op3val:0x7e8aff4b; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x19d68e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x674db3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0aff4b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d99d68e; op2val:0x40674db3;
op3val:0x7e8aff4b; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1c90a0 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x032bc4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20718c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d9c90a0; op2val:0x41032bc4;
op3val:0x7f20718c; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1c90a0 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x032bc4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20718c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d9c90a0; op2val:0x41032bc4;
op3val:0x7f20718c; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1c90a0 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x032bc4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20718c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d9c90a0; op2val:0x41032bc4;
op3val:0x7f20718c; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1c90a0 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x032bc4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20718c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d9c90a0; op2val:0x41032bc4;
op3val:0x7f20718c; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1c90a0 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x032bc4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20718c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7d9c90a0; op2val:0x41032bc4;
op3val:0x7f20718c; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x21f156 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x43f0a5 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77e620 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da1f156; op2val:0x40c3f0a5;
op3val:0x7ef7e620; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x21f156 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x43f0a5 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77e620 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da1f156; op2val:0x40c3f0a5;
op3val:0x7ef7e620; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x21f156 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x43f0a5 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77e620 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da1f156; op2val:0x40c3f0a5;
op3val:0x7ef7e620; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x21f156 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x43f0a5 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77e620 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da1f156; op2val:0x40c3f0a5;
op3val:0x7ef7e620; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x21f156 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x43f0a5 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77e620 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da1f156; op2val:0x40c3f0a5;
op3val:0x7ef7e620; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x280d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x30665c and fs3 == 0 and fe3 == 0xfd and fm3 == 0x679880 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da80d2c; op2val:0x40b0665c;
op3val:0x7ee79880; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x280d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x30665c and fs3 == 0 and fe3 == 0xfd and fm3 == 0x679880 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da80d2c; op2val:0x40b0665c;
op3val:0x7ee79880; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x280d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x30665c and fs3 == 0 and fe3 == 0xfd and fm3 == 0x679880 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da80d2c; op2val:0x40b0665c;
op3val:0x7ee79880; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x280d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x30665c and fs3 == 0 and fe3 == 0xfd and fm3 == 0x679880 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da80d2c; op2val:0x40b0665c;
op3val:0x7ee79880; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x280d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x30665c and fs3 == 0 and fe3 == 0xfd and fm3 == 0x679880 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da80d2c; op2val:0x40b0665c;
op3val:0x7ee79880; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x29bf15 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x31d38a and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6bd2c4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da9bf15; op2val:0x40b1d38a;
op3val:0x7eebd2c4; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x29bf15 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x31d38a and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6bd2c4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da9bf15; op2val:0x40b1d38a;
op3val:0x7eebd2c4; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x29bf15 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x31d38a and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6bd2c4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da9bf15; op2val:0x40b1d38a;
op3val:0x7eebd2c4; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x29bf15 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x31d38a and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6bd2c4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da9bf15; op2val:0x40b1d38a;
op3val:0x7eebd2c4; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x29bf15 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x31d38a and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6bd2c4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7da9bf15; op2val:0x40b1d38a;
op3val:0x7eebd2c4; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x2c3fe4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4d0748 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x09f410 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dac3fe4; op2val:0x40cd0748;
op3val:0x7f09f410; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x2c3fe4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4d0748 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x09f410 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dac3fe4; op2val:0x40cd0748;
op3val:0x7f09f410; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x2c3fe4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4d0748 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x09f410 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dac3fe4; op2val:0x40cd0748;
op3val:0x7f09f410; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x2c3fe4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4d0748 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x09f410 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dac3fe4; op2val:0x40cd0748;
op3val:0x7f09f410; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x2c3fe4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4d0748 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x09f410 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dac3fe4; op2val:0x40cd0748;
op3val:0x7f09f410; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x300384 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x468f57 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x088546 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db00384; op2val:0x40c68f57;
op3val:0x7f088546; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x300384 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x468f57 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x088546 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db00384; op2val:0x40c68f57;
op3val:0x7f088546; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x300384 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x468f57 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x088546 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db00384; op2val:0x40c68f57;
op3val:0x7f088546; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x300384 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x468f57 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x088546 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db00384; op2val:0x40c68f57;
op3val:0x7f088546; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x300384 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x468f57 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x088546 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db00384; op2val:0x40c68f57;
op3val:0x7f088546; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x337137 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3588f6 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e7e1b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db37137; op2val:0x40b588f6;
op3val:0x7efe7e1b; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x33e534 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x0192c8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x361b4b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db3e534; op2val:0x410192c8;
op3val:0x7f361b4b; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x33e534 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x0192c8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x361b4b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db3e534; op2val:0x410192c8;
op3val:0x7f361b4b; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x33e534 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x0192c8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x361b4b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db3e534; op2val:0x410192c8;
op3val:0x7f361b4b; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x33e534 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x0192c8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x361b4b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db3e534; op2val:0x410192c8;
op3val:0x7f361b4b; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x33e534 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x0192c8 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x361b4b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db3e534; op2val:0x410192c8;
op3val:0x7f361b4b; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3868e1 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6f4b41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2c6020 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db868e1; op2val:0x3f6f4b41;
op3val:0x7dac6020; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3868e1 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6f4b41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2c6020 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db868e1; op2val:0x3f6f4b41;
op3val:0x7dac6020; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3868e1 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6f4b41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2c6020 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db868e1; op2val:0x3f6f4b41;
op3val:0x7dac6020; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3868e1 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6f4b41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2c6020 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db868e1; op2val:0x3f6f4b41;
op3val:0x7dac6020; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3868e1 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6f4b41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2c6020 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7db868e1; op2val:0x3f6f4b41;
op3val:0x7dac6020; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3db054 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x18ba96 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6255e7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbdb054; op2val:0x4098ba96;
op3val:0x7ee255e7; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3db054 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x18ba96 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6255e7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbdb054; op2val:0x4098ba96;
op3val:0x7ee255e7; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3db054 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x18ba96 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6255e7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbdb054; op2val:0x4098ba96;
op3val:0x7ee255e7; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3db054 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x18ba96 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6255e7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbdb054; op2val:0x4098ba96;
op3val:0x7ee255e7; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3db054 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x18ba96 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6255e7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbdb054; op2val:0x4098ba96;
op3val:0x7ee255e7; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x42d171 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7c4426 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3ffa07 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc2d171; op2val:0x40fc4426;
op3val:0x7f3ffa07; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x431508 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x51cb43 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fdf11 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc31508; op2val:0x40d1cb43;
op3val:0x7f1fdf11; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x431508 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x51cb43 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fdf11 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc31508; op2val:0x40d1cb43;
op3val:0x7f1fdf11; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x431508 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x51cb43 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fdf11 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc31508; op2val:0x40d1cb43;
op3val:0x7f1fdf11; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x431508 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x51cb43 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fdf11 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc31508; op2val:0x40d1cb43;
op3val:0x7f1fdf11; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x431508 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x51cb43 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fdf11 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dc31508; op2val:0x40d1cb43;
op3val:0x7f1fdf11; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4b55e5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4aac55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20faa9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcb55e5; op2val:0x404aac55;
op3val:0x7ea0faa9; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4b55e5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4aac55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20faa9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcb55e5; op2val:0x404aac55;
op3val:0x7ea0faa9; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4b55e5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4aac55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20faa9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcb55e5; op2val:0x404aac55;
op3val:0x7ea0faa9; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4b55e5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4aac55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20faa9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcb55e5; op2val:0x404aac55;
op3val:0x7ea0faa9; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4b55e5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4aac55 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20faa9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dcb55e5; op2val:0x404aac55;
op3val:0x7ea0faa9; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x521565 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4fc576 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2a8159 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd21565; op2val:0x40cfc576;
op3val:0x7f2a8159; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x521565 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4fc576 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2a8159 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd21565; op2val:0x40cfc576;
op3val:0x7f2a8159; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x521565 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4fc576 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2a8159 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd21565; op2val:0x40cfc576;
op3val:0x7f2a8159; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x521565 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4fc576 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2a8159 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd21565; op2val:0x40cfc576;
op3val:0x7f2a8159; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x521565 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x4fc576 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2a8159 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd21565; op2val:0x40cfc576;
op3val:0x7f2a8159; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x528ae7 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x5c3da9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x352215 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd28ae7; op2val:0x40dc3da9;
op3val:0x7f352215; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x528ae7 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x5c3da9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x352215 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd28ae7; op2val:0x40dc3da9;
op3val:0x7f352215; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x528ae7 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x5c3da9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x352215 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd28ae7; op2val:0x40dc3da9;
op3val:0x7f352215; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x528ae7 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x5c3da9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x352215 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd28ae7; op2val:0x40dc3da9;
op3val:0x7f352215; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x528ae7 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x5c3da9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x352215 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd28ae7; op2val:0x40dc3da9;
op3val:0x7f352215; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x561e0c and fs2 == 0 and fe2 == 0x7b and fm2 == 0x106484 and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x7189f3 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd61e0c; op2val:0x3d906484;
op3val:0x7bf189f3; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x561e0c and fs2 == 0 and fe2 == 0x7b and fm2 == 0x106484 and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x7189f3 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd61e0c; op2val:0x3d906484;
op3val:0x7bf189f3; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x561e0c and fs2 == 0 and fe2 == 0x7b and fm2 == 0x106484 and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x7189f3 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd61e0c; op2val:0x3d906484;
op3val:0x7bf189f3; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x561e0c and fs2 == 0 and fe2 == 0x7b and fm2 == 0x106484 and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x7189f3 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd61e0c; op2val:0x3d906484;
op3val:0x7bf189f3; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x561e0c and fs2 == 0 and fe2 == 0x7b and fm2 == 0x106484 and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x7189f3 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dd61e0c; op2val:0x3d906484;
op3val:0x7bf189f3; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5ea80c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0a19f7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x703a58 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ddea80c; op2val:0x408a19f7;
op3val:0x7ef03a58; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5ea80c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0a19f7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x703a58 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ddea80c; op2val:0x408a19f7;
op3val:0x7ef03a58; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5ea80c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0a19f7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x703a58 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ddea80c; op2val:0x408a19f7;
op3val:0x7ef03a58; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5ea80c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0a19f7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x703a58 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ddea80c; op2val:0x408a19f7;
op3val:0x7ef03a58; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5ea80c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0a19f7 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x703a58 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ddea80c; op2val:0x408a19f7;
op3val:0x7ef03a58; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x624363 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x10f5b7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x001f14 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de24363; op2val:0x4090f5b7;
op3val:0x7f001f14; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x624363 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x10f5b7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x001f14 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de24363; op2val:0x4090f5b7;
op3val:0x7f001f14; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x624363 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x10f5b7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x001f14 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de24363; op2val:0x4090f5b7;
op3val:0x7f001f14; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x624363 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x10f5b7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x001f14 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de24363; op2val:0x4090f5b7;
op3val:0x7f001f14; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x624363 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x10f5b7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x001f14 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de24363; op2val:0x4090f5b7;
op3val:0x7f001f14; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x66dc85 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6fe8a0 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5859a9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de6dc85; op2val:0x3fefe8a0;
op3val:0x7e5859a9; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x66dc85 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6fe8a0 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5859a9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de6dc85; op2val:0x3fefe8a0;
op3val:0x7e5859a9; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x66dc85 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6fe8a0 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5859a9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de6dc85; op2val:0x3fefe8a0;
op3val:0x7e5859a9; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x66dc85 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6fe8a0 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5859a9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de6dc85; op2val:0x3fefe8a0;
op3val:0x7e5859a9; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x66dc85 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6fe8a0 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5859a9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de6dc85; op2val:0x3fefe8a0;
op3val:0x7e5859a9; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x67f048 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x70ec94 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a479c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de7f048; op2val:0x4070ec94;
op3val:0x7eda479c; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x67f048 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x70ec94 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a479c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de7f048; op2val:0x4070ec94;
op3val:0x7eda479c; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x67f048 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x70ec94 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a479c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de7f048; op2val:0x4070ec94;
op3val:0x7eda479c; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x67f048 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x70ec94 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a479c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de7f048; op2val:0x4070ec94;
op3val:0x7eda479c; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x67f048 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x70ec94 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a479c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de7f048; op2val:0x4070ec94;
op3val:0x7eda479c; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7aa684 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x784242 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x731230 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfaa684; op2val:0x3ff84242;
op3val:0x7e731230; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2)

inst_231:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7aa684 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x784242 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x731230 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfaa684; op2val:0x3ff84242;
op3val:0x7e731230; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 693*FLEN/8, x4, x1, x2)

inst_232:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7aa684 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x784242 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x731230 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfaa684; op2val:0x3ff84242;
op3val:0x7e731230; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 696*FLEN/8, x4, x1, x2)

inst_233:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7aa684 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x784242 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x731230 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfaa684; op2val:0x3ff84242;
op3val:0x7e731230; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 699*FLEN/8, x4, x1, x2)

inst_234:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7aa684 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x784242 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x731230 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfaa684; op2val:0x3ff84242;
op3val:0x7e731230; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 702*FLEN/8, x4, x1, x2)

inst_235:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7c19fa and fs2 == 0 and fe2 == 0x80 and fm2 == 0x73e479 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x702da8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfc19fa; op2val:0x4073e479;
op3val:0x7ef02da8; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 705*FLEN/8, x4, x1, x2)

inst_236:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7c19fa and fs2 == 0 and fe2 == 0x80 and fm2 == 0x73e479 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x702da8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfc19fa; op2val:0x4073e479;
op3val:0x7ef02da8; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 708*FLEN/8, x4, x1, x2)

inst_237:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7c19fa and fs2 == 0 and fe2 == 0x80 and fm2 == 0x73e479 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x702da8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfc19fa; op2val:0x4073e479;
op3val:0x7ef02da8; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 711*FLEN/8, x4, x1, x2)

inst_238:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7c19fa and fs2 == 0 and fe2 == 0x80 and fm2 == 0x73e479 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x702da8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfc19fa; op2val:0x4073e479;
op3val:0x7ef02da8; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 714*FLEN/8, x4, x1, x2)

inst_239:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7c19fa and fs2 == 0 and fe2 == 0x80 and fm2 == 0x73e479 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x702da8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dfc19fa; op2val:0x4073e479;
op3val:0x7ef02da8; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 717*FLEN/8, x4, x1, x2)

inst_240:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x017e79 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7b0813 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7df62e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e017e79; op2val:0x407b0813;
op3val:0x7efdf62e; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2)

inst_241:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x017e79 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7b0813 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7df62e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e017e79; op2val:0x407b0813;
op3val:0x7efdf62e; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 723*FLEN/8, x4, x1, x2)

inst_242:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x017e79 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7b0813 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7df62e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e017e79; op2val:0x407b0813;
op3val:0x7efdf62e; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 726*FLEN/8, x4, x1, x2)

inst_243:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x017e79 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7b0813 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7df62e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e017e79; op2val:0x407b0813;
op3val:0x7efdf62e; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 729*FLEN/8, x4, x1, x2)

inst_244:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x017e79 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7b0813 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7df62e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e017e79; op2val:0x407b0813;
op3val:0x7efdf62e; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 732*FLEN/8, x4, x1, x2)

inst_245:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0431c2 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x022039 and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x0663d1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0431c2; op2val:0x3e022039;
op3val:0x7c8663d1; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 735*FLEN/8, x4, x1, x2)

inst_246:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0431c2 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x022039 and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x0663d1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0431c2; op2val:0x3e022039;
op3val:0x7c8663d1; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 738*FLEN/8, x4, x1, x2)

inst_247:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0431c2 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x022039 and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x0663d1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0431c2; op2val:0x3e022039;
op3val:0x7c8663d1; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 741*FLEN/8, x4, x1, x2)

inst_248:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0431c2 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x022039 and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x0663d1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0431c2; op2val:0x3e022039;
op3val:0x7c8663d1; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 744*FLEN/8, x4, x1, x2)

inst_249:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0431c2 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x022039 and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x0663d1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0431c2; op2val:0x3e022039;
op3val:0x7c8663d1; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 747*FLEN/8, x4, x1, x2)

inst_250:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x068091 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x068118 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0d5640 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e068091; op2val:0x3f868118;
op3val:0x7e0d5640; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2)

inst_251:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x068091 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x068118 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0d5640 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e068091; op2val:0x3f868118;
op3val:0x7e0d5640; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 753*FLEN/8, x4, x1, x2)

inst_252:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x068091 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x068118 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0d5640 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e068091; op2val:0x3f868118;
op3val:0x7e0d5640; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 756*FLEN/8, x4, x1, x2)

inst_253:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x068091 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x068118 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0d5640 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e068091; op2val:0x3f868118;
op3val:0x7e0d5640; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 759*FLEN/8, x4, x1, x2)

inst_254:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x068091 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x068118 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x0d5640 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e068091; op2val:0x3f868118;
op3val:0x7e0d5640; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 762*FLEN/8, x4, x1, x2)

inst_255:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0ba7c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2bf5fd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b9e80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0ba7c1; op2val:0x40abf5fd;
op3val:0x7f3b9e80; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 765*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_256:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0ba7c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2bf5fd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b9e80 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0ba7c1; op2val:0x40abf5fd;
op3val:0x7f3b9e80; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 768*FLEN/8, x4, x1, x2)

inst_257:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0ba7c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2bf5fd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b9e80 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0ba7c1; op2val:0x40abf5fd;
op3val:0x7f3b9e80; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 771*FLEN/8, x4, x1, x2)

inst_258:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0ba7c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2bf5fd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b9e80 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0ba7c1; op2val:0x40abf5fd;
op3val:0x7f3b9e80; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 774*FLEN/8, x4, x1, x2)

inst_259:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0ba7c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2bf5fd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b9e80 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0ba7c1; op2val:0x40abf5fd;
op3val:0x7f3b9e80; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 777*FLEN/8, x4, x1, x2)

inst_260:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x107f0d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5d489c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x79cd55 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e107f0d; op2val:0x3fdd489c;
op3val:0x7e79cd55; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2)

inst_261:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x107f0d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5d489c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x79cd55 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e107f0d; op2val:0x3fdd489c;
op3val:0x7e79cd55; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 783*FLEN/8, x4, x1, x2)

inst_262:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x107f0d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5d489c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x79cd55 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e107f0d; op2val:0x3fdd489c;
op3val:0x7e79cd55; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 786*FLEN/8, x4, x1, x2)

inst_263:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x107f0d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5d489c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x79cd55 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e107f0d; op2val:0x3fdd489c;
op3val:0x7e79cd55; valaddr_reg:x3; val_offset:789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 789*FLEN/8, x4, x1, x2)

inst_264:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x107f0d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x5d489c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x79cd55 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e107f0d; op2val:0x3fdd489c;
op3val:0x7e79cd55; valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 792*FLEN/8, x4, x1, x2)

inst_265:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13dd38 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x150f89 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2c3176 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13dd38; op2val:0x40150f89;
op3val:0x7eac3176; valaddr_reg:x3; val_offset:795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 795*FLEN/8, x4, x1, x2)

inst_266:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13dd38 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x150f89 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2c3176 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13dd38; op2val:0x40150f89;
op3val:0x7eac3176; valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 798*FLEN/8, x4, x1, x2)

inst_267:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13dd38 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x150f89 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2c3176 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13dd38; op2val:0x40150f89;
op3val:0x7eac3176; valaddr_reg:x3; val_offset:801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 801*FLEN/8, x4, x1, x2)

inst_268:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13dd38 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x150f89 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2c3176 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13dd38; op2val:0x40150f89;
op3val:0x7eac3176; valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 804*FLEN/8, x4, x1, x2)

inst_269:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13dd38 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x150f89 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2c3176 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13dd38; op2val:0x40150f89;
op3val:0x7eac3176; valaddr_reg:x3; val_offset:807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 807*FLEN/8, x4, x1, x2)

inst_270:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13f0eb and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d617d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35e62e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13f0eb; op2val:0x409d617d;
op3val:0x7f35e62e; valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2)

inst_271:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13f0eb and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d617d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35e62e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13f0eb; op2val:0x409d617d;
op3val:0x7f35e62e; valaddr_reg:x3; val_offset:813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 813*FLEN/8, x4, x1, x2)

inst_272:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13f0eb and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d617d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35e62e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13f0eb; op2val:0x409d617d;
op3val:0x7f35e62e; valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 816*FLEN/8, x4, x1, x2)

inst_273:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13f0eb and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d617d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35e62e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13f0eb; op2val:0x409d617d;
op3val:0x7f35e62e; valaddr_reg:x3; val_offset:819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 819*FLEN/8, x4, x1, x2)

inst_274:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13f0eb and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d617d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35e62e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13f0eb; op2val:0x409d617d;
op3val:0x7f35e62e; valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 822*FLEN/8, x4, x1, x2)

inst_275:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 825*FLEN/8, x4, x1, x2)

inst_276:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 828*FLEN/8, x4, x1, x2)

inst_277:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 831*FLEN/8, x4, x1, x2)

inst_278:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 834*FLEN/8, x4, x1, x2)

inst_279:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14365e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3798bb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x549695 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e14365e; op2val:0x403798bb;
op3val:0x7ed49695; valaddr_reg:x3; val_offset:837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 837*FLEN/8, x4, x1, x2)

inst_280:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2)

inst_281:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 843*FLEN/8, x4, x1, x2)

inst_282:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 846*FLEN/8, x4, x1, x2)

inst_283:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 849*FLEN/8, x4, x1, x2)

inst_284:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1a457f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50d100 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7bacd4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1a457f; op2val:0x4050d100;
op3val:0x7efbacd4; valaddr_reg:x3; val_offset:852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 852*FLEN/8, x4, x1, x2)

inst_285:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 855*FLEN/8, x4, x1, x2)

inst_286:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 858*FLEN/8, x4, x1, x2)

inst_287:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 861*FLEN/8, x4, x1, x2)

inst_288:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 864*FLEN/8, x4, x1, x2)

inst_289:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21311f and fs2 == 0 and fe2 == 0x81 and fm2 == 0x03f6ba and fs3 == 0 and fe3 == 0xfe and fm3 == 0x262efb and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21311f; op2val:0x4083f6ba;
op3val:0x7f262efb; valaddr_reg:x3; val_offset:867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 867*FLEN/8, x4, x1, x2)

inst_290:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2a2f80 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x22e85e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x589913 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e2a2f80; op2val:0x4022e85e;
op3val:0x7ed89913; valaddr_reg:x3; val_offset:870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 870*FLEN/8, x4, x1, x2)

inst_291:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2a2f80 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x22e85e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x589913 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e2a2f80; op2val:0x4022e85e;
op3val:0x7ed89913; valaddr_reg:x3; val_offset:873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 873*FLEN/8, x4, x1, x2)

inst_292:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2a2f80 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x22e85e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x589913 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e2a2f80; op2val:0x4022e85e;
op3val:0x7ed89913; valaddr_reg:x3; val_offset:876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 876*FLEN/8, x4, x1, x2)

inst_293:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2a2f80 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x22e85e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x589913 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e2a2f80; op2val:0x4022e85e;
op3val:0x7ed89913; valaddr_reg:x3; val_offset:879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 879*FLEN/8, x4, x1, x2)

inst_294:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2a2f80 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x22e85e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x589913 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e2a2f80; op2val:0x4022e85e;
op3val:0x7ed89913; valaddr_reg:x3; val_offset:882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 882*FLEN/8, x4, x1, x2)

inst_295:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x389380 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x186b19 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5bc998 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e389380; op2val:0x40186b19;
op3val:0x7edbc998; valaddr_reg:x3; val_offset:885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 885*FLEN/8, x4, x1, x2)

inst_296:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x389380 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x186b19 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5bc998 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e389380; op2val:0x40186b19;
op3val:0x7edbc998; valaddr_reg:x3; val_offset:888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 888*FLEN/8, x4, x1, x2)

inst_297:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x389380 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x186b19 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5bc998 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e389380; op2val:0x40186b19;
op3val:0x7edbc998; valaddr_reg:x3; val_offset:891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 891*FLEN/8, x4, x1, x2)

inst_298:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x389380 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x186b19 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5bc998 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e389380; op2val:0x40186b19;
op3val:0x7edbc998; valaddr_reg:x3; val_offset:894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 894*FLEN/8, x4, x1, x2)

inst_299:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x389380 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x186b19 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5bc998 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e389380; op2val:0x40186b19;
op3val:0x7edbc998; valaddr_reg:x3; val_offset:897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 897*FLEN/8, x4, x1, x2)

inst_300:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x416656 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0708c5 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x4c072f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e416656; op2val:0x3f0708c5;
op3val:0x7dcc072f; valaddr_reg:x3; val_offset:900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 900*FLEN/8, x4, x1, x2)

inst_301:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x416656 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0708c5 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x4c072f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e416656; op2val:0x3f0708c5;
op3val:0x7dcc072f; valaddr_reg:x3; val_offset:903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 903*FLEN/8, x4, x1, x2)

inst_302:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x416656 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0708c5 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x4c072f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e416656; op2val:0x3f0708c5;
op3val:0x7dcc072f; valaddr_reg:x3; val_offset:906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 906*FLEN/8, x4, x1, x2)

inst_303:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x416656 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0708c5 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x4c072f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e416656; op2val:0x3f0708c5;
op3val:0x7dcc072f; valaddr_reg:x3; val_offset:909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 909*FLEN/8, x4, x1, x2)

inst_304:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x416656 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0708c5 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x4c072f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e416656; op2val:0x3f0708c5;
op3val:0x7dcc072f; valaddr_reg:x3; val_offset:912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 912*FLEN/8, x4, x1, x2)

inst_305:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x43a885 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4e4840 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1da8d4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e43a885; op2val:0x3fce4840;
op3val:0x7e9da8d4; valaddr_reg:x3; val_offset:915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 915*FLEN/8, x4, x1, x2)

inst_306:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x43a885 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4e4840 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1da8d4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e43a885; op2val:0x3fce4840;
op3val:0x7e9da8d4; valaddr_reg:x3; val_offset:918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 918*FLEN/8, x4, x1, x2)

inst_307:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x43a885 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4e4840 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1da8d4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e43a885; op2val:0x3fce4840;
op3val:0x7e9da8d4; valaddr_reg:x3; val_offset:921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 921*FLEN/8, x4, x1, x2)

inst_308:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x43a885 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4e4840 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1da8d4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e43a885; op2val:0x3fce4840;
op3val:0x7e9da8d4; valaddr_reg:x3; val_offset:924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 924*FLEN/8, x4, x1, x2)

inst_309:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x43a885 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4e4840 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1da8d4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e43a885; op2val:0x3fce4840;
op3val:0x7e9da8d4; valaddr_reg:x3; val_offset:927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 927*FLEN/8, x4, x1, x2)

inst_310:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4dc6a7 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x62c78f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3649c8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4dc6a7; op2val:0x3fe2c78f;
op3val:0x7eb649c8; valaddr_reg:x3; val_offset:930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 930*FLEN/8, x4, x1, x2)

inst_311:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4dc6a7 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x62c78f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3649c8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4dc6a7; op2val:0x3fe2c78f;
op3val:0x7eb649c8; valaddr_reg:x3; val_offset:933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 933*FLEN/8, x4, x1, x2)

inst_312:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4dc6a7 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x62c78f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3649c8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4dc6a7; op2val:0x3fe2c78f;
op3val:0x7eb649c8; valaddr_reg:x3; val_offset:936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 936*FLEN/8, x4, x1, x2)

inst_313:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4dc6a7 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x62c78f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3649c8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4dc6a7; op2val:0x3fe2c78f;
op3val:0x7eb649c8; valaddr_reg:x3; val_offset:939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 939*FLEN/8, x4, x1, x2)

inst_314:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4dc6a7 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x62c78f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3649c8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e4dc6a7; op2val:0x3fe2c78f;
op3val:0x7eb649c8; valaddr_reg:x3; val_offset:942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 942*FLEN/8, x4, x1, x2)

inst_315:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 945*FLEN/8, x4, x1, x2)

inst_316:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 948*FLEN/8, x4, x1, x2)

inst_317:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 951*FLEN/8, x4, x1, x2)

inst_318:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 954*FLEN/8, x4, x1, x2)

inst_319:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x516e9f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3c33f6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x19f7bf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e516e9f; op2val:0x403c33f6;
op3val:0x7f19f7bf; valaddr_reg:x3; val_offset:957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 957*FLEN/8, x4, x1, x2)

inst_320:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52effd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2813b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0a7dbc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52effd; op2val:0x402813b5;
op3val:0x7f0a7dbc; valaddr_reg:x3; val_offset:960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 960*FLEN/8, x4, x1, x2)

inst_321:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52effd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2813b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0a7dbc and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52effd; op2val:0x402813b5;
op3val:0x7f0a7dbc; valaddr_reg:x3; val_offset:963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 963*FLEN/8, x4, x1, x2)

inst_322:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52effd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2813b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0a7dbc and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52effd; op2val:0x402813b5;
op3val:0x7f0a7dbc; valaddr_reg:x3; val_offset:966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 966*FLEN/8, x4, x1, x2)

inst_323:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52effd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2813b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0a7dbc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52effd; op2val:0x402813b5;
op3val:0x7f0a7dbc; valaddr_reg:x3; val_offset:969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 969*FLEN/8, x4, x1, x2)

inst_324:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52effd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2813b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0a7dbc and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52effd; op2val:0x402813b5;
op3val:0x7f0a7dbc; valaddr_reg:x3; val_offset:972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 972*FLEN/8, x4, x1, x2)

inst_325:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5447d6 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x24f81b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x08cbc1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5447d6; op2val:0x4024f81b;
op3val:0x7f08cbc1; valaddr_reg:x3; val_offset:975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 975*FLEN/8, x4, x1, x2)

inst_326:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5447d6 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x24f81b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x08cbc1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5447d6; op2val:0x4024f81b;
op3val:0x7f08cbc1; valaddr_reg:x3; val_offset:978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 978*FLEN/8, x4, x1, x2)

inst_327:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5447d6 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x24f81b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x08cbc1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5447d6; op2val:0x4024f81b;
op3val:0x7f08cbc1; valaddr_reg:x3; val_offset:981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 981*FLEN/8, x4, x1, x2)

inst_328:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5447d6 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x24f81b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x08cbc1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5447d6; op2val:0x4024f81b;
op3val:0x7f08cbc1; valaddr_reg:x3; val_offset:984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 984*FLEN/8, x4, x1, x2)

inst_329:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5447d6 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x24f81b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x08cbc1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5447d6; op2val:0x4024f81b;
op3val:0x7f08cbc1; valaddr_reg:x3; val_offset:987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 987*FLEN/8, x4, x1, x2)

inst_330:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5f5397 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x2e726c and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x182ea3 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5f5397; op2val:0x3cae726c;
op3val:0x7b982ea3; valaddr_reg:x3; val_offset:990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 990*FLEN/8, x4, x1, x2)

inst_331:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5f5397 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x2e726c and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x182ea3 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5f5397; op2val:0x3cae726c;
op3val:0x7b982ea3; valaddr_reg:x3; val_offset:993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 993*FLEN/8, x4, x1, x2)

inst_332:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5f5397 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x2e726c and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x182ea3 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5f5397; op2val:0x3cae726c;
op3val:0x7b982ea3; valaddr_reg:x3; val_offset:996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 996*FLEN/8, x4, x1, x2)

inst_333:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5f5397 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x2e726c and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x182ea3 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5f5397; op2val:0x3cae726c;
op3val:0x7b982ea3; valaddr_reg:x3; val_offset:999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 999*FLEN/8, x4, x1, x2)

inst_334:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5f5397 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x2e726c and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x182ea3 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5f5397; op2val:0x3cae726c;
op3val:0x7b982ea3; valaddr_reg:x3; val_offset:1002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1002*FLEN/8, x4, x1, x2)

inst_335:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x616815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4d6ee4 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x34e1fc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e616815; op2val:0x3fcd6ee4;
op3val:0x7eb4e1fc; valaddr_reg:x3; val_offset:1005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1005*FLEN/8, x4, x1, x2)

inst_336:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x616815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4d6ee4 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x34e1fc and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e616815; op2val:0x3fcd6ee4;
op3val:0x7eb4e1fc; valaddr_reg:x3; val_offset:1008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1008*FLEN/8, x4, x1, x2)

inst_337:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x616815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4d6ee4 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x34e1fc and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e616815; op2val:0x3fcd6ee4;
op3val:0x7eb4e1fc; valaddr_reg:x3; val_offset:1011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1011*FLEN/8, x4, x1, x2)

inst_338:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x616815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4d6ee4 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x34e1fc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e616815; op2val:0x3fcd6ee4;
op3val:0x7eb4e1fc; valaddr_reg:x3; val_offset:1014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1014*FLEN/8, x4, x1, x2)

inst_339:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x616815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4d6ee4 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x34e1fc and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e616815; op2val:0x3fcd6ee4;
op3val:0x7eb4e1fc; valaddr_reg:x3; val_offset:1017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1017*FLEN/8, x4, x1, x2)

inst_340:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a2e5f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0a93e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7d8898 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6a2e5f; op2val:0x3e8a93e8;
op3val:0x7d7d8898; valaddr_reg:x3; val_offset:1020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)

inst_341:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a2e5f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0a93e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7d8898 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6a2e5f; op2val:0x3e8a93e8;
op3val:0x7d7d8898; valaddr_reg:x3; val_offset:1023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1023*FLEN/8, x4, x1, x2)

inst_342:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a2e5f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0a93e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7d8898 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6a2e5f; op2val:0x3e8a93e8;
op3val:0x7d7d8898; valaddr_reg:x3; val_offset:1026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1026*FLEN/8, x4, x1, x2)

inst_343:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a2e5f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0a93e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7d8898 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6a2e5f; op2val:0x3e8a93e8;
op3val:0x7d7d8898; valaddr_reg:x3; val_offset:1029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1029*FLEN/8, x4, x1, x2)

inst_344:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a2e5f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0a93e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x7d8898 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6a2e5f; op2val:0x3e8a93e8;
op3val:0x7d7d8898; valaddr_reg:x3; val_offset:1032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1032*FLEN/8, x4, x1, x2)

inst_345:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:1035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1035*FLEN/8, x4, x1, x2)

inst_346:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:1038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1038*FLEN/8, x4, x1, x2)

inst_347:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:1041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1041*FLEN/8, x4, x1, x2)

inst_348:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:1044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1044*FLEN/8, x4, x1, x2)

inst_349:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fd4df and fs2 == 0 and fe2 == 0x7e and fm2 == 0x20dc16 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x16b33b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fd4df; op2val:0x3f20dc16;
op3val:0x7e16b33b; valaddr_reg:x3; val_offset:1047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1047*FLEN/8, x4, x1, x2)

inst_350:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:1050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)

inst_351:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:1053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1053*FLEN/8, x4, x1, x2)

inst_352:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:1056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1056*FLEN/8, x4, x1, x2)

inst_353:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:1059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1059*FLEN/8, x4, x1, x2)

inst_354:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7fad2c and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2ddf2e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2da6ed and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7fad2c; op2val:0x402ddf2e;
op3val:0x7f2da6ed; valaddr_reg:x3; val_offset:1062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1062*FLEN/8, x4, x1, x2)

inst_355:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x03e545 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6754b2 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x6e5f0a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e83e545; op2val:0x3e6754b2;
op3val:0x7d6e5f0a; valaddr_reg:x3; val_offset:1065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1065*FLEN/8, x4, x1, x2)

inst_356:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x03e545 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6754b2 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x6e5f0a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e83e545; op2val:0x3e6754b2;
op3val:0x7d6e5f0a; valaddr_reg:x3; val_offset:1068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1068*FLEN/8, x4, x1, x2)

inst_357:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x03e545 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6754b2 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x6e5f0a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e83e545; op2val:0x3e6754b2;
op3val:0x7d6e5f0a; valaddr_reg:x3; val_offset:1071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1071*FLEN/8, x4, x1, x2)

inst_358:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x03e545 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6754b2 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x6e5f0a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e83e545; op2val:0x3e6754b2;
op3val:0x7d6e5f0a; valaddr_reg:x3; val_offset:1074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1074*FLEN/8, x4, x1, x2)

inst_359:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x03e545 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6754b2 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x6e5f0a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e83e545; op2val:0x3e6754b2;
op3val:0x7d6e5f0a; valaddr_reg:x3; val_offset:1077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1077*FLEN/8, x4, x1, x2)

inst_360:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x06cc9c and fs2 == 0 and fe2 == 0x7d and fm2 == 0x66cf6d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x73121a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e86cc9c; op2val:0x3ee6cf6d;
op3val:0x7df3121a; valaddr_reg:x3; val_offset:1080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)

inst_361:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x06cc9c and fs2 == 0 and fe2 == 0x7d and fm2 == 0x66cf6d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x73121a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e86cc9c; op2val:0x3ee6cf6d;
op3val:0x7df3121a; valaddr_reg:x3; val_offset:1083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1083*FLEN/8, x4, x1, x2)

inst_362:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x06cc9c and fs2 == 0 and fe2 == 0x7d and fm2 == 0x66cf6d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x73121a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e86cc9c; op2val:0x3ee6cf6d;
op3val:0x7df3121a; valaddr_reg:x3; val_offset:1086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1086*FLEN/8, x4, x1, x2)

inst_363:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x06cc9c and fs2 == 0 and fe2 == 0x7d and fm2 == 0x66cf6d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x73121a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e86cc9c; op2val:0x3ee6cf6d;
op3val:0x7df3121a; valaddr_reg:x3; val_offset:1089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1089*FLEN/8, x4, x1, x2)

inst_364:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x06cc9c and fs2 == 0 and fe2 == 0x7d and fm2 == 0x66cf6d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x73121a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e86cc9c; op2val:0x3ee6cf6d;
op3val:0x7df3121a; valaddr_reg:x3; val_offset:1092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1092*FLEN/8, x4, x1, x2)

inst_365:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:1095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1095*FLEN/8, x4, x1, x2)

inst_366:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:1098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1098*FLEN/8, x4, x1, x2)

inst_367:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:1101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1101*FLEN/8, x4, x1, x2)

inst_368:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:1104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1104*FLEN/8, x4, x1, x2)

inst_369:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a62c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25a532 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3315e5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a62c0; op2val:0x4025a532;
op3val:0x7f3315e5; valaddr_reg:x3; val_offset:1107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1107*FLEN/8, x4, x1, x2)

inst_370:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0aa492 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x35bca1 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x44d907 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8aa492; op2val:0x3f35bca1;
op3val:0x7e44d907; valaddr_reg:x3; val_offset:1110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)

inst_371:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0aa492 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x35bca1 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x44d907 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8aa492; op2val:0x3f35bca1;
op3val:0x7e44d907; valaddr_reg:x3; val_offset:1113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1113*FLEN/8, x4, x1, x2)

inst_372:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0aa492 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x35bca1 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x44d907 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8aa492; op2val:0x3f35bca1;
op3val:0x7e44d907; valaddr_reg:x3; val_offset:1116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1116*FLEN/8, x4, x1, x2)

inst_373:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0aa492 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x35bca1 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x44d907 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8aa492; op2val:0x3f35bca1;
op3val:0x7e44d907; valaddr_reg:x3; val_offset:1119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1119*FLEN/8, x4, x1, x2)

inst_374:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0aa492 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x35bca1 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x44d907 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8aa492; op2val:0x3f35bca1;
op3val:0x7e44d907; valaddr_reg:x3; val_offset:1122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1122*FLEN/8, x4, x1, x2)

inst_375:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b0329 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25e82c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x342e39 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b0329; op2val:0x4025e82c;
op3val:0x7f342e39; valaddr_reg:x3; val_offset:1125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1125*FLEN/8, x4, x1, x2)

inst_376:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b0329 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25e82c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x342e39 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b0329; op2val:0x4025e82c;
op3val:0x7f342e39; valaddr_reg:x3; val_offset:1128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1128*FLEN/8, x4, x1, x2)

inst_377:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b0329 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25e82c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x342e39 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b0329; op2val:0x4025e82c;
op3val:0x7f342e39; valaddr_reg:x3; val_offset:1131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1131*FLEN/8, x4, x1, x2)

inst_378:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b0329 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25e82c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x342e39 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b0329; op2val:0x4025e82c;
op3val:0x7f342e39; valaddr_reg:x3; val_offset:1134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1134*FLEN/8, x4, x1, x2)

inst_379:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b0329 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x25e82c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x342e39 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b0329; op2val:0x4025e82c;
op3val:0x7f342e39; valaddr_reg:x3; val_offset:1137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1137*FLEN/8, x4, x1, x2)

inst_380:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b58ef and fs2 == 0 and fe2 == 0x78 and fm2 == 0x71d2ec and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x03a189 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b58ef; op2val:0x3c71d2ec;
op3val:0x7b83a189; valaddr_reg:x3; val_offset:1140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)

inst_381:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b58ef and fs2 == 0 and fe2 == 0x78 and fm2 == 0x71d2ec and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x03a189 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b58ef; op2val:0x3c71d2ec;
op3val:0x7b83a189; valaddr_reg:x3; val_offset:1143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1143*FLEN/8, x4, x1, x2)

inst_382:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b58ef and fs2 == 0 and fe2 == 0x78 and fm2 == 0x71d2ec and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x03a189 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b58ef; op2val:0x3c71d2ec;
op3val:0x7b83a189; valaddr_reg:x3; val_offset:1146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1146*FLEN/8, x4, x1, x2)

inst_383:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b58ef and fs2 == 0 and fe2 == 0x78 and fm2 == 0x71d2ec and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x03a189 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b58ef; op2val:0x3c71d2ec;
op3val:0x7b83a189; valaddr_reg:x3; val_offset:1149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1149*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_384:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0b58ef and fs2 == 0 and fe2 == 0x78 and fm2 == 0x71d2ec and fs3 == 0 and fe3 == 0xf7 and fm3 == 0x03a189 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8b58ef; op2val:0x3c71d2ec;
op3val:0x7b83a189; valaddr_reg:x3; val_offset:1152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1152*FLEN/8, x4, x1, x2)

inst_385:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e4484 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0fe7df and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1ff244 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e4484; op2val:0x3e0fe7df;
op3val:0x7d1ff244; valaddr_reg:x3; val_offset:1155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1155*FLEN/8, x4, x1, x2)

inst_386:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e4484 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0fe7df and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1ff244 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e4484; op2val:0x3e0fe7df;
op3val:0x7d1ff244; valaddr_reg:x3; val_offset:1158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1158*FLEN/8, x4, x1, x2)

inst_387:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e4484 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0fe7df and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1ff244 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e4484; op2val:0x3e0fe7df;
op3val:0x7d1ff244; valaddr_reg:x3; val_offset:1161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1161*FLEN/8, x4, x1, x2)

inst_388:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e4484 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0fe7df and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1ff244 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e4484; op2val:0x3e0fe7df;
op3val:0x7d1ff244; valaddr_reg:x3; val_offset:1164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1164*FLEN/8, x4, x1, x2)

inst_389:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e4484 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0fe7df and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1ff244 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e4484; op2val:0x3e0fe7df;
op3val:0x7d1ff244; valaddr_reg:x3; val_offset:1167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1167*FLEN/8, x4, x1, x2)

inst_390:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e7599 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1380c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x242a5e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e7599; op2val:0x401380c4;
op3val:0x7f242a5e; valaddr_reg:x3; val_offset:1170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)

inst_391:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e7599 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1380c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x242a5e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e7599; op2val:0x401380c4;
op3val:0x7f242a5e; valaddr_reg:x3; val_offset:1173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1173*FLEN/8, x4, x1, x2)

inst_392:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e7599 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1380c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x242a5e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e7599; op2val:0x401380c4;
op3val:0x7f242a5e; valaddr_reg:x3; val_offset:1176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1176*FLEN/8, x4, x1, x2)

inst_393:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e7599 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1380c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x242a5e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e7599; op2val:0x401380c4;
op3val:0x7f242a5e; valaddr_reg:x3; val_offset:1179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1179*FLEN/8, x4, x1, x2)

inst_394:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e7599 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1380c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x242a5e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e7599; op2val:0x401380c4;
op3val:0x7f242a5e; valaddr_reg:x3; val_offset:1182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1182*FLEN/8, x4, x1, x2)

inst_395:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4a69 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0ed4a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fe49a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4a69; op2val:0x400ed4a6;
op3val:0x7f1fe49a; valaddr_reg:x3; val_offset:1185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1185*FLEN/8, x4, x1, x2)

inst_396:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4a69 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0ed4a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fe49a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4a69; op2val:0x400ed4a6;
op3val:0x7f1fe49a; valaddr_reg:x3; val_offset:1188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1188*FLEN/8, x4, x1, x2)

inst_397:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4a69 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0ed4a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fe49a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4a69; op2val:0x400ed4a6;
op3val:0x7f1fe49a; valaddr_reg:x3; val_offset:1191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1191*FLEN/8, x4, x1, x2)

inst_398:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4a69 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0ed4a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fe49a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4a69; op2val:0x400ed4a6;
op3val:0x7f1fe49a; valaddr_reg:x3; val_offset:1194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1194*FLEN/8, x4, x1, x2)

inst_399:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4a69 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0ed4a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1fe49a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4a69; op2val:0x400ed4a6;
op3val:0x7f1fe49a; valaddr_reg:x3; val_offset:1197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1197*FLEN/8, x4, x1, x2)

inst_400:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:1200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)

inst_401:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:1203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1203*FLEN/8, x4, x1, x2)

inst_402:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:1206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1206*FLEN/8, x4, x1, x2)

inst_403:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:1209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1209*FLEN/8, x4, x1, x2)

inst_404:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f4b27 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0415cd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x13dde9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f4b27; op2val:0x400415cd;
op3val:0x7f13dde9; valaddr_reg:x3; val_offset:1212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1212*FLEN/8, x4, x1, x2)

inst_405:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:1215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1215*FLEN/8, x4, x1, x2)

inst_406:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:1218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1218*FLEN/8, x4, x1, x2)

inst_407:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:1221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1221*FLEN/8, x4, x1, x2)

inst_408:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:1224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1224*FLEN/8, x4, x1, x2)

inst_409:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10ec66 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x03fd1f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x157088 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90ec66; op2val:0x3f83fd1f;
op3val:0x7e957088; valaddr_reg:x3; val_offset:1227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1227*FLEN/8, x4, x1, x2)

inst_410:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10f39b and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f4d9f and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6ac1db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90f39b; op2val:0x3f4f4d9f;
op3val:0x7e6ac1db; valaddr_reg:x3; val_offset:1230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)

inst_411:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10f39b and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f4d9f and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6ac1db and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90f39b; op2val:0x3f4f4d9f;
op3val:0x7e6ac1db; valaddr_reg:x3; val_offset:1233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1233*FLEN/8, x4, x1, x2)

inst_412:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10f39b and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f4d9f and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6ac1db and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90f39b; op2val:0x3f4f4d9f;
op3val:0x7e6ac1db; valaddr_reg:x3; val_offset:1236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1236*FLEN/8, x4, x1, x2)

inst_413:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10f39b and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f4d9f and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6ac1db and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90f39b; op2val:0x3f4f4d9f;
op3val:0x7e6ac1db; valaddr_reg:x3; val_offset:1239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1239*FLEN/8, x4, x1, x2)

inst_414:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10f39b and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f4d9f and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6ac1db and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90f39b; op2val:0x3f4f4d9f;
op3val:0x7e6ac1db; valaddr_reg:x3; val_offset:1242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1242*FLEN/8, x4, x1, x2)

inst_415:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12131e and fs2 == 0 and fe2 == 0x7d and fm2 == 0x296684 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x41523c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92131e; op2val:0x3ea96684;
op3val:0x7dc1523c; valaddr_reg:x3; val_offset:1245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1245*FLEN/8, x4, x1, x2)

inst_416:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12131e and fs2 == 0 and fe2 == 0x7d and fm2 == 0x296684 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x41523c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92131e; op2val:0x3ea96684;
op3val:0x7dc1523c; valaddr_reg:x3; val_offset:1248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1248*FLEN/8, x4, x1, x2)

inst_417:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12131e and fs2 == 0 and fe2 == 0x7d and fm2 == 0x296684 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x41523c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92131e; op2val:0x3ea96684;
op3val:0x7dc1523c; valaddr_reg:x3; val_offset:1251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1251*FLEN/8, x4, x1, x2)

inst_418:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12131e and fs2 == 0 and fe2 == 0x7d and fm2 == 0x296684 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x41523c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92131e; op2val:0x3ea96684;
op3val:0x7dc1523c; valaddr_reg:x3; val_offset:1254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1254*FLEN/8, x4, x1, x2)

inst_419:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12131e and fs2 == 0 and fe2 == 0x7d and fm2 == 0x296684 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x41523c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92131e; op2val:0x3ea96684;
op3val:0x7dc1523c; valaddr_reg:x3; val_offset:1257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1257*FLEN/8, x4, x1, x2)

inst_420:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1255c9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x141b63 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x295281 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9255c9; op2val:0x3f941b63;
op3val:0x7ea95281; valaddr_reg:x3; val_offset:1260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)

inst_421:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1255c9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x141b63 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x295281 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9255c9; op2val:0x3f941b63;
op3val:0x7ea95281; valaddr_reg:x3; val_offset:1263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1263*FLEN/8, x4, x1, x2)

inst_422:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1255c9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x141b63 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x295281 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9255c9; op2val:0x3f941b63;
op3val:0x7ea95281; valaddr_reg:x3; val_offset:1266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1266*FLEN/8, x4, x1, x2)

inst_423:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1255c9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x141b63 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x295281 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9255c9; op2val:0x3f941b63;
op3val:0x7ea95281; valaddr_reg:x3; val_offset:1269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1269*FLEN/8, x4, x1, x2)

inst_424:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1255c9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x141b63 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x295281 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9255c9; op2val:0x3f941b63;
op3val:0x7ea95281; valaddr_reg:x3; val_offset:1272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1272*FLEN/8, x4, x1, x2)

inst_425:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x136b51 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45fd37 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6406cc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e936b51; op2val:0x3fc5fd37;
op3val:0x7ee406cc; valaddr_reg:x3; val_offset:1275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1275*FLEN/8, x4, x1, x2)

inst_426:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x136b51 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45fd37 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6406cc and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e936b51; op2val:0x3fc5fd37;
op3val:0x7ee406cc; valaddr_reg:x3; val_offset:1278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1278*FLEN/8, x4, x1, x2)

inst_427:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x136b51 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45fd37 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6406cc and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e936b51; op2val:0x3fc5fd37;
op3val:0x7ee406cc; valaddr_reg:x3; val_offset:1281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1281*FLEN/8, x4, x1, x2)

inst_428:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x136b51 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45fd37 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6406cc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e936b51; op2val:0x3fc5fd37;
op3val:0x7ee406cc; valaddr_reg:x3; val_offset:1284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1284*FLEN/8, x4, x1, x2)

inst_429:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x136b51 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45fd37 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6406cc and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e936b51; op2val:0x3fc5fd37;
op3val:0x7ee406cc; valaddr_reg:x3; val_offset:1287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1287*FLEN/8, x4, x1, x2)

inst_430:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x137bbb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fe828 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6f8d98 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e937bbb; op2val:0x3fcfe828;
op3val:0x7eef8d98; valaddr_reg:x3; val_offset:1290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)

inst_431:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x137bbb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fe828 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6f8d98 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e937bbb; op2val:0x3fcfe828;
op3val:0x7eef8d98; valaddr_reg:x3; val_offset:1293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1293*FLEN/8, x4, x1, x2)

inst_432:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x137bbb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fe828 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6f8d98 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e937bbb; op2val:0x3fcfe828;
op3val:0x7eef8d98; valaddr_reg:x3; val_offset:1296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1296*FLEN/8, x4, x1, x2)

inst_433:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x137bbb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fe828 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6f8d98 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e937bbb; op2val:0x3fcfe828;
op3val:0x7eef8d98; valaddr_reg:x3; val_offset:1299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1299*FLEN/8, x4, x1, x2)

inst_434:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x137bbb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fe828 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6f8d98 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e937bbb; op2val:0x3fcfe828;
op3val:0x7eef8d98; valaddr_reg:x3; val_offset:1302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1302*FLEN/8, x4, x1, x2)

inst_435:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x13b96c and fs2 == 0 and fe2 == 0x7c and fm2 == 0x228cd8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3b993a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e93b96c; op2val:0x3e228cd8;
op3val:0x7d3b993a; valaddr_reg:x3; val_offset:1305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1305*FLEN/8, x4, x1, x2)

inst_436:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x13b96c and fs2 == 0 and fe2 == 0x7c and fm2 == 0x228cd8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3b993a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e93b96c; op2val:0x3e228cd8;
op3val:0x7d3b993a; valaddr_reg:x3; val_offset:1308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1308*FLEN/8, x4, x1, x2)

inst_437:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x13b96c and fs2 == 0 and fe2 == 0x7c and fm2 == 0x228cd8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3b993a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e93b96c; op2val:0x3e228cd8;
op3val:0x7d3b993a; valaddr_reg:x3; val_offset:1311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1311*FLEN/8, x4, x1, x2)

inst_438:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x13b96c and fs2 == 0 and fe2 == 0x7c and fm2 == 0x228cd8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3b993a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e93b96c; op2val:0x3e228cd8;
op3val:0x7d3b993a; valaddr_reg:x3; val_offset:1314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1314*FLEN/8, x4, x1, x2)

inst_439:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x13b96c and fs2 == 0 and fe2 == 0x7c and fm2 == 0x228cd8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3b993a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e93b96c; op2val:0x3e228cd8;
op3val:0x7d3b993a; valaddr_reg:x3; val_offset:1317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1317*FLEN/8, x4, x1, x2)

inst_440:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x151c59 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x131231 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2b53c0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e951c59; op2val:0x3f131231;
op3val:0x7e2b53c0; valaddr_reg:x3; val_offset:1320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)

inst_441:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x151c59 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x131231 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2b53c0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e951c59; op2val:0x3f131231;
op3val:0x7e2b53c0; valaddr_reg:x3; val_offset:1323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1323*FLEN/8, x4, x1, x2)

inst_442:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x151c59 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x131231 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2b53c0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e951c59; op2val:0x3f131231;
op3val:0x7e2b53c0; valaddr_reg:x3; val_offset:1326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1326*FLEN/8, x4, x1, x2)

inst_443:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x151c59 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x131231 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2b53c0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e951c59; op2val:0x3f131231;
op3val:0x7e2b53c0; valaddr_reg:x3; val_offset:1329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1329*FLEN/8, x4, x1, x2)

inst_444:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x151c59 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x131231 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2b53c0 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e951c59; op2val:0x3f131231;
op3val:0x7e2b53c0; valaddr_reg:x3; val_offset:1332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1332*FLEN/8, x4, x1, x2)

inst_445:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18a4f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x209a40 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3f8620 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98a4f0; op2val:0x40209a40;
op3val:0x7f3f8620; valaddr_reg:x3; val_offset:1335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1335*FLEN/8, x4, x1, x2)

inst_446:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18a4f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x209a40 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3f8620 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98a4f0; op2val:0x40209a40;
op3val:0x7f3f8620; valaddr_reg:x3; val_offset:1338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1338*FLEN/8, x4, x1, x2)

inst_447:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18a4f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x209a40 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3f8620 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98a4f0; op2val:0x40209a40;
op3val:0x7f3f8620; valaddr_reg:x3; val_offset:1341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1341*FLEN/8, x4, x1, x2)

inst_448:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18a4f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x209a40 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3f8620 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98a4f0; op2val:0x40209a40;
op3val:0x7f3f8620; valaddr_reg:x3; val_offset:1344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1344*FLEN/8, x4, x1, x2)

inst_449:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18a4f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x209a40 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3f8620 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98a4f0; op2val:0x40209a40;
op3val:0x7f3f8620; valaddr_reg:x3; val_offset:1347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1347*FLEN/8, x4, x1, x2)

inst_450:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18f0ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1cd557 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3b643a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98f0ab; op2val:0x3f9cd557;
op3val:0x7ebb643a; valaddr_reg:x3; val_offset:1350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)

inst_451:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18f0ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1cd557 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3b643a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98f0ab; op2val:0x3f9cd557;
op3val:0x7ebb643a; valaddr_reg:x3; val_offset:1353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1353*FLEN/8, x4, x1, x2)

inst_452:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18f0ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1cd557 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3b643a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98f0ab; op2val:0x3f9cd557;
op3val:0x7ebb643a; valaddr_reg:x3; val_offset:1356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1356*FLEN/8, x4, x1, x2)

inst_453:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18f0ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1cd557 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3b643a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98f0ab; op2val:0x3f9cd557;
op3val:0x7ebb643a; valaddr_reg:x3; val_offset:1359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1359*FLEN/8, x4, x1, x2)

inst_454:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18f0ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1cd557 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3b643a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98f0ab; op2val:0x3f9cd557;
op3val:0x7ebb643a; valaddr_reg:x3; val_offset:1362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1362*FLEN/8, x4, x1, x2)

inst_455:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d149a and fs2 == 0 and fe2 == 0x7c and fm2 == 0x571bda and fs3 == 0 and fe3 == 0xfb and fm3 == 0x03fd65 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9d149a; op2val:0x3e571bda;
op3val:0x7d83fd65; valaddr_reg:x3; val_offset:1365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1365*FLEN/8, x4, x1, x2)

inst_456:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d149a and fs2 == 0 and fe2 == 0x7c and fm2 == 0x571bda and fs3 == 0 and fe3 == 0xfb and fm3 == 0x03fd65 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9d149a; op2val:0x3e571bda;
op3val:0x7d83fd65; valaddr_reg:x3; val_offset:1368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1368*FLEN/8, x4, x1, x2)

inst_457:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d149a and fs2 == 0 and fe2 == 0x7c and fm2 == 0x571bda and fs3 == 0 and fe3 == 0xfb and fm3 == 0x03fd65 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9d149a; op2val:0x3e571bda;
op3val:0x7d83fd65; valaddr_reg:x3; val_offset:1371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1371*FLEN/8, x4, x1, x2)

inst_458:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d149a and fs2 == 0 and fe2 == 0x7c and fm2 == 0x571bda and fs3 == 0 and fe3 == 0xfb and fm3 == 0x03fd65 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9d149a; op2val:0x3e571bda;
op3val:0x7d83fd65; valaddr_reg:x3; val_offset:1374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1374*FLEN/8, x4, x1, x2)

inst_459:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d149a and fs2 == 0 and fe2 == 0x7c and fm2 == 0x571bda and fs3 == 0 and fe3 == 0xfb and fm3 == 0x03fd65 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9d149a; op2val:0x3e571bda;
op3val:0x7d83fd65; valaddr_reg:x3; val_offset:1377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1377*FLEN/8, x4, x1, x2)

inst_460:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2828cf and fs2 == 0 and fe2 == 0x7e and fm2 == 0x153dda and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4410c4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea828cf; op2val:0x3f153dda;
op3val:0x7e4410c4; valaddr_reg:x3; val_offset:1380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)

inst_461:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2828cf and fs2 == 0 and fe2 == 0x7e and fm2 == 0x153dda and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4410c4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea828cf; op2val:0x3f153dda;
op3val:0x7e4410c4; valaddr_reg:x3; val_offset:1383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1383*FLEN/8, x4, x1, x2)

inst_462:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2828cf and fs2 == 0 and fe2 == 0x7e and fm2 == 0x153dda and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4410c4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea828cf; op2val:0x3f153dda;
op3val:0x7e4410c4; valaddr_reg:x3; val_offset:1386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1386*FLEN/8, x4, x1, x2)

inst_463:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2828cf and fs2 == 0 and fe2 == 0x7e and fm2 == 0x153dda and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4410c4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea828cf; op2val:0x3f153dda;
op3val:0x7e4410c4; valaddr_reg:x3; val_offset:1389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1389*FLEN/8, x4, x1, x2)

inst_464:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2828cf and fs2 == 0 and fe2 == 0x7e and fm2 == 0x153dda and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4410c4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea828cf; op2val:0x3f153dda;
op3val:0x7e4410c4; valaddr_reg:x3; val_offset:1392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1392*FLEN/8, x4, x1, x2)

inst_465:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2a4148 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x696e25 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x1b3eab and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaa4148; op2val:0x3ee96e25;
op3val:0x7e1b3eab; valaddr_reg:x3; val_offset:1395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1395*FLEN/8, x4, x1, x2)

inst_466:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2a4148 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x696e25 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x1b3eab and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaa4148; op2val:0x3ee96e25;
op3val:0x7e1b3eab; valaddr_reg:x3; val_offset:1398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1398*FLEN/8, x4, x1, x2)

inst_467:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2a4148 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x696e25 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x1b3eab and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaa4148; op2val:0x3ee96e25;
op3val:0x7e1b3eab; valaddr_reg:x3; val_offset:1401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1401*FLEN/8, x4, x1, x2)

inst_468:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2a4148 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x696e25 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x1b3eab and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaa4148; op2val:0x3ee96e25;
op3val:0x7e1b3eab; valaddr_reg:x3; val_offset:1404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1404*FLEN/8, x4, x1, x2)

inst_469:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2a4148 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x696e25 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x1b3eab and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaa4148; op2val:0x3ee96e25;
op3val:0x7e1b3eab; valaddr_reg:x3; val_offset:1407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1407*FLEN/8, x4, x1, x2)

inst_470:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b2c70 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x64e6ed and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x190dfc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eab2c70; op2val:0x3ce4e6ed;
op3val:0x7c190dfc; valaddr_reg:x3; val_offset:1410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)

inst_471:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b2c70 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x64e6ed and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x190dfc and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eab2c70; op2val:0x3ce4e6ed;
op3val:0x7c190dfc; valaddr_reg:x3; val_offset:1413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1413*FLEN/8, x4, x1, x2)

inst_472:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b2c70 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x64e6ed and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x190dfc and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eab2c70; op2val:0x3ce4e6ed;
op3val:0x7c190dfc; valaddr_reg:x3; val_offset:1416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1416*FLEN/8, x4, x1, x2)

inst_473:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b2c70 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x64e6ed and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x190dfc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eab2c70; op2val:0x3ce4e6ed;
op3val:0x7c190dfc; valaddr_reg:x3; val_offset:1419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1419*FLEN/8, x4, x1, x2)

inst_474:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b2c70 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x64e6ed and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x190dfc and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eab2c70; op2val:0x3ce4e6ed;
op3val:0x7c190dfc; valaddr_reg:x3; val_offset:1422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1422*FLEN/8, x4, x1, x2)

inst_475:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:1425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1425*FLEN/8, x4, x1, x2)

inst_476:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:1428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1428*FLEN/8, x4, x1, x2)

inst_477:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:1431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1431*FLEN/8, x4, x1, x2)

inst_478:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:1434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1434*FLEN/8, x4, x1, x2)

inst_479:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2bb8f9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6dee41 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f9a10 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eabb8f9; op2val:0x3fedee41;
op3val:0x7f1f9a10; valaddr_reg:x3; val_offset:1437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1437*FLEN/8, x4, x1, x2)

inst_480:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2c8d9d and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0221ad and fs3 == 0 and fe3 == 0xfa and fm3 == 0x2f6d3b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eac8d9d; op2val:0x3e0221ad;
op3val:0x7d2f6d3b; valaddr_reg:x3; val_offset:1440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)

inst_481:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2c8d9d and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0221ad and fs3 == 0 and fe3 == 0xfa and fm3 == 0x2f6d3b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eac8d9d; op2val:0x3e0221ad;
op3val:0x7d2f6d3b; valaddr_reg:x3; val_offset:1443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1443*FLEN/8, x4, x1, x2)

inst_482:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2c8d9d and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0221ad and fs3 == 0 and fe3 == 0xfa and fm3 == 0x2f6d3b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eac8d9d; op2val:0x3e0221ad;
op3val:0x7d2f6d3b; valaddr_reg:x3; val_offset:1446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1446*FLEN/8, x4, x1, x2)

inst_483:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2c8d9d and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0221ad and fs3 == 0 and fe3 == 0xfa and fm3 == 0x2f6d3b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eac8d9d; op2val:0x3e0221ad;
op3val:0x7d2f6d3b; valaddr_reg:x3; val_offset:1449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1449*FLEN/8, x4, x1, x2)

inst_484:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2c8d9d and fs2 == 0 and fe2 == 0x7c and fm2 == 0x0221ad and fs3 == 0 and fe3 == 0xfa and fm3 == 0x2f6d3b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eac8d9d; op2val:0x3e0221ad;
op3val:0x7d2f6d3b; valaddr_reg:x3; val_offset:1452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1452*FLEN/8, x4, x1, x2)

inst_485:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2d6385 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x037a19 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x321940 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ead6385; op2val:0x40037a19;
op3val:0x7f321940; valaddr_reg:x3; val_offset:1455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1455*FLEN/8, x4, x1, x2)

inst_486:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2d6385 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x037a19 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x321940 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ead6385; op2val:0x40037a19;
op3val:0x7f321940; valaddr_reg:x3; val_offset:1458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1458*FLEN/8, x4, x1, x2)

inst_487:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2d6385 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x037a19 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x321940 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ead6385; op2val:0x40037a19;
op3val:0x7f321940; valaddr_reg:x3; val_offset:1461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1461*FLEN/8, x4, x1, x2)

inst_488:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2d6385 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x037a19 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x321940 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ead6385; op2val:0x40037a19;
op3val:0x7f321940; valaddr_reg:x3; val_offset:1464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1464*FLEN/8, x4, x1, x2)

inst_489:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2d6385 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x037a19 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x321940 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ead6385; op2val:0x40037a19;
op3val:0x7f321940; valaddr_reg:x3; val_offset:1467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1467*FLEN/8, x4, x1, x2)

inst_490:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2deee7 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0aa40d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c647e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eadeee7; op2val:0x400aa40d;
op3val:0x7f3c647e; valaddr_reg:x3; val_offset:1470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)

inst_491:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2deee7 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0aa40d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c647e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eadeee7; op2val:0x400aa40d;
op3val:0x7f3c647e; valaddr_reg:x3; val_offset:1473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1473*FLEN/8, x4, x1, x2)

inst_492:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2deee7 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0aa40d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c647e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eadeee7; op2val:0x400aa40d;
op3val:0x7f3c647e; valaddr_reg:x3; val_offset:1476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1476*FLEN/8, x4, x1, x2)

inst_493:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2deee7 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0aa40d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c647e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eadeee7; op2val:0x400aa40d;
op3val:0x7f3c647e; valaddr_reg:x3; val_offset:1479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1479*FLEN/8, x4, x1, x2)

inst_494:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2deee7 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0aa40d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3c647e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eadeee7; op2val:0x400aa40d;
op3val:0x7f3c647e; valaddr_reg:x3; val_offset:1482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1482*FLEN/8, x4, x1, x2)

inst_495:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2eef4a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x61d6f5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1a5333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaeef4a; op2val:0x3fe1d6f5;
op3val:0x7f1a5333; valaddr_reg:x3; val_offset:1485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1485*FLEN/8, x4, x1, x2)

inst_496:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2eef4a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x61d6f5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1a5333 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaeef4a; op2val:0x3fe1d6f5;
op3val:0x7f1a5333; valaddr_reg:x3; val_offset:1488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1488*FLEN/8, x4, x1, x2)

inst_497:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2eef4a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x61d6f5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1a5333 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaeef4a; op2val:0x3fe1d6f5;
op3val:0x7f1a5333; valaddr_reg:x3; val_offset:1491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1491*FLEN/8, x4, x1, x2)

inst_498:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2eef4a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x61d6f5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1a5333 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaeef4a; op2val:0x3fe1d6f5;
op3val:0x7f1a5333; valaddr_reg:x3; val_offset:1494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1494*FLEN/8, x4, x1, x2)

inst_499:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2eef4a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x61d6f5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1a5333 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaeef4a; op2val:0x3fe1d6f5;
op3val:0x7f1a5333; valaddr_reg:x3; val_offset:1497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1497*FLEN/8, x4, x1, x2)

inst_500:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2f0189 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x09b1fd and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3c42ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaf0189; op2val:0x3e09b1fd;
op3val:0x7d3c42ff; valaddr_reg:x3; val_offset:1500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)

inst_501:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2f0189 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x09b1fd and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3c42ff and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaf0189; op2val:0x3e09b1fd;
op3val:0x7d3c42ff; valaddr_reg:x3; val_offset:1503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1503*FLEN/8, x4, x1, x2)

inst_502:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2f0189 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x09b1fd and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3c42ff and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaf0189; op2val:0x3e09b1fd;
op3val:0x7d3c42ff; valaddr_reg:x3; val_offset:1506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1506*FLEN/8, x4, x1, x2)

inst_503:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2f0189 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x09b1fd and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3c42ff and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaf0189; op2val:0x3e09b1fd;
op3val:0x7d3c42ff; valaddr_reg:x3; val_offset:1509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1509*FLEN/8, x4, x1, x2)

inst_504:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2f0189 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x09b1fd and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3c42ff and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaf0189; op2val:0x3e09b1fd;
op3val:0x7d3c42ff; valaddr_reg:x3; val_offset:1512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1512*FLEN/8, x4, x1, x2)

inst_505:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31ae90 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x78da00 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2cb86b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1ae90; op2val:0x3ff8da00;
op3val:0x7f2cb86b; valaddr_reg:x3; val_offset:1515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1515*FLEN/8, x4, x1, x2)

inst_506:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31ae90 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x78da00 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2cb86b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1ae90; op2val:0x3ff8da00;
op3val:0x7f2cb86b; valaddr_reg:x3; val_offset:1518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1518*FLEN/8, x4, x1, x2)

inst_507:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31ae90 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x78da00 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2cb86b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1ae90; op2val:0x3ff8da00;
op3val:0x7f2cb86b; valaddr_reg:x3; val_offset:1521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1521*FLEN/8, x4, x1, x2)

inst_508:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31ae90 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x78da00 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2cb86b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1ae90; op2val:0x3ff8da00;
op3val:0x7f2cb86b; valaddr_reg:x3; val_offset:1524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1524*FLEN/8, x4, x1, x2)

inst_509:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31ae90 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x78da00 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2cb86b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1ae90; op2val:0x3ff8da00;
op3val:0x7f2cb86b; valaddr_reg:x3; val_offset:1527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1527*FLEN/8, x4, x1, x2)

inst_510:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3419f9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5cbe2f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1b4c1e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb419f9; op2val:0x3f5cbe2f;
op3val:0x7e9b4c1e; valaddr_reg:x3; val_offset:1530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)

inst_511:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3419f9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5cbe2f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1b4c1e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb419f9; op2val:0x3f5cbe2f;
op3val:0x7e9b4c1e; valaddr_reg:x3; val_offset:1533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1533*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_512:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3419f9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5cbe2f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1b4c1e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb419f9; op2val:0x3f5cbe2f;
op3val:0x7e9b4c1e; valaddr_reg:x3; val_offset:1536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1536*FLEN/8, x4, x1, x2)

inst_513:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3419f9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5cbe2f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1b4c1e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb419f9; op2val:0x3f5cbe2f;
op3val:0x7e9b4c1e; valaddr_reg:x3; val_offset:1539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1539*FLEN/8, x4, x1, x2)

inst_514:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3419f9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5cbe2f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1b4c1e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb419f9; op2val:0x3f5cbe2f;
op3val:0x7e9b4c1e; valaddr_reg:x3; val_offset:1542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1542*FLEN/8, x4, x1, x2)

inst_515:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:1545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1545*FLEN/8, x4, x1, x2)

inst_516:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:1548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1548*FLEN/8, x4, x1, x2)

inst_517:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:1551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1551*FLEN/8, x4, x1, x2)

inst_518:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:1554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1554*FLEN/8, x4, x1, x2)

inst_519:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3493df and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4ecb22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x11de47 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb493df; op2val:0x3fcecb22;
op3val:0x7f11de47; valaddr_reg:x3; val_offset:1557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1557*FLEN/8, x4, x1, x2)

inst_520:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34a6ae and fs2 == 0 and fe2 == 0x7f and fm2 == 0x65109e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x21a4d4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4a6ae; op2val:0x3fe5109e;
op3val:0x7f21a4d4; valaddr_reg:x3; val_offset:1560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)

inst_521:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34a6ae and fs2 == 0 and fe2 == 0x7f and fm2 == 0x65109e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x21a4d4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4a6ae; op2val:0x3fe5109e;
op3val:0x7f21a4d4; valaddr_reg:x3; val_offset:1563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1563*FLEN/8, x4, x1, x2)

inst_522:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34a6ae and fs2 == 0 and fe2 == 0x7f and fm2 == 0x65109e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x21a4d4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4a6ae; op2val:0x3fe5109e;
op3val:0x7f21a4d4; valaddr_reg:x3; val_offset:1566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1566*FLEN/8, x4, x1, x2)

inst_523:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34a6ae and fs2 == 0 and fe2 == 0x7f and fm2 == 0x65109e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x21a4d4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4a6ae; op2val:0x3fe5109e;
op3val:0x7f21a4d4; valaddr_reg:x3; val_offset:1569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1569*FLEN/8, x4, x1, x2)

inst_524:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34a6ae and fs2 == 0 and fe2 == 0x7f and fm2 == 0x65109e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x21a4d4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4a6ae; op2val:0x3fe5109e;
op3val:0x7f21a4d4; valaddr_reg:x3; val_offset:1572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1572*FLEN/8, x4, x1, x2)

inst_525:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:1575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1575*FLEN/8, x4, x1, x2)

inst_526:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:1578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1578*FLEN/8, x4, x1, x2)

inst_527:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:1581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1581*FLEN/8, x4, x1, x2)

inst_528:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:1584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1584*FLEN/8, x4, x1, x2)

inst_529:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d648 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3fcdc7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x077d3c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d648; op2val:0x3fbfcdc7;
op3val:0x7f077d3c; valaddr_reg:x3; val_offset:1587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1587*FLEN/8, x4, x1, x2)

inst_530:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x37c24b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x182086 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5a656b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb7c24b; op2val:0x3e982086;
op3val:0x7dda656b; valaddr_reg:x3; val_offset:1590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)

inst_531:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x37c24b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x182086 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5a656b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb7c24b; op2val:0x3e982086;
op3val:0x7dda656b; valaddr_reg:x3; val_offset:1593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1593*FLEN/8, x4, x1, x2)

inst_532:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x37c24b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x182086 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5a656b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb7c24b; op2val:0x3e982086;
op3val:0x7dda656b; valaddr_reg:x3; val_offset:1596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1596*FLEN/8, x4, x1, x2)

inst_533:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x37c24b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x182086 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5a656b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb7c24b; op2val:0x3e982086;
op3val:0x7dda656b; valaddr_reg:x3; val_offset:1599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1599*FLEN/8, x4, x1, x2)

inst_534:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x37c24b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x182086 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5a656b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb7c24b; op2val:0x3e982086;
op3val:0x7dda656b; valaddr_reg:x3; val_offset:1602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1602*FLEN/8, x4, x1, x2)

inst_535:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x387cb7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0ff35d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4f7a18 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb87cb7; op2val:0x3f0ff35d;
op3val:0x7e4f7a18; valaddr_reg:x3; val_offset:1605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1605*FLEN/8, x4, x1, x2)

inst_536:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x387cb7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0ff35d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4f7a18 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb87cb7; op2val:0x3f0ff35d;
op3val:0x7e4f7a18; valaddr_reg:x3; val_offset:1608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1608*FLEN/8, x4, x1, x2)

inst_537:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x387cb7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0ff35d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4f7a18 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb87cb7; op2val:0x3f0ff35d;
op3val:0x7e4f7a18; valaddr_reg:x3; val_offset:1611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1611*FLEN/8, x4, x1, x2)

inst_538:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x387cb7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0ff35d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4f7a18 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb87cb7; op2val:0x3f0ff35d;
op3val:0x7e4f7a18; valaddr_reg:x3; val_offset:1614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1614*FLEN/8, x4, x1, x2)

inst_539:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x387cb7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0ff35d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4f7a18 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb87cb7; op2val:0x3f0ff35d;
op3val:0x7e4f7a18; valaddr_reg:x3; val_offset:1617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1617*FLEN/8, x4, x1, x2)

inst_540:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:1620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)

inst_541:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:1623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1623*FLEN/8, x4, x1, x2)

inst_542:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:1626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1626*FLEN/8, x4, x1, x2)

inst_543:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:1629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1629*FLEN/8, x4, x1, x2)

inst_544:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x39c1fe and fs2 == 0 and fe2 == 0x7d and fm2 == 0x122c1f and fs3 == 0 and fe3 == 0xfb and fm3 == 0x54214e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb9c1fe; op2val:0x3e922c1f;
op3val:0x7dd4214e; valaddr_reg:x3; val_offset:1632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1632*FLEN/8, x4, x1, x2)

inst_545:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:1635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1635*FLEN/8, x4, x1, x2)

inst_546:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:1638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1638*FLEN/8, x4, x1, x2)

inst_547:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:1641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1641*FLEN/8, x4, x1, x2)

inst_548:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:1644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1644*FLEN/8, x4, x1, x2)

inst_549:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3a40d7 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0a1548 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x48ecdf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eba40d7; op2val:0x3f0a1548;
op3val:0x7e48ecdf; valaddr_reg:x3; val_offset:1647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1647*FLEN/8, x4, x1, x2)

inst_550:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b4351 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc9e9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x16889a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb4351; op2val:0x3fcdc9e9;
op3val:0x7f16889a; valaddr_reg:x3; val_offset:1650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)

inst_551:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b4351 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc9e9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x16889a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb4351; op2val:0x3fcdc9e9;
op3val:0x7f16889a; valaddr_reg:x3; val_offset:1653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1653*FLEN/8, x4, x1, x2)

inst_552:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b4351 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc9e9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x16889a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb4351; op2val:0x3fcdc9e9;
op3val:0x7f16889a; valaddr_reg:x3; val_offset:1656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1656*FLEN/8, x4, x1, x2)

inst_553:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b4351 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc9e9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x16889a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb4351; op2val:0x3fcdc9e9;
op3val:0x7f16889a; valaddr_reg:x3; val_offset:1659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1659*FLEN/8, x4, x1, x2)

inst_554:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b4351 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc9e9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x16889a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb4351; op2val:0x3fcdc9e9;
op3val:0x7f16889a; valaddr_reg:x3; val_offset:1662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1662*FLEN/8, x4, x1, x2)

inst_555:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b69c6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3f1118 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0be06e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb69c6; op2val:0x3f3f1118;
op3val:0x7e8be06e; valaddr_reg:x3; val_offset:1665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1665*FLEN/8, x4, x1, x2)

inst_556:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b69c6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3f1118 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0be06e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb69c6; op2val:0x3f3f1118;
op3val:0x7e8be06e; valaddr_reg:x3; val_offset:1668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1668*FLEN/8, x4, x1, x2)

inst_557:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b69c6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3f1118 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0be06e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb69c6; op2val:0x3f3f1118;
op3val:0x7e8be06e; valaddr_reg:x3; val_offset:1671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1671*FLEN/8, x4, x1, x2)

inst_558:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b69c6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3f1118 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0be06e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb69c6; op2val:0x3f3f1118;
op3val:0x7e8be06e; valaddr_reg:x3; val_offset:1674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1674*FLEN/8, x4, x1, x2)

inst_559:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b69c6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3f1118 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0be06e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb69c6; op2val:0x3f3f1118;
op3val:0x7e8be06e; valaddr_reg:x3; val_offset:1677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1677*FLEN/8, x4, x1, x2)

inst_560:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3ccf7c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7421c1 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x340ea8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebccf7c; op2val:0x3f7421c1;
op3val:0x7eb40ea8; valaddr_reg:x3; val_offset:1680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)

inst_561:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3ccf7c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7421c1 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x340ea8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebccf7c; op2val:0x3f7421c1;
op3val:0x7eb40ea8; valaddr_reg:x3; val_offset:1683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1683*FLEN/8, x4, x1, x2)

inst_562:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3ccf7c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7421c1 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x340ea8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebccf7c; op2val:0x3f7421c1;
op3val:0x7eb40ea8; valaddr_reg:x3; val_offset:1686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1686*FLEN/8, x4, x1, x2)

inst_563:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3ccf7c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7421c1 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x340ea8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebccf7c; op2val:0x3f7421c1;
op3val:0x7eb40ea8; valaddr_reg:x3; val_offset:1689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1689*FLEN/8, x4, x1, x2)

inst_564:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3ccf7c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7421c1 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x340ea8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebccf7c; op2val:0x3f7421c1;
op3val:0x7eb40ea8; valaddr_reg:x3; val_offset:1692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1692*FLEN/8, x4, x1, x2)

inst_565:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3de659 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1bacb3 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x66f527 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebde659; op2val:0x3e1bacb3;
op3val:0x7d66f527; valaddr_reg:x3; val_offset:1695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1695*FLEN/8, x4, x1, x2)

inst_566:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3de659 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1bacb3 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x66f527 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebde659; op2val:0x3e1bacb3;
op3val:0x7d66f527; valaddr_reg:x3; val_offset:1698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1698*FLEN/8, x4, x1, x2)

inst_567:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3de659 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1bacb3 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x66f527 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebde659; op2val:0x3e1bacb3;
op3val:0x7d66f527; valaddr_reg:x3; val_offset:1701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1701*FLEN/8, x4, x1, x2)

inst_568:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3de659 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1bacb3 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x66f527 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebde659; op2val:0x3e1bacb3;
op3val:0x7d66f527; valaddr_reg:x3; val_offset:1704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1704*FLEN/8, x4, x1, x2)

inst_569:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3de659 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1bacb3 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x66f527 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebde659; op2val:0x3e1bacb3;
op3val:0x7d66f527; valaddr_reg:x3; val_offset:1707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1707*FLEN/8, x4, x1, x2)

inst_570:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41f901 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x664779 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2e7bdf and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1f901; op2val:0x3e664779;
op3val:0x7dae7bdf; valaddr_reg:x3; val_offset:1710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)

inst_571:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41f901 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x664779 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2e7bdf and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1f901; op2val:0x3e664779;
op3val:0x7dae7bdf; valaddr_reg:x3; val_offset:1713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1713*FLEN/8, x4, x1, x2)

inst_572:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41f901 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x664779 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2e7bdf and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1f901; op2val:0x3e664779;
op3val:0x7dae7bdf; valaddr_reg:x3; val_offset:1716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1716*FLEN/8, x4, x1, x2)

inst_573:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41f901 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x664779 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2e7bdf and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1f901; op2val:0x3e664779;
op3val:0x7dae7bdf; valaddr_reg:x3; val_offset:1719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1719*FLEN/8, x4, x1, x2)

inst_574:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41f901 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x664779 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2e7bdf and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1f901; op2val:0x3e664779;
op3val:0x7dae7bdf; valaddr_reg:x3; val_offset:1722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1722*FLEN/8, x4, x1, x2)

inst_575:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4535cf and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6f175d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x382f3c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec535cf; op2val:0x3e6f175d;
op3val:0x7db82f3c; valaddr_reg:x3; val_offset:1725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1725*FLEN/8, x4, x1, x2)

inst_576:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4535cf and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6f175d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x382f3c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec535cf; op2val:0x3e6f175d;
op3val:0x7db82f3c; valaddr_reg:x3; val_offset:1728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1728*FLEN/8, x4, x1, x2)

inst_577:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4535cf and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6f175d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x382f3c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec535cf; op2val:0x3e6f175d;
op3val:0x7db82f3c; valaddr_reg:x3; val_offset:1731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1731*FLEN/8, x4, x1, x2)

inst_578:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4535cf and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6f175d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x382f3c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec535cf; op2val:0x3e6f175d;
op3val:0x7db82f3c; valaddr_reg:x3; val_offset:1734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1734*FLEN/8, x4, x1, x2)

inst_579:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4535cf and fs2 == 0 and fe2 == 0x7c and fm2 == 0x6f175d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x382f3c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec535cf; op2val:0x3e6f175d;
op3val:0x7db82f3c; valaddr_reg:x3; val_offset:1737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1737*FLEN/8, x4, x1, x2)

inst_580:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x479ae9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6aedd6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x372d0b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec79ae9; op2val:0x3feaedd6;
op3val:0x7f372d0b; valaddr_reg:x3; val_offset:1740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)

inst_581:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x479ae9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6aedd6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x372d0b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec79ae9; op2val:0x3feaedd6;
op3val:0x7f372d0b; valaddr_reg:x3; val_offset:1743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1743*FLEN/8, x4, x1, x2)

inst_582:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x479ae9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6aedd6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x372d0b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec79ae9; op2val:0x3feaedd6;
op3val:0x7f372d0b; valaddr_reg:x3; val_offset:1746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1746*FLEN/8, x4, x1, x2)

inst_583:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x479ae9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6aedd6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x372d0b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec79ae9; op2val:0x3feaedd6;
op3val:0x7f372d0b; valaddr_reg:x3; val_offset:1749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1749*FLEN/8, x4, x1, x2)

inst_584:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x479ae9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x6aedd6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x372d0b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec79ae9; op2val:0x3feaedd6;
op3val:0x7f372d0b; valaddr_reg:x3; val_offset:1752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1752*FLEN/8, x4, x1, x2)

inst_585:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x47c980 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3f0454 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1512b7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec7c980; op2val:0x3fbf0454;
op3val:0x7f1512b7; valaddr_reg:x3; val_offset:1755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1755*FLEN/8, x4, x1, x2)

inst_586:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x47c980 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3f0454 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1512b7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec7c980; op2val:0x3fbf0454;
op3val:0x7f1512b7; valaddr_reg:x3; val_offset:1758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1758*FLEN/8, x4, x1, x2)

inst_587:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x47c980 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3f0454 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1512b7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec7c980; op2val:0x3fbf0454;
op3val:0x7f1512b7; valaddr_reg:x3; val_offset:1761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1761*FLEN/8, x4, x1, x2)

inst_588:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x47c980 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3f0454 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1512b7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec7c980; op2val:0x3fbf0454;
op3val:0x7f1512b7; valaddr_reg:x3; val_offset:1764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1764*FLEN/8, x4, x1, x2)

inst_589:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x47c980 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3f0454 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1512b7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec7c980; op2val:0x3fbf0454;
op3val:0x7f1512b7; valaddr_reg:x3; val_offset:1767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1767*FLEN/8, x4, x1, x2)

inst_590:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:1770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)

inst_591:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:1773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1773*FLEN/8, x4, x1, x2)

inst_592:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:1776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1776*FLEN/8, x4, x1, x2)

inst_593:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:1779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1779*FLEN/8, x4, x1, x2)

inst_594:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4eb58d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x222e36 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x02f434 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eceb58d; op2val:0x3fa22e36;
op3val:0x7f02f434; valaddr_reg:x3; val_offset:1782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1782*FLEN/8, x4, x1, x2)

inst_595:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x50110c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x236d8e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x04d3e6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed0110c; op2val:0x3f236d8e;
op3val:0x7e84d3e6; valaddr_reg:x3; val_offset:1785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1785*FLEN/8, x4, x1, x2)

inst_596:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x50110c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x236d8e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x04d3e6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed0110c; op2val:0x3f236d8e;
op3val:0x7e84d3e6; valaddr_reg:x3; val_offset:1788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1788*FLEN/8, x4, x1, x2)

inst_597:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x50110c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x236d8e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x04d3e6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed0110c; op2val:0x3f236d8e;
op3val:0x7e84d3e6; valaddr_reg:x3; val_offset:1791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1791*FLEN/8, x4, x1, x2)

inst_598:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x50110c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x236d8e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x04d3e6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed0110c; op2val:0x3f236d8e;
op3val:0x7e84d3e6; valaddr_reg:x3; val_offset:1794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1794*FLEN/8, x4, x1, x2)

inst_599:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x50110c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x236d8e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x04d3e6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed0110c; op2val:0x3f236d8e;
op3val:0x7e84d3e6; valaddr_reg:x3; val_offset:1797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1797*FLEN/8, x4, x1, x2)

inst_600:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x513405 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fb5c9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x29bd9e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed13405; op2val:0x3fcfb5c9;
op3val:0x7f29bd9e; valaddr_reg:x3; val_offset:1800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)

inst_601:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x513405 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fb5c9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x29bd9e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed13405; op2val:0x3fcfb5c9;
op3val:0x7f29bd9e; valaddr_reg:x3; val_offset:1803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1803*FLEN/8, x4, x1, x2)

inst_602:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x513405 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fb5c9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x29bd9e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed13405; op2val:0x3fcfb5c9;
op3val:0x7f29bd9e; valaddr_reg:x3; val_offset:1806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1806*FLEN/8, x4, x1, x2)

inst_603:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x513405 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fb5c9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x29bd9e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed13405; op2val:0x3fcfb5c9;
op3val:0x7f29bd9e; valaddr_reg:x3; val_offset:1809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1809*FLEN/8, x4, x1, x2)

inst_604:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x513405 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4fb5c9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x29bd9e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed13405; op2val:0x3fcfb5c9;
op3val:0x7f29bd9e; valaddr_reg:x3; val_offset:1812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1812*FLEN/8, x4, x1, x2)

inst_605:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5218a0 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x592123 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x323212 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed218a0; op2val:0x3f592123;
op3val:0x7eb23212; valaddr_reg:x3; val_offset:1815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1815*FLEN/8, x4, x1, x2)

inst_606:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5218a0 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x592123 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x323212 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed218a0; op2val:0x3f592123;
op3val:0x7eb23212; valaddr_reg:x3; val_offset:1818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1818*FLEN/8, x4, x1, x2)

inst_607:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5218a0 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x592123 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x323212 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed218a0; op2val:0x3f592123;
op3val:0x7eb23212; valaddr_reg:x3; val_offset:1821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1821*FLEN/8, x4, x1, x2)

inst_608:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5218a0 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x592123 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x323212 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed218a0; op2val:0x3f592123;
op3val:0x7eb23212; valaddr_reg:x3; val_offset:1824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1824*FLEN/8, x4, x1, x2)

inst_609:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5218a0 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x592123 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x323212 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed218a0; op2val:0x3f592123;
op3val:0x7eb23212; valaddr_reg:x3; val_offset:1827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1827*FLEN/8, x4, x1, x2)

inst_610:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x539b49 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x19c970 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e3ca1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed39b49; op2val:0x3f99c970;
op3val:0x7efe3ca1; valaddr_reg:x3; val_offset:1830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)

inst_611:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x539b49 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x19c970 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e3ca1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed39b49; op2val:0x3f99c970;
op3val:0x7efe3ca1; valaddr_reg:x3; val_offset:1833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1833*FLEN/8, x4, x1, x2)

inst_612:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x539b49 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x19c970 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e3ca1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed39b49; op2val:0x3f99c970;
op3val:0x7efe3ca1; valaddr_reg:x3; val_offset:1836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1836*FLEN/8, x4, x1, x2)

inst_613:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x539b49 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x19c970 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e3ca1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed39b49; op2val:0x3f99c970;
op3val:0x7efe3ca1; valaddr_reg:x3; val_offset:1839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1839*FLEN/8, x4, x1, x2)

inst_614:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x539b49 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x19c970 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e3ca1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed39b49; op2val:0x3f99c970;
op3val:0x7efe3ca1; valaddr_reg:x3; val_offset:1842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1842*FLEN/8, x4, x1, x2)

inst_615:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x58669e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0e6227 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70b7c8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed8669e; op2val:0x3f8e6227;
op3val:0x7ef0b7c8; valaddr_reg:x3; val_offset:1845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1845*FLEN/8, x4, x1, x2)

inst_616:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x58669e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0e6227 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70b7c8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed8669e; op2val:0x3f8e6227;
op3val:0x7ef0b7c8; valaddr_reg:x3; val_offset:1848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1848*FLEN/8, x4, x1, x2)

inst_617:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x58669e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0e6227 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70b7c8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed8669e; op2val:0x3f8e6227;
op3val:0x7ef0b7c8; valaddr_reg:x3; val_offset:1851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1851*FLEN/8, x4, x1, x2)

inst_618:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x58669e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0e6227 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70b7c8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed8669e; op2val:0x3f8e6227;
op3val:0x7ef0b7c8; valaddr_reg:x3; val_offset:1854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1854*FLEN/8, x4, x1, x2)

inst_619:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x58669e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0e6227 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70b7c8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed8669e; op2val:0x3f8e6227;
op3val:0x7ef0b7c8; valaddr_reg:x3; val_offset:1857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1857*FLEN/8, x4, x1, x2)

inst_620:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5913e5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x50d3e6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3113d9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed913e5; op2val:0x3fd0d3e6;
op3val:0x7f3113d9; valaddr_reg:x3; val_offset:1860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)

inst_621:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5913e5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x50d3e6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3113d9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed913e5; op2val:0x3fd0d3e6;
op3val:0x7f3113d9; valaddr_reg:x3; val_offset:1863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1863*FLEN/8, x4, x1, x2)

inst_622:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5913e5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x50d3e6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3113d9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed913e5; op2val:0x3fd0d3e6;
op3val:0x7f3113d9; valaddr_reg:x3; val_offset:1866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1866*FLEN/8, x4, x1, x2)

inst_623:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5913e5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x50d3e6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3113d9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed913e5; op2val:0x3fd0d3e6;
op3val:0x7f3113d9; valaddr_reg:x3; val_offset:1869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1869*FLEN/8, x4, x1, x2)

inst_624:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5913e5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x50d3e6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3113d9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed913e5; op2val:0x3fd0d3e6;
op3val:0x7f3113d9; valaddr_reg:x3; val_offset:1872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1872*FLEN/8, x4, x1, x2)

inst_625:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5b9c6a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2446a0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0ceccb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edb9c6a; op2val:0x3fa446a0;
op3val:0x7f0ceccb; valaddr_reg:x3; val_offset:1875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1875*FLEN/8, x4, x1, x2)

inst_626:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5b9c6a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2446a0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0ceccb and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edb9c6a; op2val:0x3fa446a0;
op3val:0x7f0ceccb; valaddr_reg:x3; val_offset:1878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1878*FLEN/8, x4, x1, x2)

inst_627:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5b9c6a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2446a0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0ceccb and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edb9c6a; op2val:0x3fa446a0;
op3val:0x7f0ceccb; valaddr_reg:x3; val_offset:1881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1881*FLEN/8, x4, x1, x2)

inst_628:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5b9c6a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2446a0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0ceccb and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edb9c6a; op2val:0x3fa446a0;
op3val:0x7f0ceccb; valaddr_reg:x3; val_offset:1884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1884*FLEN/8, x4, x1, x2)

inst_629:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5b9c6a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2446a0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0ceccb and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edb9c6a; op2val:0x3fa446a0;
op3val:0x7f0ceccb; valaddr_reg:x3; val_offset:1887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1887*FLEN/8, x4, x1, x2)

inst_630:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:1890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)

inst_631:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:1893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1893*FLEN/8, x4, x1, x2)

inst_632:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:1896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1896*FLEN/8, x4, x1, x2)

inst_633:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:1899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1899*FLEN/8, x4, x1, x2)

inst_634:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x623c76 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1be23d and fs3 == 0 and fe3 == 0xfb and fm3 == 0x09c28b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee23c76; op2val:0x3e1be23d;
op3val:0x7d89c28b; valaddr_reg:x3; val_offset:1902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1902*FLEN/8, x4, x1, x2)

inst_635:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x62d797 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6ccffe and fs3 == 0 and fe3 == 0xfc and fm3 == 0x51d70d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee2d797; op2val:0x3eeccffe;
op3val:0x7e51d70d; valaddr_reg:x3; val_offset:1905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1905*FLEN/8, x4, x1, x2)

inst_636:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x62d797 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6ccffe and fs3 == 0 and fe3 == 0xfc and fm3 == 0x51d70d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee2d797; op2val:0x3eeccffe;
op3val:0x7e51d70d; valaddr_reg:x3; val_offset:1908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1908*FLEN/8, x4, x1, x2)

inst_637:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x62d797 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6ccffe and fs3 == 0 and fe3 == 0xfc and fm3 == 0x51d70d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee2d797; op2val:0x3eeccffe;
op3val:0x7e51d70d; valaddr_reg:x3; val_offset:1911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1911*FLEN/8, x4, x1, x2)

inst_638:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x62d797 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6ccffe and fs3 == 0 and fe3 == 0xfc and fm3 == 0x51d70d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee2d797; op2val:0x3eeccffe;
op3val:0x7e51d70d; valaddr_reg:x3; val_offset:1914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1914*FLEN/8, x4, x1, x2)

inst_639:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x62d797 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6ccffe and fs3 == 0 and fe3 == 0xfc and fm3 == 0x51d70d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee2d797; op2val:0x3eeccffe;
op3val:0x7e51d70d; valaddr_reg:x3; val_offset:1917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1917*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_640:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6334ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3b9bf9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2681e8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee334ab; op2val:0x3fbb9bf9;
op3val:0x7f2681e8; valaddr_reg:x3; val_offset:1920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)

inst_641:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6334ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3b9bf9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2681e8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee334ab; op2val:0x3fbb9bf9;
op3val:0x7f2681e8; valaddr_reg:x3; val_offset:1923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1923*FLEN/8, x4, x1, x2)

inst_642:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6334ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3b9bf9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2681e8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee334ab; op2val:0x3fbb9bf9;
op3val:0x7f2681e8; valaddr_reg:x3; val_offset:1926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1926*FLEN/8, x4, x1, x2)

inst_643:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6334ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3b9bf9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2681e8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee334ab; op2val:0x3fbb9bf9;
op3val:0x7f2681e8; valaddr_reg:x3; val_offset:1929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1929*FLEN/8, x4, x1, x2)

inst_644:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6334ab and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3b9bf9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2681e8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee334ab; op2val:0x3fbb9bf9;
op3val:0x7f2681e8; valaddr_reg:x3; val_offset:1932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1932*FLEN/8, x4, x1, x2)

inst_645:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6368b9 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5c69af and fs3 == 0 and fe3 == 0xfc and fm3 == 0x43cbe1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee368b9; op2val:0x3edc69af;
op3val:0x7e43cbe1; valaddr_reg:x3; val_offset:1935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1935*FLEN/8, x4, x1, x2)

inst_646:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6368b9 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5c69af and fs3 == 0 and fe3 == 0xfc and fm3 == 0x43cbe1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee368b9; op2val:0x3edc69af;
op3val:0x7e43cbe1; valaddr_reg:x3; val_offset:1938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1938*FLEN/8, x4, x1, x2)

inst_647:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6368b9 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5c69af and fs3 == 0 and fe3 == 0xfc and fm3 == 0x43cbe1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee368b9; op2val:0x3edc69af;
op3val:0x7e43cbe1; valaddr_reg:x3; val_offset:1941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1941*FLEN/8, x4, x1, x2)

inst_648:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6368b9 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5c69af and fs3 == 0 and fe3 == 0xfc and fm3 == 0x43cbe1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee368b9; op2val:0x3edc69af;
op3val:0x7e43cbe1; valaddr_reg:x3; val_offset:1944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1944*FLEN/8, x4, x1, x2)

inst_649:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6368b9 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5c69af and fs3 == 0 and fe3 == 0xfc and fm3 == 0x43cbe1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee368b9; op2val:0x3edc69af;
op3val:0x7e43cbe1; valaddr_reg:x3; val_offset:1947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1947*FLEN/8, x4, x1, x2)

inst_650:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x639870 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4c99bd and fs3 == 0 and fe3 == 0xfd and fm3 == 0x35e627 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee39870; op2val:0x3f4c99bd;
op3val:0x7eb5e627; valaddr_reg:x3; val_offset:1950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)

inst_651:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x639870 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4c99bd and fs3 == 0 and fe3 == 0xfd and fm3 == 0x35e627 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee39870; op2val:0x3f4c99bd;
op3val:0x7eb5e627; valaddr_reg:x3; val_offset:1953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1953*FLEN/8, x4, x1, x2)

inst_652:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x639870 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4c99bd and fs3 == 0 and fe3 == 0xfd and fm3 == 0x35e627 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee39870; op2val:0x3f4c99bd;
op3val:0x7eb5e627; valaddr_reg:x3; val_offset:1956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1956*FLEN/8, x4, x1, x2)

inst_653:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x639870 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4c99bd and fs3 == 0 and fe3 == 0xfd and fm3 == 0x35e627 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee39870; op2val:0x3f4c99bd;
op3val:0x7eb5e627; valaddr_reg:x3; val_offset:1959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1959*FLEN/8, x4, x1, x2)

inst_654:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x639870 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4c99bd and fs3 == 0 and fe3 == 0xfd and fm3 == 0x35e627 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee39870; op2val:0x3f4c99bd;
op3val:0x7eb5e627; valaddr_reg:x3; val_offset:1962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1962*FLEN/8, x4, x1, x2)

inst_655:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:1965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1965*FLEN/8, x4, x1, x2)

inst_656:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:1968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1968*FLEN/8, x4, x1, x2)

inst_657:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:1971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1971*FLEN/8, x4, x1, x2)

inst_658:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:1974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1974*FLEN/8, x4, x1, x2)

inst_659:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x671228 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0177d2 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x69b89c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee71228; op2val:0x3f0177d2;
op3val:0x7e69b89c; valaddr_reg:x3; val_offset:1977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1977*FLEN/8, x4, x1, x2)

inst_660:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x679066 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x07e51c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x75d8c6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee79066; op2val:0x3f07e51c;
op3val:0x7e75d8c6; valaddr_reg:x3; val_offset:1980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)

inst_661:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x679066 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x07e51c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x75d8c6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee79066; op2val:0x3f07e51c;
op3val:0x7e75d8c6; valaddr_reg:x3; val_offset:1983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1983*FLEN/8, x4, x1, x2)

inst_662:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x679066 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x07e51c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x75d8c6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee79066; op2val:0x3f07e51c;
op3val:0x7e75d8c6; valaddr_reg:x3; val_offset:1986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 1986*FLEN/8, x4, x1, x2)

inst_663:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x679066 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x07e51c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x75d8c6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee79066; op2val:0x3f07e51c;
op3val:0x7e75d8c6; valaddr_reg:x3; val_offset:1989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 1989*FLEN/8, x4, x1, x2)

inst_664:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x679066 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x07e51c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x75d8c6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee79066; op2val:0x3f07e51c;
op3val:0x7e75d8c6; valaddr_reg:x3; val_offset:1992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 1992*FLEN/8, x4, x1, x2)

inst_665:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68ed41 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x738f77 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5d9bbd and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee8ed41; op2val:0x3e738f77;
op3val:0x7ddd9bbd; valaddr_reg:x3; val_offset:1995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 1995*FLEN/8, x4, x1, x2)

inst_666:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68ed41 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x738f77 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5d9bbd and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee8ed41; op2val:0x3e738f77;
op3val:0x7ddd9bbd; valaddr_reg:x3; val_offset:1998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 1998*FLEN/8, x4, x1, x2)

inst_667:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68ed41 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x738f77 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5d9bbd and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee8ed41; op2val:0x3e738f77;
op3val:0x7ddd9bbd; valaddr_reg:x3; val_offset:2001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2001*FLEN/8, x4, x1, x2)

inst_668:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68ed41 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x738f77 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5d9bbd and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee8ed41; op2val:0x3e738f77;
op3val:0x7ddd9bbd; valaddr_reg:x3; val_offset:2004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2004*FLEN/8, x4, x1, x2)

inst_669:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68ed41 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x738f77 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x5d9bbd and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee8ed41; op2val:0x3e738f77;
op3val:0x7ddd9bbd; valaddr_reg:x3; val_offset:2007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2007*FLEN/8, x4, x1, x2)

inst_670:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b8edc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x302841 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x221741 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb8edc; op2val:0x3f302841;
op3val:0x7ea21741; valaddr_reg:x3; val_offset:2010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)

inst_671:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b8edc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x302841 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x221741 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb8edc; op2val:0x3f302841;
op3val:0x7ea21741; valaddr_reg:x3; val_offset:2013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2013*FLEN/8, x4, x1, x2)

inst_672:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b8edc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x302841 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x221741 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb8edc; op2val:0x3f302841;
op3val:0x7ea21741; valaddr_reg:x3; val_offset:2016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2016*FLEN/8, x4, x1, x2)

inst_673:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b8edc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x302841 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x221741 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb8edc; op2val:0x3f302841;
op3val:0x7ea21741; valaddr_reg:x3; val_offset:2019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2019*FLEN/8, x4, x1, x2)

inst_674:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b8edc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x302841 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x221741 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb8edc; op2val:0x3f302841;
op3val:0x7ea21741; valaddr_reg:x3; val_offset:2022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2022*FLEN/8, x4, x1, x2)

inst_675:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:2025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2025*FLEN/8, x4, x1, x2)

inst_676:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:2028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2028*FLEN/8, x4, x1, x2)

inst_677:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:2031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2031*FLEN/8, x4, x1, x2)

inst_678:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:2034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2034*FLEN/8, x4, x1, x2)

inst_679:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e2e8d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7cb106 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x6b1a87 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee2e8d; op2val:0x3efcb106;
op3val:0x7e6b1a87; valaddr_reg:x3; val_offset:2037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2037*FLEN/8, x4, x1, x2)

inst_680:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f0a62 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1df75c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x138057 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef0a62; op2val:0x3f9df75c;
op3val:0x7f138057; valaddr_reg:x3; val_offset:2040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)

inst_681:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f0a62 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1df75c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x138057 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef0a62; op2val:0x3f9df75c;
op3val:0x7f138057; valaddr_reg:x3; val_offset:2043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2043*FLEN/8, x4, x1, x2)

inst_682:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f0a62 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1df75c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x138057 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef0a62; op2val:0x3f9df75c;
op3val:0x7f138057; valaddr_reg:x3; val_offset:2046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2046*FLEN/8, x4, x1, x2)

inst_683:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f0a62 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1df75c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x138057 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef0a62; op2val:0x3f9df75c;
op3val:0x7f138057; valaddr_reg:x3; val_offset:2049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2049*FLEN/8, x4, x1, x2)

inst_684:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6f0a62 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1df75c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x138057 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eef0a62; op2val:0x3f9df75c;
op3val:0x7f138057; valaddr_reg:x3; val_offset:2052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2052*FLEN/8, x4, x1, x2)

inst_685:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7127a3 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1eb06b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x157ca7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef127a3; op2val:0x3e1eb06b;
op3val:0x7d957ca7; valaddr_reg:x3; val_offset:2055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2055*FLEN/8, x4, x1, x2)

inst_686:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7127a3 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1eb06b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x157ca7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef127a3; op2val:0x3e1eb06b;
op3val:0x7d957ca7; valaddr_reg:x3; val_offset:2058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2058*FLEN/8, x4, x1, x2)

inst_687:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7127a3 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1eb06b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x157ca7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef127a3; op2val:0x3e1eb06b;
op3val:0x7d957ca7; valaddr_reg:x3; val_offset:2061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2061*FLEN/8, x4, x1, x2)

inst_688:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7127a3 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1eb06b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x157ca7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef127a3; op2val:0x3e1eb06b;
op3val:0x7d957ca7; valaddr_reg:x3; val_offset:2064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2064*FLEN/8, x4, x1, x2)

inst_689:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7127a3 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1eb06b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x157ca7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef127a3; op2val:0x3e1eb06b;
op3val:0x7d957ca7; valaddr_reg:x3; val_offset:2067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2067*FLEN/8, x4, x1, x2)

inst_690:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x717d9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ef083 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x250642 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef17d9d; op2val:0x3faef083;
op3val:0x7f250642; valaddr_reg:x3; val_offset:2070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)

inst_691:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x717d9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ef083 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x250642 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef17d9d; op2val:0x3faef083;
op3val:0x7f250642; valaddr_reg:x3; val_offset:2073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2073*FLEN/8, x4, x1, x2)

inst_692:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x717d9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ef083 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x250642 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef17d9d; op2val:0x3faef083;
op3val:0x7f250642; valaddr_reg:x3; val_offset:2076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2076*FLEN/8, x4, x1, x2)

inst_693:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x717d9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ef083 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x250642 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef17d9d; op2val:0x3faef083;
op3val:0x7f250642; valaddr_reg:x3; val_offset:2079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2079*FLEN/8, x4, x1, x2)

inst_694:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x717d9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ef083 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x250642 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef17d9d; op2val:0x3faef083;
op3val:0x7f250642; valaddr_reg:x3; val_offset:2082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2082*FLEN/8, x4, x1, x2)

inst_695:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x719c9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0eaeb4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06a9c2 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef19c9d; op2val:0x3f8eaeb4;
op3val:0x7f06a9c2; valaddr_reg:x3; val_offset:2085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2085*FLEN/8, x4, x1, x2)

inst_696:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x719c9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0eaeb4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06a9c2 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef19c9d; op2val:0x3f8eaeb4;
op3val:0x7f06a9c2; valaddr_reg:x3; val_offset:2088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2088*FLEN/8, x4, x1, x2)

inst_697:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x719c9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0eaeb4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06a9c2 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef19c9d; op2val:0x3f8eaeb4;
op3val:0x7f06a9c2; valaddr_reg:x3; val_offset:2091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2091*FLEN/8, x4, x1, x2)

inst_698:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x719c9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0eaeb4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06a9c2 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef19c9d; op2val:0x3f8eaeb4;
op3val:0x7f06a9c2; valaddr_reg:x3; val_offset:2094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2094*FLEN/8, x4, x1, x2)

inst_699:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x719c9d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0eaeb4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06a9c2 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef19c9d; op2val:0x3f8eaeb4;
op3val:0x7f06a9c2; valaddr_reg:x3; val_offset:2097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2097*FLEN/8, x4, x1, x2)

inst_700:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:2100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)

inst_701:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:2103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2103*FLEN/8, x4, x1, x2)

inst_702:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:2106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2106*FLEN/8, x4, x1, x2)

inst_703:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:2109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2109*FLEN/8, x4, x1, x2)

inst_704:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73cf0f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6acfa3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5fa103 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3cf0f; op2val:0x3eeacfa3;
op3val:0x7e5fa103; valaddr_reg:x3; val_offset:2112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2112*FLEN/8, x4, x1, x2)

inst_705:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x75363e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x56ade2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4da1e6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef5363e; op2val:0x3f56ade2;
op3val:0x7ecda1e6; valaddr_reg:x3; val_offset:2115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2115*FLEN/8, x4, x1, x2)

inst_706:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x75363e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x56ade2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4da1e6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef5363e; op2val:0x3f56ade2;
op3val:0x7ecda1e6; valaddr_reg:x3; val_offset:2118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2118*FLEN/8, x4, x1, x2)

inst_707:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x75363e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x56ade2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4da1e6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef5363e; op2val:0x3f56ade2;
op3val:0x7ecda1e6; valaddr_reg:x3; val_offset:2121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2121*FLEN/8, x4, x1, x2)

inst_708:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x75363e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x56ade2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4da1e6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef5363e; op2val:0x3f56ade2;
op3val:0x7ecda1e6; valaddr_reg:x3; val_offset:2124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2124*FLEN/8, x4, x1, x2)

inst_709:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x75363e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x56ade2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4da1e6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef5363e; op2val:0x3f56ade2;
op3val:0x7ecda1e6; valaddr_reg:x3; val_offset:2127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2127*FLEN/8, x4, x1, x2)

inst_710:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:2130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)

inst_711:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:2133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2133*FLEN/8, x4, x1, x2)

inst_712:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:2136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2136*FLEN/8, x4, x1, x2)

inst_713:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:2139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2139*FLEN/8, x4, x1, x2)

inst_714:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7783fc and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a9790 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x05ffb0 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef783fc; op2val:0x3f8a9790;
op3val:0x7f05ffb0; valaddr_reg:x3; val_offset:2142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2142*FLEN/8, x4, x1, x2)

inst_715:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7962d0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1d3c53 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x192c5e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef962d0; op2val:0x3f9d3c53;
op3val:0x7f192c5e; valaddr_reg:x3; val_offset:2145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2145*FLEN/8, x4, x1, x2)

inst_716:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7962d0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1d3c53 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x192c5e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef962d0; op2val:0x3f9d3c53;
op3val:0x7f192c5e; valaddr_reg:x3; val_offset:2148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2148*FLEN/8, x4, x1, x2)

inst_717:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7962d0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1d3c53 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x192c5e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef962d0; op2val:0x3f9d3c53;
op3val:0x7f192c5e; valaddr_reg:x3; val_offset:2151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2151*FLEN/8, x4, x1, x2)

inst_718:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7962d0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1d3c53 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x192c5e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef962d0; op2val:0x3f9d3c53;
op3val:0x7f192c5e; valaddr_reg:x3; val_offset:2154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2154*FLEN/8, x4, x1, x2)

inst_719:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7962d0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1d3c53 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x192c5e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef962d0; op2val:0x3f9d3c53;
op3val:0x7f192c5e; valaddr_reg:x3; val_offset:2157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2157*FLEN/8, x4, x1, x2)

inst_720:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79f86d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x61c0e4 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5c6fb2 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9f86d; op2val:0x3ee1c0e4;
op3val:0x7e5c6fb2; valaddr_reg:x3; val_offset:2160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)

inst_721:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79f86d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x61c0e4 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5c6fb2 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9f86d; op2val:0x3ee1c0e4;
op3val:0x7e5c6fb2; valaddr_reg:x3; val_offset:2163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2163*FLEN/8, x4, x1, x2)

inst_722:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79f86d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x61c0e4 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5c6fb2 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9f86d; op2val:0x3ee1c0e4;
op3val:0x7e5c6fb2; valaddr_reg:x3; val_offset:2166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2166*FLEN/8, x4, x1, x2)

inst_723:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79f86d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x61c0e4 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5c6fb2 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9f86d; op2val:0x3ee1c0e4;
op3val:0x7e5c6fb2; valaddr_reg:x3; val_offset:2169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2169*FLEN/8, x4, x1, x2)

inst_724:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79f86d and fs2 == 0 and fe2 == 0x7d and fm2 == 0x61c0e4 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5c6fb2 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9f86d; op2val:0x3ee1c0e4;
op3val:0x7e5c6fb2; valaddr_reg:x3; val_offset:2172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2172*FLEN/8, x4, x1, x2)

inst_725:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7d263c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3c7c65 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a6317 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efd263c; op2val:0x3fbc7c65;
op3val:0x7f3a6317; valaddr_reg:x3; val_offset:2175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2175*FLEN/8, x4, x1, x2)

inst_726:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7d263c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3c7c65 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a6317 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efd263c; op2val:0x3fbc7c65;
op3val:0x7f3a6317; valaddr_reg:x3; val_offset:2178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2178*FLEN/8, x4, x1, x2)

inst_727:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7d263c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3c7c65 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a6317 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efd263c; op2val:0x3fbc7c65;
op3val:0x7f3a6317; valaddr_reg:x3; val_offset:2181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2181*FLEN/8, x4, x1, x2)

inst_728:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7d263c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3c7c65 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a6317 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efd263c; op2val:0x3fbc7c65;
op3val:0x7f3a6317; valaddr_reg:x3; val_offset:2184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2184*FLEN/8, x4, x1, x2)

inst_729:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7d263c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3c7c65 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a6317 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efd263c; op2val:0x3fbc7c65;
op3val:0x7f3a6317; valaddr_reg:x3; val_offset:2187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2187*FLEN/8, x4, x1, x2)

inst_730:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7f5201 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x4052f8 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x3fd041 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eff5201; op2val:0x3e4052f8;
op3val:0x7dbfd041; valaddr_reg:x3; val_offset:2190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)

inst_731:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7f5201 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x4052f8 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x3fd041 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eff5201; op2val:0x3e4052f8;
op3val:0x7dbfd041; valaddr_reg:x3; val_offset:2193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2193*FLEN/8, x4, x1, x2)

inst_732:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7f5201 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x4052f8 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x3fd041 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eff5201; op2val:0x3e4052f8;
op3val:0x7dbfd041; valaddr_reg:x3; val_offset:2196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2196*FLEN/8, x4, x1, x2)

inst_733:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7f5201 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x4052f8 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x3fd041 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eff5201; op2val:0x3e4052f8;
op3val:0x7dbfd041; valaddr_reg:x3; val_offset:2199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2199*FLEN/8, x4, x1, x2)

inst_734:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7f5201 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x4052f8 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x3fd041 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eff5201; op2val:0x3e4052f8;
op3val:0x7dbfd041; valaddr_reg:x3; val_offset:2202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2202*FLEN/8, x4, x1, x2)

inst_735:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ff572 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3ac415 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3abc62 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efff572; op2val:0x3fbac415;
op3val:0x7f3abc62; valaddr_reg:x3; val_offset:2205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2205*FLEN/8, x4, x1, x2)

inst_736:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ff572 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3ac415 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3abc62 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efff572; op2val:0x3fbac415;
op3val:0x7f3abc62; valaddr_reg:x3; val_offset:2208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2208*FLEN/8, x4, x1, x2)

inst_737:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ff572 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3ac415 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3abc62 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efff572; op2val:0x3fbac415;
op3val:0x7f3abc62; valaddr_reg:x3; val_offset:2211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2211*FLEN/8, x4, x1, x2)

inst_738:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ff572 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3ac415 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3abc62 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efff572; op2val:0x3fbac415;
op3val:0x7f3abc62; valaddr_reg:x3; val_offset:2214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2214*FLEN/8, x4, x1, x2)

inst_739:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ff572 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3ac415 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3abc62 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efff572; op2val:0x3fbac415;
op3val:0x7f3abc62; valaddr_reg:x3; val_offset:2217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2217*FLEN/8, x4, x1, x2)

inst_740:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:2220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2220*FLEN/8, x4, x1, x2)

inst_741:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:2223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2223*FLEN/8, x4, x1, x2)

inst_742:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:2226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2226*FLEN/8, x4, x1, x2)

inst_743:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:2229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2229*FLEN/8, x4, x1, x2)

inst_744:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x00ae82 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x29e1b5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2ac951 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f00ae82; op2val:0x3fa9e1b5;
op3val:0x7f2ac951; valaddr_reg:x3; val_offset:2232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2232*FLEN/8, x4, x1, x2)

inst_745:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01c7a5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a21b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0c0d70 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f01c7a5; op2val:0x3f8a21b9;
op3val:0x7f0c0d70; valaddr_reg:x3; val_offset:2235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2235*FLEN/8, x4, x1, x2)

inst_746:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01c7a5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a21b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0c0d70 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f01c7a5; op2val:0x3f8a21b9;
op3val:0x7f0c0d70; valaddr_reg:x3; val_offset:2238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2238*FLEN/8, x4, x1, x2)

inst_747:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01c7a5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a21b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0c0d70 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f01c7a5; op2val:0x3f8a21b9;
op3val:0x7f0c0d70; valaddr_reg:x3; val_offset:2241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2241*FLEN/8, x4, x1, x2)

inst_748:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01c7a5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a21b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0c0d70 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f01c7a5; op2val:0x3f8a21b9;
op3val:0x7f0c0d70; valaddr_reg:x3; val_offset:2244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2244*FLEN/8, x4, x1, x2)

inst_749:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01c7a5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0a21b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0c0d70 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f01c7a5; op2val:0x3f8a21b9;
op3val:0x7f0c0d70; valaddr_reg:x3; val_offset:2247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2247*FLEN/8, x4, x1, x2)

inst_750:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x024167 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x352b4f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x385c8f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f024167; op2val:0x3f352b4f;
op3val:0x7eb85c8f; valaddr_reg:x3; val_offset:2250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2250*FLEN/8, x4, x1, x2)

inst_751:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x024167 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x352b4f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x385c8f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f024167; op2val:0x3f352b4f;
op3val:0x7eb85c8f; valaddr_reg:x3; val_offset:2253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2253*FLEN/8, x4, x1, x2)

inst_752:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x024167 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x352b4f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x385c8f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f024167; op2val:0x3f352b4f;
op3val:0x7eb85c8f; valaddr_reg:x3; val_offset:2256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2256*FLEN/8, x4, x1, x2)

inst_753:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x024167 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x352b4f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x385c8f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f024167; op2val:0x3f352b4f;
op3val:0x7eb85c8f; valaddr_reg:x3; val_offset:2259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2259*FLEN/8, x4, x1, x2)

inst_754:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x024167 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x352b4f and fs3 == 0 and fe3 == 0xfd and fm3 == 0x385c8f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f024167; op2val:0x3f352b4f;
op3val:0x7eb85c8f; valaddr_reg:x3; val_offset:2262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2262*FLEN/8, x4, x1, x2)

inst_755:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x034e7c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x116e22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x152fe4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f034e7c; op2val:0x3f916e22;
op3val:0x7f152fe4; valaddr_reg:x3; val_offset:2265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2265*FLEN/8, x4, x1, x2)

inst_756:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x034e7c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x116e22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x152fe4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f034e7c; op2val:0x3f916e22;
op3val:0x7f152fe4; valaddr_reg:x3; val_offset:2268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2268*FLEN/8, x4, x1, x2)

inst_757:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x034e7c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x116e22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x152fe4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f034e7c; op2val:0x3f916e22;
op3val:0x7f152fe4; valaddr_reg:x3; val_offset:2271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2271*FLEN/8, x4, x1, x2)

inst_758:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x034e7c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x116e22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x152fe4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f034e7c; op2val:0x3f916e22;
op3val:0x7f152fe4; valaddr_reg:x3; val_offset:2274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2274*FLEN/8, x4, x1, x2)

inst_759:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x034e7c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x116e22 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x152fe4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f034e7c; op2val:0x3f916e22;
op3val:0x7f152fe4; valaddr_reg:x3; val_offset:2277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2277*FLEN/8, x4, x1, x2)

inst_760:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x040377 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1106a2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1592c4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f040377; op2val:0x3f9106a2;
op3val:0x7f1592c4; valaddr_reg:x3; val_offset:2280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2280*FLEN/8, x4, x1, x2)

inst_761:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x040377 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1106a2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1592c4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f040377; op2val:0x3f9106a2;
op3val:0x7f1592c4; valaddr_reg:x3; val_offset:2283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2283*FLEN/8, x4, x1, x2)

inst_762:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x040377 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1106a2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1592c4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f040377; op2val:0x3f9106a2;
op3val:0x7f1592c4; valaddr_reg:x3; val_offset:2286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2286*FLEN/8, x4, x1, x2)

inst_763:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x040377 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1106a2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1592c4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f040377; op2val:0x3f9106a2;
op3val:0x7f1592c4; valaddr_reg:x3; val_offset:2289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2289*FLEN/8, x4, x1, x2)

inst_764:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x040377 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1106a2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1592c4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f040377; op2val:0x3f9106a2;
op3val:0x7f1592c4; valaddr_reg:x3; val_offset:2292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2292*FLEN/8, x4, x1, x2)

inst_765:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0535ac and fs2 == 0 and fe2 == 0x7f and fm2 == 0x11fe69 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x17ef92 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0535ac; op2val:0x3f91fe69;
op3val:0x7f17ef92; valaddr_reg:x3; val_offset:2295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2295*FLEN/8, x4, x1, x2)

inst_766:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0535ac and fs2 == 0 and fe2 == 0x7f and fm2 == 0x11fe69 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x17ef92 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0535ac; op2val:0x3f91fe69;
op3val:0x7f17ef92; valaddr_reg:x3; val_offset:2298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2298*FLEN/8, x4, x1, x2)

inst_767:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0535ac and fs2 == 0 and fe2 == 0x7f and fm2 == 0x11fe69 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x17ef92 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0535ac; op2val:0x3f91fe69;
op3val:0x7f17ef92; valaddr_reg:x3; val_offset:2301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2301*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_7)

inst_768:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0535ac and fs2 == 0 and fe2 == 0x7f and fm2 == 0x11fe69 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x17ef92 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0535ac; op2val:0x3f91fe69;
op3val:0x7f17ef92; valaddr_reg:x3; val_offset:2304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2304*FLEN/8, x4, x1, x2)

inst_769:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0535ac and fs2 == 0 and fe2 == 0x7f and fm2 == 0x11fe69 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x17ef92 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0535ac; op2val:0x3f91fe69;
op3val:0x7f17ef92; valaddr_reg:x3; val_offset:2307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2307*FLEN/8, x4, x1, x2)

inst_770:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x054c46 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x15a306 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1bd48f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f054c46; op2val:0x3f95a306;
op3val:0x7f1bd48f; valaddr_reg:x3; val_offset:2310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2310*FLEN/8, x4, x1, x2)

inst_771:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x054c46 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x15a306 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1bd48f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f054c46; op2val:0x3f95a306;
op3val:0x7f1bd48f; valaddr_reg:x3; val_offset:2313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2313*FLEN/8, x4, x1, x2)

inst_772:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x054c46 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x15a306 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1bd48f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f054c46; op2val:0x3f95a306;
op3val:0x7f1bd48f; valaddr_reg:x3; val_offset:2316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2316*FLEN/8, x4, x1, x2)

inst_773:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x054c46 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x15a306 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1bd48f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f054c46; op2val:0x3f95a306;
op3val:0x7f1bd48f; valaddr_reg:x3; val_offset:2319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2319*FLEN/8, x4, x1, x2)

inst_774:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x054c46 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x15a306 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1bd48f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f054c46; op2val:0x3f95a306;
op3val:0x7f1bd48f; valaddr_reg:x3; val_offset:2322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2322*FLEN/8, x4, x1, x2)

inst_775:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:2325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2325*FLEN/8, x4, x1, x2)

inst_776:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:2328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2328*FLEN/8, x4, x1, x2)

inst_777:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:2331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2331*FLEN/8, x4, x1, x2)

inst_778:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:2334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2334*FLEN/8, x4, x1, x2)

inst_779:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x060f17 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x12ec96 and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x19e100 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f060f17; op2val:0x3c92ec96;
op3val:0x7c19e100; valaddr_reg:x3; val_offset:2337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2337*FLEN/8, x4, x1, x2)

inst_780:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x075c57 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x103fcc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x188b59 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f075c57; op2val:0x3f903fcc;
op3val:0x7f188b59; valaddr_reg:x3; val_offset:2340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2340*FLEN/8, x4, x1, x2)

inst_781:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x075c57 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x103fcc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x188b59 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f075c57; op2val:0x3f903fcc;
op3val:0x7f188b59; valaddr_reg:x3; val_offset:2343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2343*FLEN/8, x4, x1, x2)

inst_782:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x075c57 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x103fcc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x188b59 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f075c57; op2val:0x3f903fcc;
op3val:0x7f188b59; valaddr_reg:x3; val_offset:2346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2346*FLEN/8, x4, x1, x2)

inst_783:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x075c57 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x103fcc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x188b59 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f075c57; op2val:0x3f903fcc;
op3val:0x7f188b59; valaddr_reg:x3; val_offset:2349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2349*FLEN/8, x4, x1, x2)

inst_784:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x075c57 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x103fcc and fs3 == 0 and fe3 == 0xfe and fm3 == 0x188b59 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f075c57; op2val:0x3f903fcc;
op3val:0x7f188b59; valaddr_reg:x3; val_offset:2352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2352*FLEN/8, x4, x1, x2)

inst_785:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x098b22 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x668bbe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77bc2c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f098b22; op2val:0x3f668bbe;
op3val:0x7ef7bc2c; valaddr_reg:x3; val_offset:2355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2355*FLEN/8, x4, x1, x2)

inst_786:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x098b22 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x668bbe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77bc2c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f098b22; op2val:0x3f668bbe;
op3val:0x7ef7bc2c; valaddr_reg:x3; val_offset:2358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2358*FLEN/8, x4, x1, x2)

inst_787:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x098b22 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x668bbe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77bc2c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f098b22; op2val:0x3f668bbe;
op3val:0x7ef7bc2c; valaddr_reg:x3; val_offset:2361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2361*FLEN/8, x4, x1, x2)

inst_788:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x098b22 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x668bbe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77bc2c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f098b22; op2val:0x3f668bbe;
op3val:0x7ef7bc2c; valaddr_reg:x3; val_offset:2364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2364*FLEN/8, x4, x1, x2)

inst_789:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x098b22 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x668bbe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x77bc2c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f098b22; op2val:0x3f668bbe;
op3val:0x7ef7bc2c; valaddr_reg:x3; val_offset:2367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2367*FLEN/8, x4, x1, x2)

inst_790:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09ecac and fs2 == 0 and fe2 == 0x7b and fm2 == 0x026746 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0c83a7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09ecac; op2val:0x3d826746;
op3val:0x7d0c83a7; valaddr_reg:x3; val_offset:2370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2370*FLEN/8, x4, x1, x2)

inst_791:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09ecac and fs2 == 0 and fe2 == 0x7b and fm2 == 0x026746 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0c83a7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09ecac; op2val:0x3d826746;
op3val:0x7d0c83a7; valaddr_reg:x3; val_offset:2373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2373*FLEN/8, x4, x1, x2)

inst_792:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09ecac and fs2 == 0 and fe2 == 0x7b and fm2 == 0x026746 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0c83a7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09ecac; op2val:0x3d826746;
op3val:0x7d0c83a7; valaddr_reg:x3; val_offset:2376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2376*FLEN/8, x4, x1, x2)

inst_793:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09ecac and fs2 == 0 and fe2 == 0x7b and fm2 == 0x026746 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0c83a7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09ecac; op2val:0x3d826746;
op3val:0x7d0c83a7; valaddr_reg:x3; val_offset:2379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2379*FLEN/8, x4, x1, x2)

inst_794:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09ecac and fs2 == 0 and fe2 == 0x7b and fm2 == 0x026746 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x0c83a7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09ecac; op2val:0x3d826746;
op3val:0x7d0c83a7; valaddr_reg:x3; val_offset:2382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2382*FLEN/8, x4, x1, x2)

inst_795:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a2ca1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x5cb7f4 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6e4348 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0a2ca1; op2val:0x3e5cb7f4;
op3val:0x7dee4348; valaddr_reg:x3; val_offset:2385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2385*FLEN/8, x4, x1, x2)

inst_796:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a2ca1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x5cb7f4 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6e4348 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0a2ca1; op2val:0x3e5cb7f4;
op3val:0x7dee4348; valaddr_reg:x3; val_offset:2388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2388*FLEN/8, x4, x1, x2)

inst_797:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a2ca1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x5cb7f4 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6e4348 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0a2ca1; op2val:0x3e5cb7f4;
op3val:0x7dee4348; valaddr_reg:x3; val_offset:2391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2391*FLEN/8, x4, x1, x2)

inst_798:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a2ca1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x5cb7f4 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6e4348 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0a2ca1; op2val:0x3e5cb7f4;
op3val:0x7dee4348; valaddr_reg:x3; val_offset:2394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2394*FLEN/8, x4, x1, x2)

inst_799:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a2ca1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x5cb7f4 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6e4348 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0a2ca1; op2val:0x3e5cb7f4;
op3val:0x7dee4348; valaddr_reg:x3; val_offset:2397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2397*FLEN/8, x4, x1, x2)

inst_800:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b0956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x18c26e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25ee48 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0b0956; op2val:0x3f98c26e;
op3val:0x7f25ee48; valaddr_reg:x3; val_offset:2400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2400*FLEN/8, x4, x1, x2)

inst_801:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b0956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x18c26e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25ee48 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0b0956; op2val:0x3f98c26e;
op3val:0x7f25ee48; valaddr_reg:x3; val_offset:2403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2403*FLEN/8, x4, x1, x2)

inst_802:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b0956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x18c26e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25ee48 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0b0956; op2val:0x3f98c26e;
op3val:0x7f25ee48; valaddr_reg:x3; val_offset:2406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2406*FLEN/8, x4, x1, x2)

inst_803:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b0956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x18c26e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25ee48 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0b0956; op2val:0x3f98c26e;
op3val:0x7f25ee48; valaddr_reg:x3; val_offset:2409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2409*FLEN/8, x4, x1, x2)

inst_804:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b0956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x18c26e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25ee48 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0b0956; op2val:0x3f98c26e;
op3val:0x7f25ee48; valaddr_reg:x3; val_offset:2412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2412*FLEN/8, x4, x1, x2)

inst_805:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0bc4e1 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x213184 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3003b5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0bc4e1; op2val:0x3fa13184;
op3val:0x7f3003b5; valaddr_reg:x3; val_offset:2415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2415*FLEN/8, x4, x1, x2)

inst_806:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0bc4e1 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x213184 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3003b5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0bc4e1; op2val:0x3fa13184;
op3val:0x7f3003b5; valaddr_reg:x3; val_offset:2418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2418*FLEN/8, x4, x1, x2)

inst_807:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0bc4e1 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x213184 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3003b5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0bc4e1; op2val:0x3fa13184;
op3val:0x7f3003b5; valaddr_reg:x3; val_offset:2421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2421*FLEN/8, x4, x1, x2)

inst_808:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0bc4e1 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x213184 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3003b5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0bc4e1; op2val:0x3fa13184;
op3val:0x7f3003b5; valaddr_reg:x3; val_offset:2424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2424*FLEN/8, x4, x1, x2)

inst_809:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0bc4e1 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x213184 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3003b5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0bc4e1; op2val:0x3fa13184;
op3val:0x7f3003b5; valaddr_reg:x3; val_offset:2427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2427*FLEN/8, x4, x1, x2)

inst_810:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:2430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2430*FLEN/8, x4, x1, x2)

inst_811:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:2433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2433*FLEN/8, x4, x1, x2)

inst_812:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:2436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2436*FLEN/8, x4, x1, x2)

inst_813:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:2439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2439*FLEN/8, x4, x1, x2)

inst_814:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c2059 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x11387d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1efa7c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c2059; op2val:0x3f11387d;
op3val:0x7e9efa7c; valaddr_reg:x3; val_offset:2442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2442*FLEN/8, x4, x1, x2)

inst_815:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c73a9 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1fa10c and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2f2863 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c73a9; op2val:0x3e1fa10c;
op3val:0x7daf2863; valaddr_reg:x3; val_offset:2445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2445*FLEN/8, x4, x1, x2)

inst_816:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c73a9 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1fa10c and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2f2863 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c73a9; op2val:0x3e1fa10c;
op3val:0x7daf2863; valaddr_reg:x3; val_offset:2448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2448*FLEN/8, x4, x1, x2)

inst_817:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c73a9 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1fa10c and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2f2863 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c73a9; op2val:0x3e1fa10c;
op3val:0x7daf2863; valaddr_reg:x3; val_offset:2451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2451*FLEN/8, x4, x1, x2)

inst_818:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c73a9 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1fa10c and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2f2863 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c73a9; op2val:0x3e1fa10c;
op3val:0x7daf2863; valaddr_reg:x3; val_offset:2454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2454*FLEN/8, x4, x1, x2)

inst_819:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c73a9 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x1fa10c and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2f2863 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c73a9; op2val:0x3e1fa10c;
op3val:0x7daf2863; valaddr_reg:x3; val_offset:2457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2457*FLEN/8, x4, x1, x2)

inst_820:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0de12c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e961e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2fc857 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0de12c; op2val:0x3f1e961e;
op3val:0x7eafc857; valaddr_reg:x3; val_offset:2460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2460*FLEN/8, x4, x1, x2)

inst_821:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0de12c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e961e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2fc857 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0de12c; op2val:0x3f1e961e;
op3val:0x7eafc857; valaddr_reg:x3; val_offset:2463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2463*FLEN/8, x4, x1, x2)

inst_822:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0de12c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e961e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2fc857 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0de12c; op2val:0x3f1e961e;
op3val:0x7eafc857; valaddr_reg:x3; val_offset:2466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2466*FLEN/8, x4, x1, x2)

inst_823:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0de12c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e961e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2fc857 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0de12c; op2val:0x3f1e961e;
op3val:0x7eafc857; valaddr_reg:x3; val_offset:2469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2469*FLEN/8, x4, x1, x2)

inst_824:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0de12c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e961e and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2fc857 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0de12c; op2val:0x3f1e961e;
op3val:0x7eafc857; valaddr_reg:x3; val_offset:2472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2472*FLEN/8, x4, x1, x2)

inst_825:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:2475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2475*FLEN/8, x4, x1, x2)

inst_826:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:2478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2478*FLEN/8, x4, x1, x2)

inst_827:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:2481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2481*FLEN/8, x4, x1, x2)

inst_828:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:2484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2484*FLEN/8, x4, x1, x2)

inst_829:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f4ac6 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0870e2 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x18bdd1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f4ac6; op2val:0x3f0870e2;
op3val:0x7e98bdd1; valaddr_reg:x3; val_offset:2487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2487*FLEN/8, x4, x1, x2)

inst_830:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f54bf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x36502d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4c2647 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f54bf; op2val:0x3eb6502d;
op3val:0x7e4c2647; valaddr_reg:x3; val_offset:2490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2490*FLEN/8, x4, x1, x2)

inst_831:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f54bf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x36502d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4c2647 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f54bf; op2val:0x3eb6502d;
op3val:0x7e4c2647; valaddr_reg:x3; val_offset:2493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2493*FLEN/8, x4, x1, x2)

inst_832:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f54bf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x36502d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4c2647 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f54bf; op2val:0x3eb6502d;
op3val:0x7e4c2647; valaddr_reg:x3; val_offset:2496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2496*FLEN/8, x4, x1, x2)

inst_833:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f54bf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x36502d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4c2647 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f54bf; op2val:0x3eb6502d;
op3val:0x7e4c2647; valaddr_reg:x3; val_offset:2499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2499*FLEN/8, x4, x1, x2)

inst_834:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f54bf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x36502d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4c2647 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f54bf; op2val:0x3eb6502d;
op3val:0x7e4c2647; valaddr_reg:x3; val_offset:2502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2502*FLEN/8, x4, x1, x2)

inst_835:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:2505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2505*FLEN/8, x4, x1, x2)

inst_836:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:2508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2508*FLEN/8, x4, x1, x2)

inst_837:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:2511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2511*FLEN/8, x4, x1, x2)

inst_838:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:2514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2514*FLEN/8, x4, x1, x2)

inst_839:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x156314 and fs2 == 0 and fe2 == 0x79 and fm2 == 0x339b9f and fs3 == 0 and fe3 == 0xf8 and fm3 == 0x519e2f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f156314; op2val:0x3cb39b9f;
op3val:0x7c519e2f; valaddr_reg:x3; val_offset:2517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2517*FLEN/8, x4, x1, x2)

inst_840:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1578bb and fs2 == 0 and fe2 == 0x7e and fm2 == 0x130440 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2bad9e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1578bb; op2val:0x3f130440;
op3val:0x7eabad9e; valaddr_reg:x3; val_offset:2520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2520*FLEN/8, x4, x1, x2)

inst_841:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1578bb and fs2 == 0 and fe2 == 0x7e and fm2 == 0x130440 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2bad9e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1578bb; op2val:0x3f130440;
op3val:0x7eabad9e; valaddr_reg:x3; val_offset:2523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2523*FLEN/8, x4, x1, x2)

inst_842:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1578bb and fs2 == 0 and fe2 == 0x7e and fm2 == 0x130440 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2bad9e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1578bb; op2val:0x3f130440;
op3val:0x7eabad9e; valaddr_reg:x3; val_offset:2526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2526*FLEN/8, x4, x1, x2)

inst_843:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1578bb and fs2 == 0 and fe2 == 0x7e and fm2 == 0x130440 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2bad9e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1578bb; op2val:0x3f130440;
op3val:0x7eabad9e; valaddr_reg:x3; val_offset:2529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2529*FLEN/8, x4, x1, x2)

inst_844:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1578bb and fs2 == 0 and fe2 == 0x7e and fm2 == 0x130440 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2bad9e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1578bb; op2val:0x3f130440;
op3val:0x7eabad9e; valaddr_reg:x3; val_offset:2532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2532*FLEN/8, x4, x1, x2)

inst_845:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16332e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x051bd2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1c31d4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16332e; op2val:0x3f851bd2;
op3val:0x7f1c31d4; valaddr_reg:x3; val_offset:2535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2535*FLEN/8, x4, x1, x2)

inst_846:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16332e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x051bd2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1c31d4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16332e; op2val:0x3f851bd2;
op3val:0x7f1c31d4; valaddr_reg:x3; val_offset:2538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2538*FLEN/8, x4, x1, x2)

inst_847:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16332e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x051bd2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1c31d4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16332e; op2val:0x3f851bd2;
op3val:0x7f1c31d4; valaddr_reg:x3; val_offset:2541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2541*FLEN/8, x4, x1, x2)

inst_848:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16332e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x051bd2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1c31d4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16332e; op2val:0x3f851bd2;
op3val:0x7f1c31d4; valaddr_reg:x3; val_offset:2544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2544*FLEN/8, x4, x1, x2)

inst_849:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16332e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x051bd2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1c31d4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16332e; op2val:0x3f851bd2;
op3val:0x7f1c31d4; valaddr_reg:x3; val_offset:2547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2547*FLEN/8, x4, x1, x2)

inst_850:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fd83 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x12dd89 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2d3e7e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fd83; op2val:0x3e92dd89;
op3val:0x7e2d3e7e; valaddr_reg:x3; val_offset:2550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2550*FLEN/8, x4, x1, x2)

inst_851:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fd83 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x12dd89 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2d3e7e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fd83; op2val:0x3e92dd89;
op3val:0x7e2d3e7e; valaddr_reg:x3; val_offset:2553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2553*FLEN/8, x4, x1, x2)

inst_852:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fd83 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x12dd89 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2d3e7e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fd83; op2val:0x3e92dd89;
op3val:0x7e2d3e7e; valaddr_reg:x3; val_offset:2556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2556*FLEN/8, x4, x1, x2)

inst_853:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fd83 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x12dd89 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2d3e7e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fd83; op2val:0x3e92dd89;
op3val:0x7e2d3e7e; valaddr_reg:x3; val_offset:2559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2559*FLEN/8, x4, x1, x2)

inst_854:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fd83 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x12dd89 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2d3e7e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fd83; op2val:0x3e92dd89;
op3val:0x7e2d3e7e; valaddr_reg:x3; val_offset:2562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2562*FLEN/8, x4, x1, x2)

inst_855:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fe06 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x393272 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a76a7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fe06; op2val:0x3f393272;
op3val:0x7eda76a7; valaddr_reg:x3; val_offset:2565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2565*FLEN/8, x4, x1, x2)

inst_856:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fe06 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x393272 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a76a7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fe06; op2val:0x3f393272;
op3val:0x7eda76a7; valaddr_reg:x3; val_offset:2568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2568*FLEN/8, x4, x1, x2)

inst_857:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fe06 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x393272 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a76a7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fe06; op2val:0x3f393272;
op3val:0x7eda76a7; valaddr_reg:x3; val_offset:2571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2571*FLEN/8, x4, x1, x2)

inst_858:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fe06 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x393272 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a76a7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fe06; op2val:0x3f393272;
op3val:0x7eda76a7; valaddr_reg:x3; val_offset:2574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2574*FLEN/8, x4, x1, x2)

inst_859:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x16fe06 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x393272 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5a76a7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f16fe06; op2val:0x3f393272;
op3val:0x7eda76a7; valaddr_reg:x3; val_offset:2577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2577*FLEN/8, x4, x1, x2)

inst_860:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x173551 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0b1967 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2451e9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f173551; op2val:0x3e8b1967;
op3val:0x7e2451e9; valaddr_reg:x3; val_offset:2580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2580*FLEN/8, x4, x1, x2)

inst_861:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x173551 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0b1967 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2451e9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f173551; op2val:0x3e8b1967;
op3val:0x7e2451e9; valaddr_reg:x3; val_offset:2583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2583*FLEN/8, x4, x1, x2)

inst_862:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x173551 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0b1967 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2451e9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f173551; op2val:0x3e8b1967;
op3val:0x7e2451e9; valaddr_reg:x3; val_offset:2586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2586*FLEN/8, x4, x1, x2)

inst_863:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x173551 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0b1967 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2451e9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f173551; op2val:0x3e8b1967;
op3val:0x7e2451e9; valaddr_reg:x3; val_offset:2589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2589*FLEN/8, x4, x1, x2)

inst_864:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x173551 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x0b1967 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x2451e9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f173551; op2val:0x3e8b1967;
op3val:0x7e2451e9; valaddr_reg:x3; val_offset:2592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2592*FLEN/8, x4, x1, x2)

inst_865:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x17c861 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x712e6f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0eff2c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f17c861; op2val:0x3f712e6f;
op3val:0x7f0eff2c; valaddr_reg:x3; val_offset:2595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2595*FLEN/8, x4, x1, x2)

inst_866:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x17c861 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x712e6f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0eff2c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f17c861; op2val:0x3f712e6f;
op3val:0x7f0eff2c; valaddr_reg:x3; val_offset:2598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2598*FLEN/8, x4, x1, x2)

inst_867:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x17c861 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x712e6f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0eff2c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f17c861; op2val:0x3f712e6f;
op3val:0x7f0eff2c; valaddr_reg:x3; val_offset:2601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2601*FLEN/8, x4, x1, x2)

inst_868:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x17c861 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x712e6f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0eff2c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f17c861; op2val:0x3f712e6f;
op3val:0x7f0eff2c; valaddr_reg:x3; val_offset:2604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2604*FLEN/8, x4, x1, x2)

inst_869:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x17c861 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x712e6f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0eff2c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f17c861; op2val:0x3f712e6f;
op3val:0x7f0eff2c; valaddr_reg:x3; val_offset:2607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2607*FLEN/8, x4, x1, x2)

inst_870:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:2610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2610*FLEN/8, x4, x1, x2)

inst_871:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:2613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2613*FLEN/8, x4, x1, x2)

inst_872:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:2616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2616*FLEN/8, x4, x1, x2)

inst_873:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:2619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2619*FLEN/8, x4, x1, x2)

inst_874:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185240 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x049ddd and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1dd0ae and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185240; op2val:0x3f849ddd;
op3val:0x7f1dd0ae; valaddr_reg:x3; val_offset:2622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2622*FLEN/8, x4, x1, x2)

inst_875:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18571c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1718df and fs3 == 0 and fe3 == 0xfe and fm3 == 0x33d45e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18571c; op2val:0x3f9718df;
op3val:0x7f33d45e; valaddr_reg:x3; val_offset:2625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2625*FLEN/8, x4, x1, x2)

inst_876:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18571c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1718df and fs3 == 0 and fe3 == 0xfe and fm3 == 0x33d45e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18571c; op2val:0x3f9718df;
op3val:0x7f33d45e; valaddr_reg:x3; val_offset:2628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2628*FLEN/8, x4, x1, x2)

inst_877:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18571c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1718df and fs3 == 0 and fe3 == 0xfe and fm3 == 0x33d45e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18571c; op2val:0x3f9718df;
op3val:0x7f33d45e; valaddr_reg:x3; val_offset:2631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2631*FLEN/8, x4, x1, x2)

inst_878:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18571c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1718df and fs3 == 0 and fe3 == 0xfe and fm3 == 0x33d45e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18571c; op2val:0x3f9718df;
op3val:0x7f33d45e; valaddr_reg:x3; val_offset:2634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2634*FLEN/8, x4, x1, x2)

inst_879:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18571c and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1718df and fs3 == 0 and fe3 == 0xfe and fm3 == 0x33d45e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18571c; op2val:0x3f9718df;
op3val:0x7f33d45e; valaddr_reg:x3; val_offset:2637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2637*FLEN/8, x4, x1, x2)

inst_880:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:2640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2640*FLEN/8, x4, x1, x2)

inst_881:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:2643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2643*FLEN/8, x4, x1, x2)

inst_882:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:2646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2646*FLEN/8, x4, x1, x2)

inst_883:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:2649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2649*FLEN/8, x4, x1, x2)

inst_884:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18d9d9 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x262663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x46685d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18d9d9; op2val:0x3f262663;
op3val:0x7ec6685d; valaddr_reg:x3; val_offset:2652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2652*FLEN/8, x4, x1, x2)

inst_885:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:2655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2655*FLEN/8, x4, x1, x2)

inst_886:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:2658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2658*FLEN/8, x4, x1, x2)

inst_887:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:2661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2661*FLEN/8, x4, x1, x2)

inst_888:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:2664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2664*FLEN/8, x4, x1, x2)

inst_889:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a3f02 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a8069 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x03a707 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a3f02; op2val:0x3f5a8069;
op3val:0x7f03a707; valaddr_reg:x3; val_offset:2667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2667*FLEN/8, x4, x1, x2)

inst_890:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a82a0 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4dc01c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x785d1b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a82a0; op2val:0x3ecdc01c;
op3val:0x7e785d1b; valaddr_reg:x3; val_offset:2670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2670*FLEN/8, x4, x1, x2)

inst_891:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a82a0 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4dc01c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x785d1b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a82a0; op2val:0x3ecdc01c;
op3val:0x7e785d1b; valaddr_reg:x3; val_offset:2673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2673*FLEN/8, x4, x1, x2)

inst_892:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a82a0 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4dc01c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x785d1b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a82a0; op2val:0x3ecdc01c;
op3val:0x7e785d1b; valaddr_reg:x3; val_offset:2676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2676*FLEN/8, x4, x1, x2)

inst_893:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a82a0 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4dc01c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x785d1b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a82a0; op2val:0x3ecdc01c;
op3val:0x7e785d1b; valaddr_reg:x3; val_offset:2679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2679*FLEN/8, x4, x1, x2)

inst_894:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a82a0 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4dc01c and fs3 == 0 and fe3 == 0xfc and fm3 == 0x785d1b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a82a0; op2val:0x3ecdc01c;
op3val:0x7e785d1b; valaddr_reg:x3; val_offset:2682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2682*FLEN/8, x4, x1, x2)

inst_895:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:2685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2685*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_8)

inst_896:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:2688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2688*FLEN/8, x4, x1, x2)

inst_897:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:2691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2691*FLEN/8, x4, x1, x2)

inst_898:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:2694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2694*FLEN/8, x4, x1, x2)

inst_899:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a849e and fs2 == 0 and fe2 == 0x7e and fm2 == 0x0d9f1b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2af628 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a849e; op2val:0x3f0d9f1b;
op3val:0x7eaaf628; valaddr_reg:x3; val_offset:2697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2697*FLEN/8, x4, x1, x2)

inst_900:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:2700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2700*FLEN/8, x4, x1, x2)

inst_901:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:2703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2703*FLEN/8, x4, x1, x2)

inst_902:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:2706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2706*FLEN/8, x4, x1, x2)

inst_903:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:2709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2709*FLEN/8, x4, x1, x2)

inst_904:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9574 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x28da1a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4beb8f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9574; op2val:0x3ea8da1a;
op3val:0x7e4beb8f; valaddr_reg:x3; val_offset:2712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2712*FLEN/8, x4, x1, x2)

inst_905:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9c08 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6caafe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0eef1c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9c08; op2val:0x3eecaafe;
op3val:0x7e8eef1c; valaddr_reg:x3; val_offset:2715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2715*FLEN/8, x4, x1, x2)

inst_906:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9c08 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6caafe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0eef1c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9c08; op2val:0x3eecaafe;
op3val:0x7e8eef1c; valaddr_reg:x3; val_offset:2718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2718*FLEN/8, x4, x1, x2)

inst_907:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9c08 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6caafe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0eef1c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9c08; op2val:0x3eecaafe;
op3val:0x7e8eef1c; valaddr_reg:x3; val_offset:2721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2721*FLEN/8, x4, x1, x2)

inst_908:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9c08 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6caafe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0eef1c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9c08; op2val:0x3eecaafe;
op3val:0x7e8eef1c; valaddr_reg:x3; val_offset:2724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2724*FLEN/8, x4, x1, x2)

inst_909:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a9c08 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6caafe and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0eef1c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a9c08; op2val:0x3eecaafe;
op3val:0x7e8eef1c; valaddr_reg:x3; val_offset:2727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2727*FLEN/8, x4, x1, x2)

inst_910:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:2730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2730*FLEN/8, x4, x1, x2)

inst_911:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:2733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2733*FLEN/8, x4, x1, x2)

inst_912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:2736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2736*FLEN/8, x4, x1, x2)

inst_913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:2739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2739*FLEN/8, x4, x1, x2)

inst_914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1aa82d and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b2701 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3b76c8 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1aa82d; op2val:0x3f9b2701;
op3val:0x7f3b76c8; valaddr_reg:x3; val_offset:2742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2742*FLEN/8, x4, x1, x2)

inst_915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b3506 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x366e13 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5d34de and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b3506; op2val:0x3f366e13;
op3val:0x7edd34de; valaddr_reg:x3; val_offset:2745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2745*FLEN/8, x4, x1, x2)

inst_916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b3506 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x366e13 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5d34de and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b3506; op2val:0x3f366e13;
op3val:0x7edd34de; valaddr_reg:x3; val_offset:2748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2748*FLEN/8, x4, x1, x2)

inst_917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b3506 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x366e13 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5d34de and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b3506; op2val:0x3f366e13;
op3val:0x7edd34de; valaddr_reg:x3; val_offset:2751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2751*FLEN/8, x4, x1, x2)

inst_918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b3506 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x366e13 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5d34de and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b3506; op2val:0x3f366e13;
op3val:0x7edd34de; valaddr_reg:x3; val_offset:2754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2754*FLEN/8, x4, x1, x2)

inst_919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b3506 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x366e13 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5d34de and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b3506; op2val:0x3f366e13;
op3val:0x7edd34de; valaddr_reg:x3; val_offset:2757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2757*FLEN/8, x4, x1, x2)

inst_920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f0a23 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x586415 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x066eba and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1f0a23; op2val:0x3dd86415;
op3val:0x7d866eba; valaddr_reg:x3; val_offset:2760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2760*FLEN/8, x4, x1, x2)

inst_921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f0a23 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x586415 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x066eba and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1f0a23; op2val:0x3dd86415;
op3val:0x7d866eba; valaddr_reg:x3; val_offset:2763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2763*FLEN/8, x4, x1, x2)

inst_922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f0a23 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x586415 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x066eba and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1f0a23; op2val:0x3dd86415;
op3val:0x7d866eba; valaddr_reg:x3; val_offset:2766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2766*FLEN/8, x4, x1, x2)

inst_923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f0a23 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x586415 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x066eba and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1f0a23; op2val:0x3dd86415;
op3val:0x7d866eba; valaddr_reg:x3; val_offset:2769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2769*FLEN/8, x4, x1, x2)

inst_924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f0a23 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x586415 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x066eba and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1f0a23; op2val:0x3dd86415;
op3val:0x7d866eba; valaddr_reg:x3; val_offset:2772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2772*FLEN/8, x4, x1, x2)

inst_925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1fd54d and fs2 == 0 and fe2 == 0x7a and fm2 == 0x7ea0e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1efa19 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1fd54d; op2val:0x3d7ea0e8;
op3val:0x7d1efa19; valaddr_reg:x3; val_offset:2775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2775*FLEN/8, x4, x1, x2)

inst_926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1fd54d and fs2 == 0 and fe2 == 0x7a and fm2 == 0x7ea0e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1efa19 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1fd54d; op2val:0x3d7ea0e8;
op3val:0x7d1efa19; valaddr_reg:x3; val_offset:2778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2778*FLEN/8, x4, x1, x2)

inst_927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1fd54d and fs2 == 0 and fe2 == 0x7a and fm2 == 0x7ea0e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1efa19 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1fd54d; op2val:0x3d7ea0e8;
op3val:0x7d1efa19; valaddr_reg:x3; val_offset:2781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2781*FLEN/8, x4, x1, x2)

inst_928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1fd54d and fs2 == 0 and fe2 == 0x7a and fm2 == 0x7ea0e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1efa19 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1fd54d; op2val:0x3d7ea0e8;
op3val:0x7d1efa19; valaddr_reg:x3; val_offset:2784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2784*FLEN/8, x4, x1, x2)

inst_929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1fd54d and fs2 == 0 and fe2 == 0x7a and fm2 == 0x7ea0e8 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x1efa19 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1fd54d; op2val:0x3d7ea0e8;
op3val:0x7d1efa19; valaddr_reg:x3; val_offset:2787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2787*FLEN/8, x4, x1, x2)

inst_930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20e7b1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x7dd916 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x1f8d6c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20e7b1; op2val:0x3dfdd916;
op3val:0x7d9f8d6c; valaddr_reg:x3; val_offset:2790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2790*FLEN/8, x4, x1, x2)

inst_931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20e7b1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x7dd916 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x1f8d6c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20e7b1; op2val:0x3dfdd916;
op3val:0x7d9f8d6c; valaddr_reg:x3; val_offset:2793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2793*FLEN/8, x4, x1, x2)

inst_932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20e7b1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x7dd916 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x1f8d6c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20e7b1; op2val:0x3dfdd916;
op3val:0x7d9f8d6c; valaddr_reg:x3; val_offset:2796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2796*FLEN/8, x4, x1, x2)

inst_933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20e7b1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x7dd916 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x1f8d6c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20e7b1; op2val:0x3dfdd916;
op3val:0x7d9f8d6c; valaddr_reg:x3; val_offset:2799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2799*FLEN/8, x4, x1, x2)

inst_934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20e7b1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x7dd916 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x1f8d6c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20e7b1; op2val:0x3dfdd916;
op3val:0x7d9f8d6c; valaddr_reg:x3; val_offset:2802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2802*FLEN/8, x4, x1, x2)

inst_935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:2805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2805*FLEN/8, x4, x1, x2)

inst_936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:2808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2808*FLEN/8, x4, x1, x2)

inst_937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:2811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2811*FLEN/8, x4, x1, x2)

inst_938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:2814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2814*FLEN/8, x4, x1, x2)

inst_939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x221a29 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4b81fb and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00dd0d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f221a29; op2val:0x3ecb81fb;
op3val:0x7e80dd0d; valaddr_reg:x3; val_offset:2817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2817*FLEN/8, x4, x1, x2)

inst_940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ded1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x156e92 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3f4eee and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ded1; op2val:0x3d956e92;
op3val:0x7d3f4eee; valaddr_reg:x3; val_offset:2820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2820*FLEN/8, x4, x1, x2)

inst_941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ded1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x156e92 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3f4eee and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ded1; op2val:0x3d956e92;
op3val:0x7d3f4eee; valaddr_reg:x3; val_offset:2823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2823*FLEN/8, x4, x1, x2)

inst_942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ded1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x156e92 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3f4eee and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ded1; op2val:0x3d956e92;
op3val:0x7d3f4eee; valaddr_reg:x3; val_offset:2826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2826*FLEN/8, x4, x1, x2)

inst_943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ded1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x156e92 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3f4eee and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ded1; op2val:0x3d956e92;
op3val:0x7d3f4eee; valaddr_reg:x3; val_offset:2829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2829*FLEN/8, x4, x1, x2)

inst_944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23ded1 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x156e92 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x3f4eee and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23ded1; op2val:0x3d956e92;
op3val:0x7d3f4eee; valaddr_reg:x3; val_offset:2832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2832*FLEN/8, x4, x1, x2)

inst_945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2428ca and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4a4396 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x01b386 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2428ca; op2val:0x3eca4396;
op3val:0x7e81b386; valaddr_reg:x3; val_offset:2835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2835*FLEN/8, x4, x1, x2)

inst_946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2428ca and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4a4396 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x01b386 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2428ca; op2val:0x3eca4396;
op3val:0x7e81b386; valaddr_reg:x3; val_offset:2838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2838*FLEN/8, x4, x1, x2)

inst_947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2428ca and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4a4396 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x01b386 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2428ca; op2val:0x3eca4396;
op3val:0x7e81b386; valaddr_reg:x3; val_offset:2841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2841*FLEN/8, x4, x1, x2)

inst_948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2428ca and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4a4396 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x01b386 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2428ca; op2val:0x3eca4396;
op3val:0x7e81b386; valaddr_reg:x3; val_offset:2844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2844*FLEN/8, x4, x1, x2)

inst_949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2428ca and fs2 == 0 and fe2 == 0x7d and fm2 == 0x4a4396 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x01b386 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2428ca; op2val:0x3eca4396;
op3val:0x7e81b386; valaddr_reg:x3; val_offset:2847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2847*FLEN/8, x4, x1, x2)

inst_950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24c049 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x26f4cf and fs3 == 0 and fe3 == 0xfc and fm3 == 0x56e479 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24c049; op2val:0x3ea6f4cf;
op3val:0x7e56e479; valaddr_reg:x3; val_offset:2850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2850*FLEN/8, x4, x1, x2)

inst_951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24c049 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x26f4cf and fs3 == 0 and fe3 == 0xfc and fm3 == 0x56e479 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24c049; op2val:0x3ea6f4cf;
op3val:0x7e56e479; valaddr_reg:x3; val_offset:2853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2853*FLEN/8, x4, x1, x2)

inst_952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24c049 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x26f4cf and fs3 == 0 and fe3 == 0xfc and fm3 == 0x56e479 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24c049; op2val:0x3ea6f4cf;
op3val:0x7e56e479; valaddr_reg:x3; val_offset:2856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2856*FLEN/8, x4, x1, x2)

inst_953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24c049 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x26f4cf and fs3 == 0 and fe3 == 0xfc and fm3 == 0x56e479 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24c049; op2val:0x3ea6f4cf;
op3val:0x7e56e479; valaddr_reg:x3; val_offset:2859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2859*FLEN/8, x4, x1, x2)

inst_954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24c049 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x26f4cf and fs3 == 0 and fe3 == 0xfc and fm3 == 0x56e479 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24c049; op2val:0x3ea6f4cf;
op3val:0x7e56e479; valaddr_reg:x3; val_offset:2862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2862*FLEN/8, x4, x1, x2)

inst_955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24fad5 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x680772 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x15881d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24fad5; op2val:0x3f680772;
op3val:0x7f15881d; valaddr_reg:x3; val_offset:2865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2865*FLEN/8, x4, x1, x2)

inst_956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24fad5 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x680772 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x15881d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24fad5; op2val:0x3f680772;
op3val:0x7f15881d; valaddr_reg:x3; val_offset:2868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2868*FLEN/8, x4, x1, x2)

inst_957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24fad5 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x680772 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x15881d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24fad5; op2val:0x3f680772;
op3val:0x7f15881d; valaddr_reg:x3; val_offset:2871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2871*FLEN/8, x4, x1, x2)

inst_958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24fad5 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x680772 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x15881d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24fad5; op2val:0x3f680772;
op3val:0x7f15881d; valaddr_reg:x3; val_offset:2874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2874*FLEN/8, x4, x1, x2)

inst_959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x24fad5 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x680772 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x15881d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f24fad5; op2val:0x3f680772;
op3val:0x7f15881d; valaddr_reg:x3; val_offset:2877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2877*FLEN/8, x4, x1, x2)

inst_960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x257510 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1daeab and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4bd35e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f257510; op2val:0x3f1daeab;
op3val:0x7ecbd35e; valaddr_reg:x3; val_offset:2880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2880*FLEN/8, x4, x1, x2)

inst_961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x257510 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1daeab and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4bd35e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f257510; op2val:0x3f1daeab;
op3val:0x7ecbd35e; valaddr_reg:x3; val_offset:2883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2883*FLEN/8, x4, x1, x2)

inst_962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x257510 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1daeab and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4bd35e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f257510; op2val:0x3f1daeab;
op3val:0x7ecbd35e; valaddr_reg:x3; val_offset:2886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2886*FLEN/8, x4, x1, x2)

inst_963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x257510 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1daeab and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4bd35e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f257510; op2val:0x3f1daeab;
op3val:0x7ecbd35e; valaddr_reg:x3; val_offset:2889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2889*FLEN/8, x4, x1, x2)

inst_964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x257510 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1daeab and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4bd35e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f257510; op2val:0x3f1daeab;
op3val:0x7ecbd35e; valaddr_reg:x3; val_offset:2892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2892*FLEN/8, x4, x1, x2)

inst_965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28d30c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x323b1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6b1376 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28d30c; op2val:0x3f323b1d;
op3val:0x7eeb1376; valaddr_reg:x3; val_offset:2895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2895*FLEN/8, x4, x1, x2)

inst_966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28d30c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x323b1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6b1376 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28d30c; op2val:0x3f323b1d;
op3val:0x7eeb1376; valaddr_reg:x3; val_offset:2898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2898*FLEN/8, x4, x1, x2)

inst_967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28d30c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x323b1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6b1376 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28d30c; op2val:0x3f323b1d;
op3val:0x7eeb1376; valaddr_reg:x3; val_offset:2901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2901*FLEN/8, x4, x1, x2)

inst_968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28d30c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x323b1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6b1376 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28d30c; op2val:0x3f323b1d;
op3val:0x7eeb1376; valaddr_reg:x3; val_offset:2904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2904*FLEN/8, x4, x1, x2)

inst_969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28d30c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x323b1d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6b1376 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28d30c; op2val:0x3f323b1d;
op3val:0x7eeb1376; valaddr_reg:x3; val_offset:2907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2907*FLEN/8, x4, x1, x2)

inst_970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:2910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2910*FLEN/8, x4, x1, x2)

inst_971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:2913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2913*FLEN/8, x4, x1, x2)

inst_972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:2916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2916*FLEN/8, x4, x1, x2)

inst_973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:2919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2919*FLEN/8, x4, x1, x2)

inst_974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x28f9a2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x18ca47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x49b378 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f28f9a2; op2val:0x3f18ca47;
op3val:0x7ec9b378; valaddr_reg:x3; val_offset:2922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2922*FLEN/8, x4, x1, x2)

inst_975:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2b8337 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x018782 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2d8fd1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2b8337; op2val:0x3f018782;
op3val:0x7ead8fd1; valaddr_reg:x3; val_offset:2925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2925*FLEN/8, x4, x1, x2)

inst_976:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2b8337 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x018782 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2d8fd1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2b8337; op2val:0x3f018782;
op3val:0x7ead8fd1; valaddr_reg:x3; val_offset:2928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2928*FLEN/8, x4, x1, x2)

inst_977:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2b8337 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x018782 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2d8fd1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2b8337; op2val:0x3f018782;
op3val:0x7ead8fd1; valaddr_reg:x3; val_offset:2931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2931*FLEN/8, x4, x1, x2)

inst_978:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2b8337 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x018782 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2d8fd1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2b8337; op2val:0x3f018782;
op3val:0x7ead8fd1; valaddr_reg:x3; val_offset:2934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2934*FLEN/8, x4, x1, x2)

inst_979:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2b8337 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x018782 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2d8fd1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2b8337; op2val:0x3f018782;
op3val:0x7ead8fd1; valaddr_reg:x3; val_offset:2937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2937*FLEN/8, x4, x1, x2)

inst_980:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2cacd1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x2fbe41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6d14ee and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2cacd1; op2val:0x3e2fbe41;
op3val:0x7ded14ee; valaddr_reg:x3; val_offset:2940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2940*FLEN/8, x4, x1, x2)

inst_981:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2cacd1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x2fbe41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6d14ee and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2cacd1; op2val:0x3e2fbe41;
op3val:0x7ded14ee; valaddr_reg:x3; val_offset:2943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2943*FLEN/8, x4, x1, x2)

inst_982:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2cacd1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x2fbe41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6d14ee and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2cacd1; op2val:0x3e2fbe41;
op3val:0x7ded14ee; valaddr_reg:x3; val_offset:2946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2946*FLEN/8, x4, x1, x2)

inst_983:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2cacd1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x2fbe41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6d14ee and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2cacd1; op2val:0x3e2fbe41;
op3val:0x7ded14ee; valaddr_reg:x3; val_offset:2949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2949*FLEN/8, x4, x1, x2)

inst_984:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2cacd1 and fs2 == 0 and fe2 == 0x7c and fm2 == 0x2fbe41 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x6d14ee and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2cacd1; op2val:0x3e2fbe41;
op3val:0x7ded14ee; valaddr_reg:x3; val_offset:2952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2952*FLEN/8, x4, x1, x2)

inst_985:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2e7c12 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7864d3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x294ceb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2e7c12; op2val:0x3ef864d3;
op3val:0x7ea94ceb; valaddr_reg:x3; val_offset:2955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2955*FLEN/8, x4, x1, x2)

inst_986:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2e7c12 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7864d3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x294ceb and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2e7c12; op2val:0x3ef864d3;
op3val:0x7ea94ceb; valaddr_reg:x3; val_offset:2958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2958*FLEN/8, x4, x1, x2)

inst_987:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2e7c12 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7864d3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x294ceb and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2e7c12; op2val:0x3ef864d3;
op3val:0x7ea94ceb; valaddr_reg:x3; val_offset:2961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2961*FLEN/8, x4, x1, x2)

inst_988:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2e7c12 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7864d3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x294ceb and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2e7c12; op2val:0x3ef864d3;
op3val:0x7ea94ceb; valaddr_reg:x3; val_offset:2964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2964*FLEN/8, x4, x1, x2)

inst_989:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2e7c12 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x7864d3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x294ceb and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2e7c12; op2val:0x3ef864d3;
op3val:0x7ea94ceb; valaddr_reg:x3; val_offset:2967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2967*FLEN/8, x4, x1, x2)

inst_990:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:2970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2970*FLEN/8, x4, x1, x2)

inst_991:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:2973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2973*FLEN/8, x4, x1, x2)

inst_992:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:2976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2976*FLEN/8, x4, x1, x2)

inst_993:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:2979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2979*FLEN/8, x4, x1, x2)

inst_994:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ea04a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x10dbda and fs3 == 0 and fe3 == 0xfd and fm3 == 0x45a044 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ea04a; op2val:0x3f10dbda;
op3val:0x7ec5a044; valaddr_reg:x3; val_offset:2982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2982*FLEN/8, x4, x1, x2)

inst_995:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eccce and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6b5891 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20b27b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eccce; op2val:0x3f6b5891;
op3val:0x7f20b27b; valaddr_reg:x3; val_offset:2985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 2985*FLEN/8, x4, x1, x2)

inst_996:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eccce and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6b5891 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20b27b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eccce; op2val:0x3f6b5891;
op3val:0x7f20b27b; valaddr_reg:x3; val_offset:2988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 2988*FLEN/8, x4, x1, x2)

inst_997:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eccce and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6b5891 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20b27b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eccce; op2val:0x3f6b5891;
op3val:0x7f20b27b; valaddr_reg:x3; val_offset:2991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 2991*FLEN/8, x4, x1, x2)

inst_998:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eccce and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6b5891 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20b27b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eccce; op2val:0x3f6b5891;
op3val:0x7f20b27b; valaddr_reg:x3; val_offset:2994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 2994*FLEN/8, x4, x1, x2)

inst_999:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eccce and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6b5891 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x20b27b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eccce; op2val:0x3f6b5891;
op3val:0x7f20b27b; valaddr_reg:x3; val_offset:2997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 2997*FLEN/8, x4, x1, x2)

inst_1000:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ed4d8 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6bab23 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20f242 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ed4d8; op2val:0x3eebab23;
op3val:0x7ea0f242; valaddr_reg:x3; val_offset:3000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3000*FLEN/8, x4, x1, x2)

inst_1001:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ed4d8 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6bab23 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20f242 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ed4d8; op2val:0x3eebab23;
op3val:0x7ea0f242; valaddr_reg:x3; val_offset:3003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3003*FLEN/8, x4, x1, x2)

inst_1002:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ed4d8 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6bab23 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20f242 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ed4d8; op2val:0x3eebab23;
op3val:0x7ea0f242; valaddr_reg:x3; val_offset:3006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3006*FLEN/8, x4, x1, x2)

inst_1003:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ed4d8 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6bab23 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20f242 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ed4d8; op2val:0x3eebab23;
op3val:0x7ea0f242; valaddr_reg:x3; val_offset:3009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3009*FLEN/8, x4, x1, x2)

inst_1004:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2ed4d8 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6bab23 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x20f242 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2ed4d8; op2val:0x3eebab23;
op3val:0x7ea0f242; valaddr_reg:x3; val_offset:3012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3012*FLEN/8, x4, x1, x2)

inst_1005:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2efd0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7ef82d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2e48b6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2efd0c; op2val:0x3f7ef82d;
op3val:0x7f2e48b6; valaddr_reg:x3; val_offset:3015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3015*FLEN/8, x4, x1, x2)

inst_1006:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2efd0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7ef82d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2e48b6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2efd0c; op2val:0x3f7ef82d;
op3val:0x7f2e48b6; valaddr_reg:x3; val_offset:3018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3018*FLEN/8, x4, x1, x2)

inst_1007:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2efd0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7ef82d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2e48b6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2efd0c; op2val:0x3f7ef82d;
op3val:0x7f2e48b6; valaddr_reg:x3; val_offset:3021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3021*FLEN/8, x4, x1, x2)

inst_1008:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2efd0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7ef82d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2e48b6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2efd0c; op2val:0x3f7ef82d;
op3val:0x7f2e48b6; valaddr_reg:x3; val_offset:3024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3024*FLEN/8, x4, x1, x2)

inst_1009:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2efd0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x7ef82d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2e48b6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2efd0c; op2val:0x3f7ef82d;
op3val:0x7f2e48b6; valaddr_reg:x3; val_offset:3027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3027*FLEN/8, x4, x1, x2)

inst_1010:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2f0a94 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x19db73 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5266c0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2f0a94; op2val:0x3e99db73;
op3val:0x7e5266c0; valaddr_reg:x3; val_offset:3030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3030*FLEN/8, x4, x1, x2)

inst_1011:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2f0a94 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x19db73 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5266c0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2f0a94; op2val:0x3e99db73;
op3val:0x7e5266c0; valaddr_reg:x3; val_offset:3033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3033*FLEN/8, x4, x1, x2)

inst_1012:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2f0a94 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x19db73 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5266c0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2f0a94; op2val:0x3e99db73;
op3val:0x7e5266c0; valaddr_reg:x3; val_offset:3036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3036*FLEN/8, x4, x1, x2)

inst_1013:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2f0a94 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x19db73 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5266c0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2f0a94; op2val:0x3e99db73;
op3val:0x7e5266c0; valaddr_reg:x3; val_offset:3039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3039*FLEN/8, x4, x1, x2)

inst_1014:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2f0a94 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x19db73 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5266c0 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2f0a94; op2val:0x3e99db73;
op3val:0x7e5266c0; valaddr_reg:x3; val_offset:3042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3042*FLEN/8, x4, x1, x2)

inst_1015:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x307a0a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x723d58 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x26fda7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f307a0a; op2val:0x3f723d58;
op3val:0x7f26fda7; valaddr_reg:x3; val_offset:3045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3045*FLEN/8, x4, x1, x2)

inst_1016:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x307a0a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x723d58 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x26fda7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f307a0a; op2val:0x3f723d58;
op3val:0x7f26fda7; valaddr_reg:x3; val_offset:3048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3048*FLEN/8, x4, x1, x2)

inst_1017:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x307a0a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x723d58 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x26fda7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f307a0a; op2val:0x3f723d58;
op3val:0x7f26fda7; valaddr_reg:x3; val_offset:3051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3051*FLEN/8, x4, x1, x2)

inst_1018:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x307a0a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x723d58 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x26fda7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f307a0a; op2val:0x3f723d58;
op3val:0x7f26fda7; valaddr_reg:x3; val_offset:3054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3054*FLEN/8, x4, x1, x2)

inst_1019:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x307a0a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x723d58 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x26fda7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f307a0a; op2val:0x3f723d58;
op3val:0x7f26fda7; valaddr_reg:x3; val_offset:3057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3057*FLEN/8, x4, x1, x2)

inst_1020:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x309a0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x50c5b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x100590 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f309a0c; op2val:0x3f50c5b9;
op3val:0x7f100590; valaddr_reg:x3; val_offset:3060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3060*FLEN/8, x4, x1, x2)

inst_1021:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x309a0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x50c5b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x100590 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f309a0c; op2val:0x3f50c5b9;
op3val:0x7f100590; valaddr_reg:x3; val_offset:3063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3063*FLEN/8, x4, x1, x2)

inst_1022:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x309a0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x50c5b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x100590 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f309a0c; op2val:0x3f50c5b9;
op3val:0x7f100590; valaddr_reg:x3; val_offset:3066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3066*FLEN/8, x4, x1, x2)

inst_1023:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x309a0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x50c5b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x100590 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f309a0c; op2val:0x3f50c5b9;
op3val:0x7f100590; valaddr_reg:x3; val_offset:3069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3069*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_9)

inst_1024:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x309a0c and fs2 == 0 and fe2 == 0x7e and fm2 == 0x50c5b9 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x100590 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f309a0c; op2val:0x3f50c5b9;
op3val:0x7f100590; valaddr_reg:x3; val_offset:3072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3072*FLEN/8, x4, x1, x2)

inst_1025:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310e27 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x0dbfdf and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x4412ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f310e27; op2val:0x3d0dbfdf;
op3val:0x7cc412ff; valaddr_reg:x3; val_offset:3075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3075*FLEN/8, x4, x1, x2)

inst_1026:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310e27 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x0dbfdf and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x4412ff and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f310e27; op2val:0x3d0dbfdf;
op3val:0x7cc412ff; valaddr_reg:x3; val_offset:3078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3078*FLEN/8, x4, x1, x2)

inst_1027:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310e27 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x0dbfdf and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x4412ff and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f310e27; op2val:0x3d0dbfdf;
op3val:0x7cc412ff; valaddr_reg:x3; val_offset:3081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3081*FLEN/8, x4, x1, x2)

inst_1028:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310e27 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x0dbfdf and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x4412ff and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f310e27; op2val:0x3d0dbfdf;
op3val:0x7cc412ff; valaddr_reg:x3; val_offset:3084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3084*FLEN/8, x4, x1, x2)

inst_1029:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x310e27 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x0dbfdf and fs3 == 0 and fe3 == 0xf9 and fm3 == 0x4412ff and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f310e27; op2val:0x3d0dbfdf;
op3val:0x7cc412ff; valaddr_reg:x3; val_offset:3087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3087*FLEN/8, x4, x1, x2)

inst_1030:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x313b25 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5093fc and fs3 == 0 and fe3 == 0xfd and fm3 == 0x106682 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f313b25; op2val:0x3ed093fc;
op3val:0x7e906682; valaddr_reg:x3; val_offset:3090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3090*FLEN/8, x4, x1, x2)

inst_1031:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x313b25 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5093fc and fs3 == 0 and fe3 == 0xfd and fm3 == 0x106682 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f313b25; op2val:0x3ed093fc;
op3val:0x7e906682; valaddr_reg:x3; val_offset:3093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3093*FLEN/8, x4, x1, x2)

inst_1032:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x313b25 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5093fc and fs3 == 0 and fe3 == 0xfd and fm3 == 0x106682 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f313b25; op2val:0x3ed093fc;
op3val:0x7e906682; valaddr_reg:x3; val_offset:3096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3096*FLEN/8, x4, x1, x2)

inst_1033:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x313b25 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5093fc and fs3 == 0 and fe3 == 0xfd and fm3 == 0x106682 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f313b25; op2val:0x3ed093fc;
op3val:0x7e906682; valaddr_reg:x3; val_offset:3099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3099*FLEN/8, x4, x1, x2)

inst_1034:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x313b25 and fs2 == 0 and fe2 == 0x7d and fm2 == 0x5093fc and fs3 == 0 and fe3 == 0xfd and fm3 == 0x106682 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f313b25; op2val:0x3ed093fc;
op3val:0x7e906682; valaddr_reg:x3; val_offset:3102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3102*FLEN/8, x4, x1, x2)

inst_1035:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e959 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x453067 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x090a35 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f31e959; op2val:0x3dc53067;
op3val:0x7d890a35; valaddr_reg:x3; val_offset:3105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3105*FLEN/8, x4, x1, x2)

inst_1036:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e959 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x453067 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x090a35 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f31e959; op2val:0x3dc53067;
op3val:0x7d890a35; valaddr_reg:x3; val_offset:3108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3108*FLEN/8, x4, x1, x2)

inst_1037:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e959 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x453067 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x090a35 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f31e959; op2val:0x3dc53067;
op3val:0x7d890a35; valaddr_reg:x3; val_offset:3111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3111*FLEN/8, x4, x1, x2)

inst_1038:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e959 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x453067 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x090a35 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f31e959; op2val:0x3dc53067;
op3val:0x7d890a35; valaddr_reg:x3; val_offset:3114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3114*FLEN/8, x4, x1, x2)

inst_1039:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x31e959 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x453067 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x090a35 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f31e959; op2val:0x3dc53067;
op3val:0x7d890a35; valaddr_reg:x3; val_offset:3117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3117*FLEN/8, x4, x1, x2)

inst_1040:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x346ab9 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x366217 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x008901 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f346ab9; op2val:0x3db66217;
op3val:0x7d808901; valaddr_reg:x3; val_offset:3120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3120*FLEN/8, x4, x1, x2)

inst_1041:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x346ab9 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x366217 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x008901 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f346ab9; op2val:0x3db66217;
op3val:0x7d808901; valaddr_reg:x3; val_offset:3123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3123*FLEN/8, x4, x1, x2)

inst_1042:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x346ab9 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x366217 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x008901 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f346ab9; op2val:0x3db66217;
op3val:0x7d808901; valaddr_reg:x3; val_offset:3126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3126*FLEN/8, x4, x1, x2)

inst_1043:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x346ab9 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x366217 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x008901 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f346ab9; op2val:0x3db66217;
op3val:0x7d808901; valaddr_reg:x3; val_offset:3129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3129*FLEN/8, x4, x1, x2)

inst_1044:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x346ab9 and fs2 == 0 and fe2 == 0x7b and fm2 == 0x366217 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x008901 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f346ab9; op2val:0x3db66217;
op3val:0x7d808901; valaddr_reg:x3; val_offset:3132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3132*FLEN/8, x4, x1, x2)

inst_1045:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35fe5b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6b4e05 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2747f5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35fe5b; op2val:0x3eeb4e05;
op3val:0x7ea747f5; valaddr_reg:x3; val_offset:3135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3135*FLEN/8, x4, x1, x2)

inst_1046:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35fe5b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6b4e05 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2747f5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35fe5b; op2val:0x3eeb4e05;
op3val:0x7ea747f5; valaddr_reg:x3; val_offset:3138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3138*FLEN/8, x4, x1, x2)

inst_1047:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35fe5b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6b4e05 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2747f5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35fe5b; op2val:0x3eeb4e05;
op3val:0x7ea747f5; valaddr_reg:x3; val_offset:3141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3141*FLEN/8, x4, x1, x2)

inst_1048:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35fe5b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6b4e05 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2747f5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35fe5b; op2val:0x3eeb4e05;
op3val:0x7ea747f5; valaddr_reg:x3; val_offset:3144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3144*FLEN/8, x4, x1, x2)

inst_1049:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35fe5b and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6b4e05 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x2747f5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35fe5b; op2val:0x3eeb4e05;
op3val:0x7ea747f5; valaddr_reg:x3; val_offset:3147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3147*FLEN/8, x4, x1, x2)

inst_1050:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3607d2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a9724 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1b6e21 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3607d2; op2val:0x3f5a9724;
op3val:0x7f1b6e21; valaddr_reg:x3; val_offset:3150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3150*FLEN/8, x4, x1, x2)

inst_1051:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3607d2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a9724 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1b6e21 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3607d2; op2val:0x3f5a9724;
op3val:0x7f1b6e21; valaddr_reg:x3; val_offset:3153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3153*FLEN/8, x4, x1, x2)

inst_1052:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3607d2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a9724 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1b6e21 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3607d2; op2val:0x3f5a9724;
op3val:0x7f1b6e21; valaddr_reg:x3; val_offset:3156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3156*FLEN/8, x4, x1, x2)

inst_1053:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3607d2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a9724 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1b6e21 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3607d2; op2val:0x3f5a9724;
op3val:0x7f1b6e21; valaddr_reg:x3; val_offset:3159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3159*FLEN/8, x4, x1, x2)

inst_1054:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3607d2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5a9724 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1b6e21 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3607d2; op2val:0x3f5a9724;
op3val:0x7f1b6e21; valaddr_reg:x3; val_offset:3162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3162*FLEN/8, x4, x1, x2)

inst_1055:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x365c6a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3cdb59 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06881f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f365c6a; op2val:0x3f3cdb59;
op3val:0x7f06881f; valaddr_reg:x3; val_offset:3165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3165*FLEN/8, x4, x1, x2)

inst_1056:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x365c6a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3cdb59 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06881f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f365c6a; op2val:0x3f3cdb59;
op3val:0x7f06881f; valaddr_reg:x3; val_offset:3168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3168*FLEN/8, x4, x1, x2)

inst_1057:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x365c6a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3cdb59 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06881f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f365c6a; op2val:0x3f3cdb59;
op3val:0x7f06881f; valaddr_reg:x3; val_offset:3171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3171*FLEN/8, x4, x1, x2)

inst_1058:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x365c6a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3cdb59 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06881f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f365c6a; op2val:0x3f3cdb59;
op3val:0x7f06881f; valaddr_reg:x3; val_offset:3174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3174*FLEN/8, x4, x1, x2)

inst_1059:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x365c6a and fs2 == 0 and fe2 == 0x7e and fm2 == 0x3cdb59 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x06881f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f365c6a; op2val:0x3f3cdb59;
op3val:0x7f06881f; valaddr_reg:x3; val_offset:3177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3177*FLEN/8, x4, x1, x2)

inst_1060:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:3180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3180*FLEN/8, x4, x1, x2)

inst_1061:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:3183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3183*FLEN/8, x4, x1, x2)

inst_1062:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:3186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3186*FLEN/8, x4, x1, x2)

inst_1063:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:3189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3189*FLEN/8, x4, x1, x2)

inst_1064:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36a9e2 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x1e600b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6202c3 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f36a9e2; op2val:0x3f1e600b;
op3val:0x7ee202c3; valaddr_reg:x3; val_offset:3192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3192*FLEN/8, x4, x1, x2)

inst_1065:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3983ab and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6439df and fs3 == 0 and fe3 == 0xfd and fm3 == 0x256335 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3983ab; op2val:0x3ee439df;
op3val:0x7ea56335; valaddr_reg:x3; val_offset:3195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3195*FLEN/8, x4, x1, x2)

inst_1066:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3983ab and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6439df and fs3 == 0 and fe3 == 0xfd and fm3 == 0x256335 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3983ab; op2val:0x3ee439df;
op3val:0x7ea56335; valaddr_reg:x3; val_offset:3198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3198*FLEN/8, x4, x1, x2)

inst_1067:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3983ab and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6439df and fs3 == 0 and fe3 == 0xfd and fm3 == 0x256335 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3983ab; op2val:0x3ee439df;
op3val:0x7ea56335; valaddr_reg:x3; val_offset:3201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3201*FLEN/8, x4, x1, x2)

inst_1068:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3983ab and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6439df and fs3 == 0 and fe3 == 0xfd and fm3 == 0x256335 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3983ab; op2val:0x3ee439df;
op3val:0x7ea56335; valaddr_reg:x3; val_offset:3204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3204*FLEN/8, x4, x1, x2)

inst_1069:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3983ab and fs2 == 0 and fe2 == 0x7d and fm2 == 0x6439df and fs3 == 0 and fe3 == 0xfd and fm3 == 0x256335 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3983ab; op2val:0x3ee439df;
op3val:0x7ea56335; valaddr_reg:x3; val_offset:3207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3207*FLEN/8, x4, x1, x2)

inst_1070:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a7368 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x2505b8 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70611a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a7368; op2val:0x3f2505b8;
op3val:0x7ef0611a; valaddr_reg:x3; val_offset:3210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3210*FLEN/8, x4, x1, x2)

inst_1071:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a7368 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x2505b8 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70611a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a7368; op2val:0x3f2505b8;
op3val:0x7ef0611a; valaddr_reg:x3; val_offset:3213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3213*FLEN/8, x4, x1, x2)

inst_1072:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a7368 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x2505b8 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70611a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a7368; op2val:0x3f2505b8;
op3val:0x7ef0611a; valaddr_reg:x3; val_offset:3216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3216*FLEN/8, x4, x1, x2)

inst_1073:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a7368 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x2505b8 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70611a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a7368; op2val:0x3f2505b8;
op3val:0x7ef0611a; valaddr_reg:x3; val_offset:3219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3219*FLEN/8, x4, x1, x2)

inst_1074:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a7368 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x2505b8 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x70611a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a7368; op2val:0x3f2505b8;
op3val:0x7ef0611a; valaddr_reg:x3; val_offset:3222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3222*FLEN/8, x4, x1, x2)

inst_1075:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3bca6f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x15c04d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5bb3c7 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3bca6f; op2val:0x3e95c04d;
op3val:0x7e5bb3c7; valaddr_reg:x3; val_offset:3225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3225*FLEN/8, x4, x1, x2)

inst_1076:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3bca6f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x15c04d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5bb3c7 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3bca6f; op2val:0x3e95c04d;
op3val:0x7e5bb3c7; valaddr_reg:x3; val_offset:3228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3228*FLEN/8, x4, x1, x2)

inst_1077:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3bca6f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x15c04d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5bb3c7 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3bca6f; op2val:0x3e95c04d;
op3val:0x7e5bb3c7; valaddr_reg:x3; val_offset:3231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3231*FLEN/8, x4, x1, x2)

inst_1078:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3bca6f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x15c04d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5bb3c7 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3bca6f; op2val:0x3e95c04d;
op3val:0x7e5bb3c7; valaddr_reg:x3; val_offset:3234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3234*FLEN/8, x4, x1, x2)

inst_1079:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3bca6f and fs2 == 0 and fe2 == 0x7d and fm2 == 0x15c04d and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5bb3c7 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3bca6f; op2val:0x3e95c04d;
op3val:0x7e5bb3c7; valaddr_reg:x3; val_offset:3237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3237*FLEN/8, x4, x1, x2)

inst_1080:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:3240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3240*FLEN/8, x4, x1, x2)

inst_1081:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:3243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3243*FLEN/8, x4, x1, x2)

inst_1082:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:3246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3246*FLEN/8, x4, x1, x2)

inst_1083:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:3249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3249*FLEN/8, x4, x1, x2)

inst_1084:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c0464 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x6941a6 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2b5036 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c0464; op2val:0x3f6941a6;
op3val:0x7f2b5036; valaddr_reg:x3; val_offset:3252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3252*FLEN/8, x4, x1, x2)

inst_1085:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:3255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3255*FLEN/8, x4, x1, x2)

inst_1086:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:3258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3258*FLEN/8, x4, x1, x2)

inst_1087:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:3261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3261*FLEN/8, x4, x1, x2)

inst_1088:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:3264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3264*FLEN/8, x4, x1, x2)

inst_1089:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c58cf and fs2 == 0 and fe2 == 0x7d and fm2 == 0x00090a and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3c661c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c58cf; op2val:0x3e80090a;
op3val:0x7e3c661c; valaddr_reg:x3; val_offset:3267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3267*FLEN/8, x4, x1, x2)

inst_1090:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc8a3 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x5057a9 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x19a3aa and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3cc8a3; op2val:0x3d5057a9;
op3val:0x7d19a3aa; valaddr_reg:x3; val_offset:3270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3270*FLEN/8, x4, x1, x2)

inst_1091:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc8a3 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x5057a9 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x19a3aa and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3cc8a3; op2val:0x3d5057a9;
op3val:0x7d19a3aa; valaddr_reg:x3; val_offset:3273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3273*FLEN/8, x4, x1, x2)

inst_1092:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc8a3 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x5057a9 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x19a3aa and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3cc8a3; op2val:0x3d5057a9;
op3val:0x7d19a3aa; valaddr_reg:x3; val_offset:3276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3276*FLEN/8, x4, x1, x2)

inst_1093:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc8a3 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x5057a9 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x19a3aa and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3cc8a3; op2val:0x3d5057a9;
op3val:0x7d19a3aa; valaddr_reg:x3; val_offset:3279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3279*FLEN/8, x4, x1, x2)

inst_1094:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc8a3 and fs2 == 0 and fe2 == 0x7a and fm2 == 0x5057a9 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x19a3aa and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3cc8a3; op2val:0x3d5057a9;
op3val:0x7d19a3aa; valaddr_reg:x3; val_offset:3282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3282*FLEN/8, x4, x1, x2)

inst_1095:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3de754 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5f097a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25738b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3de754; op2val:0x3f5f097a;
op3val:0x7f25738b; valaddr_reg:x3; val_offset:3285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3285*FLEN/8, x4, x1, x2)

inst_1096:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3de754 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5f097a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25738b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3de754; op2val:0x3f5f097a;
op3val:0x7f25738b; valaddr_reg:x3; val_offset:3288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3288*FLEN/8, x4, x1, x2)

inst_1097:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3de754 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5f097a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25738b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3de754; op2val:0x3f5f097a;
op3val:0x7f25738b; valaddr_reg:x3; val_offset:3291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3291*FLEN/8, x4, x1, x2)

inst_1098:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3de754 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5f097a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25738b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3de754; op2val:0x3f5f097a;
op3val:0x7f25738b; valaddr_reg:x3; val_offset:3294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3294*FLEN/8, x4, x1, x2)

inst_1099:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3de754 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x5f097a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x25738b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3de754; op2val:0x3f5f097a;
op3val:0x7f25738b; valaddr_reg:x3; val_offset:3297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3297*FLEN/8, x4, x1, x2)

inst_1100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ea9e8 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x454378 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12eaff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ea9e8; op2val:0x3f454378;
op3val:0x7f12eaff; valaddr_reg:x3; val_offset:3300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3300*FLEN/8, x4, x1, x2)

inst_1101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ea9e8 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x454378 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12eaff and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ea9e8; op2val:0x3f454378;
op3val:0x7f12eaff; valaddr_reg:x3; val_offset:3303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3303*FLEN/8, x4, x1, x2)

inst_1102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ea9e8 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x454378 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12eaff and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ea9e8; op2val:0x3f454378;
op3val:0x7f12eaff; valaddr_reg:x3; val_offset:3306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3306*FLEN/8, x4, x1, x2)

inst_1103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ea9e8 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x454378 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12eaff and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ea9e8; op2val:0x3f454378;
op3val:0x7f12eaff; valaddr_reg:x3; val_offset:3309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3309*FLEN/8, x4, x1, x2)

inst_1104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ea9e8 and fs2 == 0 and fe2 == 0x7e and fm2 == 0x454378 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12eaff and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ea9e8; op2val:0x3f454378;
op3val:0x7f12eaff; valaddr_reg:x3; val_offset:3312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3312*FLEN/8, x4, x1, x2)

inst_1105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3edebd and fs2 == 0 and fe2 == 0x7e and fm2 == 0x79a9e2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a2550 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3edebd; op2val:0x3f79a9e2;
op3val:0x7f3a2550; valaddr_reg:x3; val_offset:3315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3315*FLEN/8, x4, x1, x2)

inst_1106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3edebd and fs2 == 0 and fe2 == 0x7e and fm2 == 0x79a9e2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a2550 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3edebd; op2val:0x3f79a9e2;
op3val:0x7f3a2550; valaddr_reg:x3; val_offset:3318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3318*FLEN/8, x4, x1, x2)

inst_1107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3edebd and fs2 == 0 and fe2 == 0x7e and fm2 == 0x79a9e2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a2550 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3edebd; op2val:0x3f79a9e2;
op3val:0x7f3a2550; valaddr_reg:x3; val_offset:3321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3321*FLEN/8, x4, x1, x2)

inst_1108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3edebd and fs2 == 0 and fe2 == 0x7e and fm2 == 0x79a9e2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a2550 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3edebd; op2val:0x3f79a9e2;
op3val:0x7f3a2550; valaddr_reg:x3; val_offset:3324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3324*FLEN/8, x4, x1, x2)

inst_1109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3edebd and fs2 == 0 and fe2 == 0x7e and fm2 == 0x79a9e2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3a2550 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3edebd; op2val:0x3f79a9e2;
op3val:0x7f3a2550; valaddr_reg:x3; val_offset:3327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3327*FLEN/8, x4, x1, x2)

inst_1110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3eed5f and fs2 == 0 and fe2 == 0x7e and fm2 == 0x58afb5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x219b54 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3eed5f; op2val:0x3f58afb5;
op3val:0x7f219b54; valaddr_reg:x3; val_offset:3330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3330*FLEN/8, x4, x1, x2)

inst_1111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3eed5f and fs2 == 0 and fe2 == 0x7e and fm2 == 0x58afb5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x219b54 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3eed5f; op2val:0x3f58afb5;
op3val:0x7f219b54; valaddr_reg:x3; val_offset:3333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3333*FLEN/8, x4, x1, x2)

inst_1112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3eed5f and fs2 == 0 and fe2 == 0x7e and fm2 == 0x58afb5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x219b54 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3eed5f; op2val:0x3f58afb5;
op3val:0x7f219b54; valaddr_reg:x3; val_offset:3336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3336*FLEN/8, x4, x1, x2)

inst_1113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3eed5f and fs2 == 0 and fe2 == 0x7e and fm2 == 0x58afb5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x219b54 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3eed5f; op2val:0x3f58afb5;
op3val:0x7f219b54; valaddr_reg:x3; val_offset:3339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3339*FLEN/8, x4, x1, x2)

inst_1114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3eed5f and fs2 == 0 and fe2 == 0x7e and fm2 == 0x58afb5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x219b54 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3eed5f; op2val:0x3f58afb5;
op3val:0x7f219b54; valaddr_reg:x3; val_offset:3342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3342*FLEN/8, x4, x1, x2)

inst_1115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3f0fcc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x363027 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x07f92b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3f0fcc; op2val:0x3f363027;
op3val:0x7f07f92b; valaddr_reg:x3; val_offset:3345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3345*FLEN/8, x4, x1, x2)

inst_1116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3f0fcc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x363027 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x07f92b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3f0fcc; op2val:0x3f363027;
op3val:0x7f07f92b; valaddr_reg:x3; val_offset:3348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3348*FLEN/8, x4, x1, x2)

inst_1117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3f0fcc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x363027 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x07f92b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3f0fcc; op2val:0x3f363027;
op3val:0x7f07f92b; valaddr_reg:x3; val_offset:3351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3351*FLEN/8, x4, x1, x2)

inst_1118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3f0fcc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x363027 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x07f92b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3f0fcc; op2val:0x3f363027;
op3val:0x7f07f92b; valaddr_reg:x3; val_offset:3354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3354*FLEN/8, x4, x1, x2)

inst_1119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3f0fcc and fs2 == 0 and fe2 == 0x7e and fm2 == 0x363027 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x07f92b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3f0fcc; op2val:0x3f363027;
op3val:0x7f07f92b; valaddr_reg:x3; val_offset:3357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3357*FLEN/8, x4, x1, x2)

inst_1120:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3360*FLEN/8, x4, x1, x2)

inst_1121:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3363*FLEN/8, x4, x1, x2)

inst_1122:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3366*FLEN/8, x4, x1, x2)

inst_1123:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3369*FLEN/8, x4, x1, x2)

inst_1124:
// fs1 == 0 and fe1 == 0xf3 and fm1 == 0x319f1b and fs2 == 0 and fe2 == 0x89 and fm2 == 0x376ad3 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e85b6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b19f1b; op2val:0x44b76ad3;
op3val:0x7efe85b6; valaddr_reg:x3; val_offset:3372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3372*FLEN/8, x4, x1, x2)

inst_1125:
// fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:3375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3375*FLEN/8, x4, x1, x2)

inst_1126:
// fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:3378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 64, 0, x3, 3378*FLEN/8, x4, x1, x2)

inst_1127:
// fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:3381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 96, 0, x3, 3381*FLEN/8, x4, x1, x2)

inst_1128:
// fs1 == 0 and fe1 == 0xf5 and fm1 == 0x16be52 and fs2 == 0 and fe2 == 0x88 and fm2 == 0x0fdc26 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x296be5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a96be52; op2val:0x440fdc26;
op3val:0x7f296be5; valaddr_reg:x3; val_offset:3384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 128, 0, x3, 3384*FLEN/8, x4, x1, x2)

inst_1129:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c6d92ab; op2val:0x41dc039b;
op3val:0x7ecc2d63; valaddr_reg:x3; val_offset:3387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 3387*FLEN/8, x4, x1, x2)

inst_1130:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x6d92ab and fs2 == 0 and fe2 == 0x83 and fm2 == 0x5c039b and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4c2d63 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c6d92ab; op2val:0x41dc039b;
op3val:0x7ecc2d63; valaddr_reg:x3; val_offset:3390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 32, 0, x3, 3390*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x79b19f1b041683739,32,FLEN)
NAN_BOXED(0x44b76ad3152871123,32,FLEN)
NAN_BOXED(0x44b76ad3152871123,32,FLEN)
NAN_BOXED(0x79b19f1b041683739,32,FLEN)
NAN_BOXED(0x79b19f1b041683739,32,FLEN)
NAN_BOXED(0x7efe85b6130609590,32,FLEN)
NAN_BOXED(0x79b19f1b041683739,32,FLEN)
NAN_BOXED(0x44b76ad3152871123,32,FLEN)
NAN_BOXED(0x7efe85b6130609590,32,FLEN)
NAN_BOXED(0x79b19f1b041683739,32,FLEN)
NAN_BOXED(0x44b76ad3152871123,32,FLEN)
NAN_BOXED(0x44b76ad3152871123,32,FLEN)
NAN_BOXED(0x79b19f1b041683739,32,FLEN)
NAN_BOXED(0x44b76ad3152871123,32,FLEN)
NAN_BOXED(0x7efe85b6130609590,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x440fdc26141890086,32,FLEN)
NAN_BOXED(0x7f296be5133421029,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x440fdc26141890086,32,FLEN)
NAN_BOXED(0x7f296be5133421029,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x7f296be5133421029,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x440fdc26141890086,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x440fdc26141890086,32,FLEN)
NAN_BOXED(0x7a96be52056699474,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x41dc039b104937883,32,FLEN)
NAN_BOXED(0x7ecc2d63127310179,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x41dc039b104937883,32,FLEN)
NAN_BOXED(0x7ecc2d63127310179,32,FLEN)
NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x41dc039b104937883,32,FLEN)
NAN_BOXED(0x7ecc2d63127310179,32,FLEN)
NAN_BOXED(0x7cac1d45091654469,32,FLEN)
NAN_BOXED(0x42038dbf107529151,32,FLEN)
NAN_BOXED(0x7f30e48e133910670,32,FLEN)
NAN_BOXED(0x7cac1d45091654469,32,FLEN)
NAN_BOXED(0x42038dbf107529151,32,FLEN)
NAN_BOXED(0x7f30e48e133910670,32,FLEN)
NAN_BOXED(0x7cac1d45091654469,32,FLEN)
NAN_BOXED(0x42038dbf107529151,32,FLEN)
NAN_BOXED(0x7f30e48e133910670,32,FLEN)
NAN_BOXED(0x7cac1d45091654469,32,FLEN)
NAN_BOXED(0x42038dbf107529151,32,FLEN)
NAN_BOXED(0x7f30e48e133910670,32,FLEN)
NAN_BOXED(0x7cac1d45091654469,32,FLEN)
NAN_BOXED(0x42038dbf107529151,32,FLEN)
NAN_BOXED(0x7f30e48e133910670,32,FLEN)
NAN_BOXED(0x7cae9fe8091818984,32,FLEN)
NAN_BOXED(0x414b6f55095462741,32,FLEN)
NAN_BOXED(0x7e8ac4bf123023551,32,FLEN)
NAN_BOXED(0x7cae9fe8091818984,32,FLEN)
NAN_BOXED(0x414b6f55095462741,32,FLEN)
NAN_BOXED(0x7e8ac4bf123023551,32,FLEN)
NAN_BOXED(0x7cae9fe8091818984,32,FLEN)
NAN_BOXED(0x414b6f55095462741,32,FLEN)
NAN_BOXED(0x7e8ac4bf123023551,32,FLEN)
NAN_BOXED(0x7cae9fe8091818984,32,FLEN)
NAN_BOXED(0x414b6f55095462741,32,FLEN)
NAN_BOXED(0x7e8ac4bf123023551,32,FLEN)
NAN_BOXED(0x7cae9fe8091818984,32,FLEN)
NAN_BOXED(0x414b6f55095462741,32,FLEN)
NAN_BOXED(0x7e8ac4bf123023551,32,FLEN)
NAN_BOXED(0x7cb78e9e092404382,32,FLEN)
NAN_BOXED(0x4205090e107626254,32,FLEN)
NAN_BOXED(0x7f3ec72e134820654,32,FLEN)
NAN_BOXED(0x7cb78e9e092404382,32,FLEN)
NAN_BOXED(0x4205090e107626254,32,FLEN)
NAN_BOXED(0x7f3ec72e134820654,32,FLEN)
NAN_BOXED(0x7cb78e9e092404382,32,FLEN)
NAN_BOXED(0x4205090e107626254,32,FLEN)
NAN_BOXED(0x7f3ec72e134820654,32,FLEN)
NAN_BOXED(0x7cb78e9e092404382,32,FLEN)
NAN_BOXED(0x4205090e107626254,32,FLEN)
NAN_BOXED(0x7f3ec72e134820654,32,FLEN)
NAN_BOXED(0x7cb78e9e092404382,32,FLEN)
NAN_BOXED(0x4205090e107626254,32,FLEN)
NAN_BOXED(0x7f3ec72e134820654,32,FLEN)
NAN_BOXED(0x7cb9031d092499741,32,FLEN)
NAN_BOXED(0x41cd83ab103987627,32,FLEN)
NAN_BOXED(0x7f1486a7132051623,32,FLEN)
NAN_BOXED(0x7cb9031d092499741,32,FLEN)
NAN_BOXED(0x41cd83ab103987627,32,FLEN)
NAN_BOXED(0x7f1486a7132051623,32,FLEN)
NAN_BOXED(0x7cb9031d092499741,32,FLEN)
NAN_BOXED(0x41cd83ab103987627,32,FLEN)
NAN_BOXED(0x7f1486a7132051623,32,FLEN)
NAN_BOXED(0x7cb9031d092499741,32,FLEN)
NAN_BOXED(0x41cd83ab103987627,32,FLEN)
NAN_BOXED(0x7f1486a7132051623,32,FLEN)
NAN_BOXED(0x7cb9031d092499741,32,FLEN)
NAN_BOXED(0x41cd83ab103987627,32,FLEN)
NAN_BOXED(0x7f1486a7132051623,32,FLEN)
NAN_BOXED(0x7cbb3e27092645927,32,FLEN)
NAN_BOXED(0x4189ecfa099558138,32,FLEN)
NAN_BOXED(0x7ec9c32f127151919,32,FLEN)
NAN_BOXED(0x7cbb3e27092645927,32,FLEN)
NAN_BOXED(0x4189ecfa099558138,32,FLEN)
NAN_BOXED(0x7ec9c32f127151919,32,FLEN)
NAN_BOXED(0x7cbb3e27092645927,32,FLEN)
NAN_BOXED(0x4189ecfa099558138,32,FLEN)
NAN_BOXED(0x7ec9c32f127151919,32,FLEN)
NAN_BOXED(0x7cbb3e27092645927,32,FLEN)
NAN_BOXED(0x4189ecfa099558138,32,FLEN)
NAN_BOXED(0x7ec9c32f127151919,32,FLEN)
NAN_BOXED(0x7cbb3e27092645927,32,FLEN)
NAN_BOXED(0x4189ecfa099558138,32,FLEN)
NAN_BOXED(0x7ec9c32f127151919,32,FLEN)
NAN_BOXED(0x7cc5b82c093332524,32,FLEN)
NAN_BOXED(0x4186ed1d099361565,32,FLEN)
NAN_BOXED(0x7ed06b12127588114,32,FLEN)
NAN_BOXED(0x7cc5b82c093332524,32,FLEN)
NAN_BOXED(0x4186ed1d099361565,32,FLEN)
NAN_BOXED(0x7ed06b12127588114,32,FLEN)
NAN_BOXED(0x7cc5b82c093332524,32,FLEN)
NAN_BOXED(0x4186ed1d099361565,32,FLEN)
NAN_BOXED(0x7ed06b12127588114,32,FLEN)
NAN_BOXED(0x7cc5b82c093332524,32,FLEN)
NAN_BOXED(0x4186ed1d099361565,32,FLEN)
NAN_BOXED(0x7ed06b12127588114,32,FLEN)
NAN_BOXED(0x7cc5b82c093332524,32,FLEN)
NAN_BOXED(0x4186ed1d099361565,32,FLEN)
NAN_BOXED(0x7ed06b12127588114,32,FLEN)
NAN_BOXED(0x7cc8fcb3093546675,32,FLEN)
NAN_BOXED(0x40a98476084851318,32,FLEN)
NAN_BOXED(0x7e0516d1114262737,32,FLEN)
NAN_BOXED(0x7cc8fcb3093546675,32,FLEN)
NAN_BOXED(0x40a98476084851318,32,FLEN)
NAN_BOXED(0x7e0516d1114262737,32,FLEN)
NAN_BOXED(0x7cc8fcb3093546675,32,FLEN)
NAN_BOXED(0x40a98476084851318,32,FLEN)
NAN_BOXED(0x7e0516d1114262737,32,FLEN)
NAN_BOXED(0x7cc8fcb3093546675,32,FLEN)
NAN_BOXED(0x40a98476084851318,32,FLEN)
NAN_BOXED(0x7e0516d1114262737,32,FLEN)
NAN_BOXED(0x7cc8fcb3093546675,32,FLEN)
NAN_BOXED(0x40a98476084851318,32,FLEN)
NAN_BOXED(0x7e0516d1114262737,32,FLEN)
NAN_BOXED(0x7cc9296d093558125,32,FLEN)
NAN_BOXED(0x41336a25093888549,32,FLEN)
NAN_BOXED(0x7e8cfb60123168608,32,FLEN)
NAN_BOXED(0x7cc9296d093558125,32,FLEN)
NAN_BOXED(0x41336a25093888549,32,FLEN)
NAN_BOXED(0x7e8cfb60123168608,32,FLEN)
NAN_BOXED(0x7cc9296d093558125,32,FLEN)
NAN_BOXED(0x41336a25093888549,32,FLEN)
NAN_BOXED(0x7e8cfb60123168608,32,FLEN)
NAN_BOXED(0x7cc9296d093558125,32,FLEN)
NAN_BOXED(0x41336a25093888549,32,FLEN)
NAN_BOXED(0x7e8cfb60123168608,32,FLEN)
NAN_BOXED(0x7cc9296d093558125,32,FLEN)
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NAN_BOXED(0x7c6d92ab087555755,32,FLEN)
NAN_BOXED(0x41dc039b104937883,32,FLEN)
NAN_BOXED(0x7ecc2d63127310179,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 214*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
