
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 05:45:15 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fadd.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fadd_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fadd_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x18,test_dataset_0)
RVTEST_SIGBASE(x8,signature_x8_1)

inst_0:
// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x29; op2:x29; dest:x15; op1val:0x32; op2val:0x32; 
   valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x15, x29, x29, dyn, 0, 0, x18, 0*FLEN/8, x19, x8, x9)

inst_1:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x0, rs2==x17, rd==x5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x034 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x0; op2:x17; dest:x5; op1val:0x0; op2val:0x8034; 
   valaddr_reg:x18; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x5, x0, x17, dyn, 0, 0, x18, 2*FLEN/8, x19, x8, x9)

inst_2:
// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x13; op2:x13; dest:x13; op1val:0x22; op2val:0x22; 
   valaddr_reg:x18; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x13, x13, x13, dyn, 0, 0, x18, 4*FLEN/8, x19, x8, x9)

inst_3:
// rs2 == rd != rs1, rs1==x17, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x037 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x17; op2:x0; dest:x0; op1val:0x3f; op2val:0x0; 
   valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x0, x17, x0, dyn, 0, 0, x18, 6*FLEN/8, x19, x8, x9)

inst_4:
// rs1 == rd != rs2, rs1==x2, rs2==x30, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x2; op2:x30; dest:x2; op1val:0x27; op2val:0x8017; 
   valaddr_reg:x18; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x2, x2, x30, dyn, 0, 0, x18, 8*FLEN/8, x19, x8, x9)

inst_5:
// rs1==x1, rs2==x26, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x1; op2:x26; dest:x23; op1val:0x2e; op2val:0x800e; 
   valaddr_reg:x18; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x23, x1, x26, dyn, 0, 0, x18, 10*FLEN/8, x19, x8, x9)

inst_6:
// rs1==x12, rs2==x24, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x024 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x12; op2:x24; dest:x11; op1val:0x1c; op2val:0x24; 
   valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x11, x12, x24, dyn, 0, 0, x18, 12*FLEN/8, x19, x8, x9)

inst_7:
// rs1==x7, rs2==x28, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x06e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x7; op2:x28; dest:x22; op1val:0x12; op2val:0x6e; 
   valaddr_reg:x18; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x22, x7, x28, dyn, 0, 0, x18, 14*FLEN/8, x19, x8, x9)

inst_8:
// rs1==x22, rs2==x4, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x22; op2:x4; dest:x14; op1val:0x12; op2val:0xee; 
   valaddr_reg:x18; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x14, x22, x4, dyn, 0, 0, x18, 16*FLEN/8, x19, x8, x9)

inst_9:
// rs1==x11, rs2==x7, rd==x3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1f3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x11; op2:x7; dest:x3; op1val:0xd; op2val:0x1f3; 
   valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x3, x11, x7, dyn, 0, 0, x18, 18*FLEN/8, x19, x8, x9)

inst_10:
// rs1==x23, rs2==x1, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x022 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x23; op2:x1; dest:x6; op1val:0x21; op2val:0x8022; 
   valaddr_reg:x18; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x6, x23, x1, dyn, 0, 0, x18, 20*FLEN/8, x19, x8, x9)

inst_11:
// rs1==x20, rs2==x12, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x20; op2:x12; dest:x16; op1val:0x5b; op2val:0x805d; 
   valaddr_reg:x18; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x16, x20, x12, dyn, 0, 0, x18, 22*FLEN/8, x19, x8, x9)

inst_12:
// rs1==x10, rs2==x14, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x10; op2:x14; dest:x20; op1val:0x13; op2val:0x8017; 
   valaddr_reg:x18; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x20, x10, x14, dyn, 0, 0, x18, 24*FLEN/8, x19, x8, x9)
RVTEST_VALBASEUPD(x2,test_dataset_1)

inst_13:
// rs1==x27, rs2==x23, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x27; op2:x23; dest:x18; op1val:0xd; op2val:0x8015; 
   valaddr_reg:x2; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9 
*/
TEST_FPRR_OP(fadd.h, x18, x27, x23, dyn, 0, 0, x2, 0*FLEN/8, x5, x8, x9)

inst_14:
// rs1==x4, rs2==x22, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x4; op2:x22; dest:x25; op1val:0xa; op2val:0x801a; 
   valaddr_reg:x2; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x25, x4, x22, dyn, 0, 0, x2, 2*FLEN/8, x5, x8, x1)
RVTEST_SIGBASE(x13,signature_x13_0)

inst_15:
// rs1==x6, rs2==x21, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x6; op2:x21; dest:x19; op1val:0x2b; op2val:0x804b; 
   valaddr_reg:x2; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x19, x6, x21, dyn, 0, 0, x2, 4*FLEN/8, x5, x13, x1)

inst_16:
// rs1==x21, rs2==x6, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x088 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x21; op2:x6; dest:x12; op1val:0x48; op2val:0x8088; 
   valaddr_reg:x2; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x12, x21, x6, dyn, 0, 0, x2, 6*FLEN/8, x5, x13, x1)

inst_17:
// rs1==x19, rs2==x10, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x19; op2:x10; dest:x29; op1val:0x2e; op2val:0x80ae; 
   valaddr_reg:x2; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x29, x19, x10, dyn, 0, 0, x2, 8*FLEN/8, x5, x13, x1)

inst_18:
// rs1==x18, rs2==x8, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x129 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x18; op2:x8; dest:x27; op1val:0x29; op2val:0x8129; 
   valaddr_reg:x2; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x27, x18, x8, dyn, 0, 0, x2, 10*FLEN/8, x5, x13, x1)

inst_19:
// rs1==x9, rs2==x18, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x252 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x9; op2:x18; dest:x4; op1val:0x52; op2val:0x8252; 
   valaddr_reg:x2; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x4, x9, x18, dyn, 0, 0, x2, 12*FLEN/8, x5, x13, x1)

inst_20:
// rs1==x31, rs2==x11, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x060 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x31; op2:x11; dest:x17; op1val:0x3c47; op2val:0xac60; 
   valaddr_reg:x2; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x17, x31, x11, dyn, 0, 0, x2, 14*FLEN/8, x5, x13, x1)

inst_21:
// rs1==x14, rs2==x9, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x14; op2:x9; dest:x26; op1val:0x3c39; op2val:0xaae0; 
   valaddr_reg:x2; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x26, x14, x9, dyn, 0, 0, x2, 16*FLEN/8, x5, x13, x1)

inst_22:
// rs1==x24, rs2==x15, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x022 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x380 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x24; op2:x15; dest:x28; op1val:0x3c22; op2val:0xa780; 
   valaddr_reg:x2; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x28, x24, x15, dyn, 0, 0, x2, 18*FLEN/8, x5, x13, x1)

inst_23:
// rs1==x15, rs2==x27, rd==x24,fs1 == 0 and fe1 == 0x0f and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x15; op2:x27; dest:x24; op1val:0x3c47; op2val:0xabe0; 
   valaddr_reg:x2; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x24, x15, x27, dyn, 0, 0, x2, 20*FLEN/8, x5, x13, x1)

inst_24:
// rs1==x30, rs2==x3, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00c and fs2 == 0 and fe2 == 0x07 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x3; dest:x10; op1val:0x3c0c; op2val:0x1c00; 
   valaddr_reg:x2; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x10, x30, x3, dyn, 0, 0, x2, 22*FLEN/8, x5, x13, x1)
RVTEST_VALBASEUPD(x4,test_dataset_2)

inst_25:
// rs1==x3, rs2==x2, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x034 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x100 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x3; op2:x2; dest:x31; op1val:0x3c34; op2val:0xa500; 
   valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x31, x3, x2, dyn, 0, 0, x4, 0*FLEN/8, x6, x13, x1)

inst_26:
// rs1==x26, rs2==x31, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x056 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x180 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x26; op2:x31; dest:x7; op1val:0x3c56; op2val:0xa580; 
   valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x1 
*/
TEST_FPRR_OP(fadd.h, x7, x26, x31, dyn, 0, 0, x4, 2*FLEN/8, x6, x13, x1)

inst_27:
// rs1==x5, rs2==x25, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x5; op2:x25; dest:x21; op1val:0x3c01; op2val:0x2ff0; 
   valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x21, x5, x25, dyn, 0, 0, x4, 4*FLEN/8, x6, x13, x2)

inst_28:
// rs1==x8, rs2==x19, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x8; op2:x19; dest:x1; op1val:0x3c40; op2val:0x3200; 
   valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x1, x8, x19, dyn, 0, 0, x4, 6*FLEN/8, x6, x13, x2)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_29:
// rs1==x28, rs2==x20, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x380 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x28; op2:x20; dest:x30; op1val:0x3c20; op2val:0x3780; 
   valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x30, x28, x20, dyn, 0, 0, x4, 8*FLEN/8, x6, x1, x2)

inst_30:
// rs1==x25, rs2==x16, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x25; op2:x16; dest:x9; op1val:0x3c2a; op2val:0xc015; 
   valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x9, x25, x16, dyn, 0, 0, x4, 10*FLEN/8, x6, x1, x2)

inst_31:
// rs1==x16, rs2==x5, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x16; op2:x5; dest:x8; op1val:0x3c09; op2val:0xc005; 
   valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x8, x16, x5, dyn, 0, 0, x4, 12*FLEN/8, x6, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x026 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c49; op2val:0xc026; 
   valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 14*FLEN/8, x6, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x013 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1f; op2val:0xc013; 
   valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 16*FLEN/8, x6, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x046 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c46; op2val:0xc02b; 
   valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x6, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x016 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c0c; op2val:0xc016; 
   valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 20*FLEN/8, x6, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x034 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c29; op2val:0xc034; 
   valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 22*FLEN/8, x6, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c3f; op2val:0xc05f; 
   valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 24*FLEN/8, x6, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x093 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c27; op2val:0xc093; 
   valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 26*FLEN/8, x6, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x026 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x113 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c26; op2val:0xc113; 
   valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x6, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x10; op2val:0x800e; 
   valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 30*FLEN/8, x6, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0x8028; 
   valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 32*FLEN/8, x6, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x016 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1b; op2val:0x8016; 
   valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 34*FLEN/8, x6, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x47; op2val:0x803e; 
   valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 36*FLEN/8, x6, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x25; op2val:0x8014; 
   valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x6, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc; op2val:0x15; 
   valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 40*FLEN/8, x6, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32; op2val:0xf; 
   valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 42*FLEN/8, x6, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x037 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a; op2val:0x37; 
   valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 44*FLEN/8, x6, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0db and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x26; op2val:0xdb; 
   valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 46*FLEN/8, x6, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1e8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x19; op2val:0x1e8; 
   valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x6, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x006 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x8006; 
   valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 50*FLEN/8, x6, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x058 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x8058; 
   valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 52*FLEN/8, x6, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x042 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3d; op2val:0x8042; 
   valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 54*FLEN/8, x6, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x015 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xc; op2val:0x8015; 
   valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 56*FLEN/8, x6, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x061 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x072 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x61; op2val:0x8072; 
   valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x6, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x035 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x14; op2val:0x8035; 
   valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 60*FLEN/8, x6, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb; op2val:0x804c; 
   valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 62*FLEN/8, x6, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0c7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x46; op2val:0x80c7; 
   valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 64*FLEN/8, x6, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x134 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x33; op2val:0x8134; 
   valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 66*FLEN/8, x6, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x245 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44; op2val:0x8245; 
   valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x6, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3bb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43; op2val:0x3bb; 
   valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 70*FLEN/8, x6, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3e1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1c; op2val:0x3e1; 
   valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 72*FLEN/8, x6, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4c; op2val:0x3af; 
   valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 74*FLEN/8, x6, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ac and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4b; op2val:0x3ac; 
   valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 76*FLEN/8, x6, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3b5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3a; op2val:0x3b5; 
   valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x6, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x38a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x55; op2val:0x38a; 
   valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 80*FLEN/8, x6, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x365 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5a; op2val:0x365; 
   valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 82*FLEN/8, x6, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x374 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0xb; op2val:0x374; 
   valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 84*FLEN/8, x6, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0x2b0; 
   valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 86*FLEN/8, x6, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x1c0; 
   valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x6, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x04f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x51; op2val:0x844f; 
   valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 90*FLEN/8, x6, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x016 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x19; op2val:0x8416; 
   valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 92*FLEN/8, x6, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0x83fe; 
   valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 94*FLEN/8, x6, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x23; op2val:0x841a; 
   valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 96*FLEN/8, x6, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x01 and fm2 == 0x04a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x5b; op2val:0x844a; 
   valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x6, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x00f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x30; op2val:0x840f; 
   valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 100*FLEN/8, x6, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ea and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0x83ea; 
   valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 102*FLEN/8, x6, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x387 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x8; op2val:0x8387; 
   valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 104*FLEN/8, x6, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x312 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x13; op2val:0x8312; 
   valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 106*FLEN/8, x6, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x1d; op2val:0x821c; 
   valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x6, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x049 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44a; op2val:0x8049; 
   valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 110*FLEN/8, x6, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x045 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x043 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x445; op2val:0x8043; 
   valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 112*FLEN/8, x6, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x054 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x458; op2val:0x8054; 
   valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 114*FLEN/8, x6, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x404; op2val:0x4; 
   valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 116*FLEN/8, x6, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x042 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x452; op2val:0x8042; 
   valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x6, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x02e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44e; op2val:0x802e; 
   valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 120*FLEN/8, x6, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x410; op2val:0x30; 
   valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 122*FLEN/8, x6, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x074 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40c; op2val:0x74; 
   valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 124*FLEN/8, x6, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x40f; op2val:0xf1; 
   valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 126*FLEN/8, x6, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1b2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x44e; op2val:0x1b2; 
   valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x6, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x00d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x419; op2val:0x880d; 
   valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 130*FLEN/8, x6, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x02 and fm2 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x45c; op2val:0x882f; 
   valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 132*FLEN/8, x6, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x02 and fm2 == 0x021 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x43e; op2val:0x8821; 
   valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 134*FLEN/8, x6, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x02 and fm2 == 0x033 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x45e; op2val:0x8833; 
   valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 136*FLEN/8, x6, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x033 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0x8833; 
   valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x6, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x033 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x446; op2val:0x8833; 
   valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 140*FLEN/8, x6, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x048 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x450; op2val:0x8848; 
   valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 142*FLEN/8, x6, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x051 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x422; op2val:0x8851; 
   valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 144*FLEN/8, x6, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01d and fs2 == 1 and fe2 == 0x02 and fm2 == 0x08e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x41d; op2val:0x888e; 
   valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 146*FLEN/8, x6, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x02 and fm2 == 0x129 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x453; op2val:0x8929; 
   valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x6, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782d; op2val:0x77a2; 
   valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 150*FLEN/8, x6, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ca and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7818; op2val:0x77ca; 
   valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 152*FLEN/8, x6, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x374 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7841; op2val:0x7774; 
   valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 154*FLEN/8, x6, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7806; op2val:0x77e2; 
   valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 156*FLEN/8, x6, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x780d; op2val:0x77c4; 
   valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x6, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x358 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7833; op2val:0x7758; 
   valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 160*FLEN/8, x6, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x33a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7822; op2val:0x773a; 
   valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 162*FLEN/8, x6, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x242 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x785e; op2val:0x7642; 
   valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 164*FLEN/8, x6, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x049 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7849; op2val:0x756c; 
   valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 166*FLEN/8, x6, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0x7294; 
   valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x6, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 170*FLEN/8, x6, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 172*FLEN/8, x6, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7815; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 174*FLEN/8, x6, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02c and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x782c; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 176*FLEN/8, x6, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7821; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x6, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 180*FLEN/8, x6, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x056 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7856; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 182*FLEN/8, x6, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7802; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 184*FLEN/8, x6, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7858; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 186*FLEN/8, x6, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x049 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x7849; op2val:0xfc00; 
   valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x6, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x32; op2val:0x8030; 
   valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 190*FLEN/8, x6, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x034 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x36; op2val:0x8034; 
   valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 192*FLEN/8, x6, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x22; op2val:0x801e; 
   valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 194*FLEN/8, x6, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x037 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fadd.h ; op1:x30; op2:x29; dest:x31; op1val:0x3f; op2val:0x8037; 
   valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2 
*/
TEST_FPRR_OP(fadd.h, x31, x30, x29, dyn, 0, 0, x4, 196*FLEN/8, x6, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(50,32,FLEN)
NAN_BOXED(50,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(32820,16,FLEN)
NAN_BOXED(34,32,FLEN)
NAN_BOXED(34,16,FLEN)
NAN_BOXED(63,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(39,32,FLEN)
NAN_BOXED(32791,16,FLEN)
NAN_BOXED(46,32,FLEN)
NAN_BOXED(32782,16,FLEN)
NAN_BOXED(28,32,FLEN)
NAN_BOXED(36,32,FLEN)
NAN_BOXED(18,32,FLEN)
NAN_BOXED(110,32,FLEN)
NAN_BOXED(18,32,FLEN)
NAN_BOXED(238,32,FLEN)
NAN_BOXED(13,32,FLEN)
NAN_BOXED(499,32,FLEN)
NAN_BOXED(33,32,FLEN)
NAN_BOXED(32802,16,FLEN)
NAN_BOXED(91,32,FLEN)
NAN_BOXED(32861,16,FLEN)
NAN_BOXED(19,32,FLEN)
NAN_BOXED(32791,16,FLEN)
test_dataset_1:
NAN_BOXED(13,32,FLEN)
NAN_BOXED(32789,16,FLEN)
NAN_BOXED(10,32,FLEN)
NAN_BOXED(32794,16,FLEN)
NAN_BOXED(43,32,FLEN)
NAN_BOXED(32843,16,FLEN)
NAN_BOXED(72,32,FLEN)
NAN_BOXED(32904,16,FLEN)
NAN_BOXED(46,32,FLEN)
NAN_BOXED(32942,16,FLEN)
NAN_BOXED(41,32,FLEN)
NAN_BOXED(33065,16,FLEN)
NAN_BOXED(82,32,FLEN)
NAN_BOXED(33362,16,FLEN)
NAN_BOXED(15431,32,FLEN)
NAN_BOXED(44128,16,FLEN)
NAN_BOXED(15417,32,FLEN)
NAN_BOXED(43744,16,FLEN)
NAN_BOXED(15394,32,FLEN)
NAN_BOXED(42880,16,FLEN)
NAN_BOXED(15431,32,FLEN)
NAN_BOXED(44000,16,FLEN)
NAN_BOXED(15372,32,FLEN)
NAN_BOXED(7168,32,FLEN)
test_dataset_2:
NAN_BOXED(15412,16,FLEN)
NAN_BOXED(42240,16,FLEN)
NAN_BOXED(15446,16,FLEN)
NAN_BOXED(42368,16,FLEN)
NAN_BOXED(15361,16,FLEN)
NAN_BOXED(12272,16,FLEN)
NAN_BOXED(15424,16,FLEN)
NAN_BOXED(12800,16,FLEN)
NAN_BOXED(15392,16,FLEN)
NAN_BOXED(14208,16,FLEN)
NAN_BOXED(15402,16,FLEN)
NAN_BOXED(49173,16,FLEN)
NAN_BOXED(15369,16,FLEN)
NAN_BOXED(49157,16,FLEN)
NAN_BOXED(15433,16,FLEN)
NAN_BOXED(49190,16,FLEN)
NAN_BOXED(15391,16,FLEN)
NAN_BOXED(49171,16,FLEN)
NAN_BOXED(15430,16,FLEN)
NAN_BOXED(49195,16,FLEN)
NAN_BOXED(15372,16,FLEN)
NAN_BOXED(49174,16,FLEN)
NAN_BOXED(15401,16,FLEN)
NAN_BOXED(49204,16,FLEN)
NAN_BOXED(15423,16,FLEN)
NAN_BOXED(49247,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(49299,16,FLEN)
NAN_BOXED(15398,16,FLEN)
NAN_BOXED(49427,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(32782,16,FLEN)
NAN_BOXED(43,16,FLEN)
NAN_BOXED(32808,16,FLEN)
NAN_BOXED(27,16,FLEN)
NAN_BOXED(32790,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(32830,16,FLEN)
NAN_BOXED(37,16,FLEN)
NAN_BOXED(32788,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(21,16,FLEN)
NAN_BOXED(50,16,FLEN)
NAN_BOXED(15,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(55,16,FLEN)
NAN_BOXED(38,16,FLEN)
NAN_BOXED(219,16,FLEN)
NAN_BOXED(25,16,FLEN)
NAN_BOXED(488,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(32774,16,FLEN)
NAN_BOXED(85,16,FLEN)
NAN_BOXED(32856,16,FLEN)
NAN_BOXED(61,16,FLEN)
NAN_BOXED(32834,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(32789,16,FLEN)
NAN_BOXED(97,16,FLEN)
NAN_BOXED(32882,16,FLEN)
NAN_BOXED(20,16,FLEN)
NAN_BOXED(32821,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(32844,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(32967,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(33076,16,FLEN)
NAN_BOXED(68,16,FLEN)
NAN_BOXED(33349,16,FLEN)
NAN_BOXED(67,16,FLEN)
NAN_BOXED(955,16,FLEN)
NAN_BOXED(28,16,FLEN)
NAN_BOXED(993,16,FLEN)
NAN_BOXED(76,16,FLEN)
NAN_BOXED(943,16,FLEN)
NAN_BOXED(75,16,FLEN)
NAN_BOXED(940,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(949,16,FLEN)
NAN_BOXED(85,16,FLEN)
NAN_BOXED(906,16,FLEN)
NAN_BOXED(90,16,FLEN)
NAN_BOXED(869,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(884,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(688,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(448,16,FLEN)
NAN_BOXED(81,16,FLEN)
NAN_BOXED(33871,16,FLEN)
NAN_BOXED(25,16,FLEN)
NAN_BOXED(33814,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(35,16,FLEN)
NAN_BOXED(33818,16,FLEN)
NAN_BOXED(91,16,FLEN)
NAN_BOXED(33866,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(33807,16,FLEN)
NAN_BOXED(43,16,FLEN)
NAN_BOXED(33770,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(33671,16,FLEN)
NAN_BOXED(19,16,FLEN)
NAN_BOXED(33554,16,FLEN)
NAN_BOXED(29,16,FLEN)
NAN_BOXED(33308,16,FLEN)
NAN_BOXED(1098,16,FLEN)
NAN_BOXED(32841,16,FLEN)
NAN_BOXED(1093,16,FLEN)
NAN_BOXED(32835,16,FLEN)
NAN_BOXED(1112,16,FLEN)
NAN_BOXED(32852,16,FLEN)
NAN_BOXED(1028,16,FLEN)
NAN_BOXED(4,16,FLEN)
NAN_BOXED(1106,16,FLEN)
NAN_BOXED(32834,16,FLEN)
NAN_BOXED(1102,16,FLEN)
NAN_BOXED(32814,16,FLEN)
NAN_BOXED(1040,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(1036,16,FLEN)
NAN_BOXED(116,16,FLEN)
NAN_BOXED(1039,16,FLEN)
NAN_BOXED(241,16,FLEN)
NAN_BOXED(1102,16,FLEN)
NAN_BOXED(434,16,FLEN)
NAN_BOXED(1049,16,FLEN)
NAN_BOXED(34829,16,FLEN)
NAN_BOXED(1116,16,FLEN)
NAN_BOXED(34863,16,FLEN)
NAN_BOXED(1086,16,FLEN)
NAN_BOXED(34849,16,FLEN)
NAN_BOXED(1118,16,FLEN)
NAN_BOXED(34867,16,FLEN)
NAN_BOXED(1111,16,FLEN)
NAN_BOXED(34867,16,FLEN)
NAN_BOXED(1094,16,FLEN)
NAN_BOXED(34867,16,FLEN)
NAN_BOXED(1104,16,FLEN)
NAN_BOXED(34888,16,FLEN)
NAN_BOXED(1058,16,FLEN)
NAN_BOXED(34897,16,FLEN)
NAN_BOXED(1053,16,FLEN)
NAN_BOXED(34958,16,FLEN)
NAN_BOXED(1107,16,FLEN)
NAN_BOXED(35113,16,FLEN)
NAN_BOXED(30765,16,FLEN)
NAN_BOXED(30626,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(30666,16,FLEN)
NAN_BOXED(30785,16,FLEN)
NAN_BOXED(30580,16,FLEN)
NAN_BOXED(30726,16,FLEN)
NAN_BOXED(30690,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(30660,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(30552,16,FLEN)
NAN_BOXED(30754,16,FLEN)
NAN_BOXED(30522,16,FLEN)
NAN_BOXED(30814,16,FLEN)
NAN_BOXED(30274,16,FLEN)
NAN_BOXED(30793,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30741,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30764,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30753,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30797,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30806,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30808,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(30793,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(50,16,FLEN)
NAN_BOXED(32816,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(32820,16,FLEN)
NAN_BOXED(34,16,FLEN)
NAN_BOXED(32798,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(32823,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x8_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x8_1:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x13_0:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 190*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
