
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 04:50:26 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b7 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b7)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x18,test_dataset_0)
RVTEST_SIGBASE(x9,signature_x9_1)

inst_0:
// rs1 == rd != rs2, rs1==x4, rs2==x7, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x4; op2:x7; dest:x4; op1val:0x7ba5; op2val:0x0;
   valaddr_reg:x18; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x4, x4, x7, dyn, 96, 0, x18, 0*FLEN/8, x21, x9, x10)

inst_1:
// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x8; op2:x8; dest:x8; op1val:0x6b3c; op2val:0x6b3c;
   valaddr_reg:x18; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x8, x8, x8, dyn, 96, 0, x18, 2*FLEN/8, x21, x9, x10)

inst_2:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x12, rs2==x23, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x12; op2:x23; dest:x19; op1val:0x7aae; op2val:0x0;
   valaddr_reg:x18; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x19, x12, x23, dyn, 96, 0, x18, 4*FLEN/8, x21, x9, x10)

inst_3:
// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x29; op2:x29; dest:x23; op1val:0x795a; op2val:0x795a;
   valaddr_reg:x18; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x23, x29, x29, dyn, 96, 0, x18, 6*FLEN/8, x21, x9, x10)

inst_4:
// rs2 == rd != rs1, rs1==x11, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x11; op2:x1; dest:x1; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x18; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x1, x11, x1, dyn, 96, 0, x18, 8*FLEN/8, x21, x9, x10)

inst_5:
// rs1==x5, rs2==x24, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x5; op2:x24; dest:x3; op1val:0x78a5; op2val:0x0;
   valaddr_reg:x18; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x3, x5, x24, dyn, 96, 0, x18, 10*FLEN/8, x21, x9, x10)

inst_6:
// rs1==x3, rs2==x26, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x3; op2:x26; dest:x16; op1val:0x76e3; op2val:0x0;
   valaddr_reg:x18; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x16, x3, x26, dyn, 96, 0, x18, 12*FLEN/8, x21, x9, x10)

inst_7:
// rs1==x23, rs2==x20, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x23; op2:x20; dest:x15; op1val:0x79c8; op2val:0x0;
   valaddr_reg:x18; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x15, x23, x20, dyn, 96, 0, x18, 14*FLEN/8, x21, x9, x10)

inst_8:
// rs1==x6, rs2==x31, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x6; op2:x31; dest:x26; op1val:0x7b97; op2val:0x0;
   valaddr_reg:x18; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x26, x6, x31, dyn, 96, 0, x18, 16*FLEN/8, x21, x9, x10)

inst_9:
// rs1==x2, rs2==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x2; op2:x22; dest:x12; op1val:0x771d; op2val:0x0;
   valaddr_reg:x18; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x12, x2, x22, dyn, 96, 0, x18, 18*FLEN/8, x21, x9, x10)

inst_10:
// rs1==x17, rs2==x0, rd==x29,fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x17; op2:x0; dest:x29; op1val:0x6899; op2val:0x0;
   valaddr_reg:x18; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x29, x17, x0, dyn, 96, 0, x18, 20*FLEN/8, x21, x9, x10)

inst_11:
// rs1==x24, rs2==x3, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x24; op2:x3; dest:x13; op1val:0x776f; op2val:0x0;
   valaddr_reg:x18; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x13, x24, x3, dyn, 96, 0, x18, 22*FLEN/8, x21, x9, x10)

inst_12:
// rs1==x14, rs2==x12, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x14; op2:x12; dest:x6; op1val:0x7613; op2val:0x0;
   valaddr_reg:x18; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x6, x14, x12, dyn, 96, 0, x18, 24*FLEN/8, x21, x9, x10)
RVTEST_VALBASEUPD(x4,test_dataset_1)

inst_13:
// rs1==x1, rs2==x17, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x1; op2:x17; dest:x18; op1val:0x7834; op2val:0x0;
   valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x18, x1, x17, dyn, 96, 0, x4, 0*FLEN/8, x6, x9, x10)

inst_14:
// rs1==x21, rs2==x11, rd==x27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x21; op2:x11; dest:x27; op1val:0x738d; op2val:0x0;
   valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10
*/
TEST_FPRR_OP(fmul.h, x27, x21, x11, dyn, 96, 0, x4, 2*FLEN/8, x6, x9, x10)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_15:
// rs1==x30, rs2==x19, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x19; dest:x17; op1val:0x7533; op2val:0x0;
   valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x17, x30, x19, dyn, 96, 0, x4, 4*FLEN/8, x6, x1, x3)

inst_16:
// rs1==x15, rs2==x16, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x15; op2:x16; dest:x10; op1val:0x7814; op2val:0x0;
   valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x10, x15, x16, dyn, 96, 0, x4, 6*FLEN/8, x6, x1, x3)

inst_17:
// rs1==x9, rs2==x21, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x9; op2:x21; dest:x31; op1val:0x7964; op2val:0x0;
   valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x31, x9, x21, dyn, 96, 0, x4, 8*FLEN/8, x6, x1, x3)

inst_18:
// rs1==x22, rs2==x30, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x22; op2:x30; dest:x0; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x0, x22, x30, dyn, 96, 0, x4, 10*FLEN/8, x6, x1, x3)

inst_19:
// rs1==x10, rs2==x27, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x10; op2:x27; dest:x28; op1val:0x79df; op2val:0x0;
   valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x28, x10, x27, dyn, 96, 0, x4, 12*FLEN/8, x6, x1, x3)

inst_20:
// rs1==x16, rs2==x18, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x16; op2:x18; dest:x25; op1val:0x7a19; op2val:0x0;
   valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x25, x16, x18, dyn, 96, 0, x4, 14*FLEN/8, x6, x1, x3)

inst_21:
// rs1==x7, rs2==x15, rd==x11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x7; op2:x15; dest:x11; op1val:0x75a8; op2val:0x0;
   valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x11, x7, x15, dyn, 96, 0, x4, 16*FLEN/8, x6, x1, x3)

inst_22:
// rs1==x27, rs2==x10, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x27; op2:x10; dest:x9; op1val:0x7bb1; op2val:0x0;
   valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x9, x27, x10, dyn, 96, 0, x4, 18*FLEN/8, x6, x1, x3)

inst_23:
// rs1==x18, rs2==x2, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x18; op2:x2; dest:x21; op1val:0x7a07; op2val:0x0;
   valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x21, x18, x2, dyn, 96, 0, x4, 20*FLEN/8, x6, x1, x3)

inst_24:
// rs1==x19, rs2==x14, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x19; op2:x14; dest:x24; op1val:0x7761; op2val:0x0;
   valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x24, x19, x14, dyn, 96, 0, x4, 22*FLEN/8, x6, x1, x3)

inst_25:
// rs1==x26, rs2==x9, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x26; op2:x9; dest:x22; op1val:0x77d6; op2val:0x0;
   valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x22, x26, x9, dyn, 96, 0, x4, 24*FLEN/8, x6, x1, x3)

inst_26:
// rs1==x0, rs2==x13, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x0; op2:x13; dest:x30; op1val:0x0; op2val:0x0;
   valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x30, x0, x13, dyn, 96, 0, x4, 26*FLEN/8, x6, x1, x3)

inst_27:
// rs1==x20, rs2==x28, rd==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x20; op2:x28; dest:x5; op1val:0x75a9; op2val:0x0;
   valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x5, x20, x28, dyn, 96, 0, x4, 28*FLEN/8, x6, x1, x3)
RVTEST_VALBASEUPD(x8,test_dataset_2)

inst_28:
// rs1==x31, rs2==x6, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x31; op2:x6; dest:x2; op1val:0x7b31; op2val:0x0;
   valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x2, x31, x6, dyn, 96, 0, x8, 0*FLEN/8, x9, x1, x3)

inst_29:
// rs1==x28, rs2==x4, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x28; op2:x4; dest:x7; op1val:0x788a; op2val:0x0;
   valaddr_reg:x8; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fmul.h, x7, x28, x4, dyn, 96, 0, x8, 2*FLEN/8, x9, x1, x3)

inst_30:
// rs1==x13, rs2==x5, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x13; op2:x5; dest:x14; op1val:0x79c9; op2val:0x0;
   valaddr_reg:x8; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x14, x13, x5, dyn, 96, 0, x8, 4*FLEN/8, x9, x1, x2)

inst_31:
// rs1==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x25; op2:x5; dest:x24; op1val:0x7318; op2val:0x0;
   valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x24, x25, x5, dyn, 96, 0, x8, 6*FLEN/8, x9, x1, x2)

inst_32:
// rs2==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x16; op2:x25; dest:x18; op1val:0x7998; op2val:0x0;
   valaddr_reg:x8; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x18, x16, x25, dyn, 96, 0, x8, 8*FLEN/8, x9, x1, x2)

inst_33:
// rd==x20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x16; op2:x28; dest:x20; op1val:0x7b42; op2val:0x0;
   valaddr_reg:x8; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x20, x16, x28, dyn, 96, 0, x8, 10*FLEN/8, x9, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x0;
   valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 12*FLEN/8, x9, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x0;
   valaddr_reg:x8; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 14*FLEN/8, x9, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x0;
   valaddr_reg:x8; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 16*FLEN/8, x9, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x0;
   valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 18*FLEN/8, x9, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x0;
   valaddr_reg:x8; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 20*FLEN/8, x9, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x0;
   valaddr_reg:x8; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 22*FLEN/8, x9, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x0;
   valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 24*FLEN/8, x9, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x0;
   valaddr_reg:x8; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 26*FLEN/8, x9, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x068 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x1468;
   valaddr_reg:x8; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 28*FLEN/8, x9, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x15f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x155f;
   valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 30*FLEN/8, x9, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x221 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7938; op2val:0x1621;
   valaddr_reg:x8; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 32*FLEN/8, x9, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x07 and fm2 == 0x06a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x733f; op2val:0x1c6a;
   valaddr_reg:x8; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 34*FLEN/8, x9, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x08 and fm2 == 0x0b4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ecc; op2val:0x20b4;
   valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 36*FLEN/8, x9, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad4; op2val:0x14af;
   valaddr_reg:x8; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 38*FLEN/8, x9, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0c0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x72bb; op2val:0x1cc0;
   valaddr_reg:x8; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 40*FLEN/8, x9, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76c3; op2val:0x12;
   valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 42*FLEN/8, x9, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6814; op2val:0xfb;
   valaddr_reg:x8; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 44*FLEN/8, x9, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x717f; op2val:0x2e;
   valaddr_reg:x8; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 46*FLEN/8, x9, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x060 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d4d; op2val:0x60;
   valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 48*FLEN/8, x9, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x13b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x667d; op2val:0x13b;
   valaddr_reg:x8; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 50*FLEN/8, x9, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x656a; op2val:0x17a;
   valaddr_reg:x8; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 52*FLEN/8, x9, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a80; op2val:0x9;
   valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 54*FLEN/8, x9, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b3c; op2val:0x0;
   valaddr_reg:x8; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 56*FLEN/8, x9, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x795a; op2val:0x0;
   valaddr_reg:x8; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 58*FLEN/8, x9, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0;
   valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 60*FLEN/8, x9, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x8; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 62*FLEN/8, x9, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x0;
   valaddr_reg:x8; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x8, 64*FLEN/8, x9, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(30936,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30885,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30435,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31176,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31639,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30493,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(26777,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30575,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30227,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(30772,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(29581,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30003,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30740,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31076,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31525,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31199,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31257,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30120,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31665,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31239,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30561,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30678,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30121,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_2:
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(5224,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(5471,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(5665,16,FLEN)
NAN_BOXED(29503,16,FLEN)
NAN_BOXED(7274,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(8372,16,FLEN)
NAN_BOXED(31444,16,FLEN)
NAN_BOXED(5295,16,FLEN)
NAN_BOXED(29371,16,FLEN)
NAN_BOXED(7360,16,FLEN)
NAN_BOXED(30403,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(26644,16,FLEN)
NAN_BOXED(251,16,FLEN)
NAN_BOXED(29055,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(27981,16,FLEN)
NAN_BOXED(96,16,FLEN)
NAN_BOXED(26237,16,FLEN)
NAN_BOXED(315,16,FLEN)
NAN_BOXED(25962,16,FLEN)
NAN_BOXED(378,16,FLEN)
NAN_BOXED(31360,16,FLEN)
NAN_BOXED(9,16,FLEN)
NAN_BOXED(27452,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x9_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_1:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 40*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 52*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
