
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Sun Aug  7 18:12:45 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/anku/work2/bcrypto/64/dataset.yaml \
//                  --cgf /home/anku/work2/bcrypto/64/rv64ik.yaml \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sha512sum0 instruction of the RISC-V RV64Zk,RV64Zkn,RV64Zknh extension for the sha512sum0 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IZk,RV64IZkn,RV64IZknh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*Zk.*);def TEST_CASE_1=True;",sha512sum0)

RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*Zkn.*);def TEST_CASE_1=True;",sha512sum0)

RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*Zknh.*);def TEST_CASE_1=True;",sha512sum0)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 != rd, rs1==x30, rd==x31, 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x75a3adb3254a9493;
LI(x30,0x75a3adb3254a9493)
sha512sum0 x31, x30
SREG x31, 0(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000000000000)

inst_1:
// rs1 == rd, rs1==x29, rd==x29, 
// opcode: sha512sum0 ; op1:x29; dest:x29; op1val:0x7fffffffffffffff;
LI(x29,0x7fffffffffffffff)
sha512sum0 x29, x29
SREG x29, 8(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x29, 0x0000000000000000)

inst_2:
// rs1==x31, rd==x30, 
// opcode: sha512sum0 ; op1:x31; dest:x30; op1val:0xbfffffffffffffff;
LI(x31,0xbfffffffffffffff)
sha512sum0 x30, x31
SREG x30, 16(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x30, 0x0000000000000000)

inst_3:
// rs1==x27, rd==x28, 
// opcode: sha512sum0 ; op1:x27; dest:x28; op1val:0xdfffffffffffffff;
LI(x27,0xdfffffffffffffff)
sha512sum0 x28, x27
SREG x28, 24(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x28, 0x0000000000000000)

inst_4:
// rs1==x28, rd==x27, 
// opcode: sha512sum0 ; op1:x28; dest:x27; op1val:0xefffffffffffffff;
LI(x28,0xefffffffffffffff)
sha512sum0 x27, x28
SREG x27, 32(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x27, 0x0000000000000000)

inst_5:
// rs1==x25, rd==x26, 
// opcode: sha512sum0 ; op1:x25; dest:x26; op1val:0xf7ffffffffffffff;
LI(x25,0xf7ffffffffffffff)
sha512sum0 x26, x25
SREG x26, 40(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x26, 0x0000000000000000)

inst_6:
// rs1==x26, rd==x25, 
// opcode: sha512sum0 ; op1:x26; dest:x25; op1val:0xfbffffffffffffff;
LI(x26,0xfbffffffffffffff)
sha512sum0 x25, x26
SREG x25, 48(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x25, 0x0000000000000000)

inst_7:
// rs1==x23, rd==x24, 
// opcode: sha512sum0 ; op1:x23; dest:x24; op1val:0xfdffffffffffffff;
LI(x23,0xfdffffffffffffff)
sha512sum0 x24, x23
SREG x24, 56(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x24, 0x0000000000000000)

inst_8:
// rs1==x24, rd==x23, 
// opcode: sha512sum0 ; op1:x24; dest:x23; op1val:0xfeffffffffffffff;
LI(x24,0xfeffffffffffffff)
sha512sum0 x23, x24
SREG x23, 64(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x23, 0x0000000000000000)

inst_9:
// rs1==x21, rd==x22, 
// opcode: sha512sum0 ; op1:x21; dest:x22; op1val:0xff7fffffffffffff;
LI(x21,0xff7fffffffffffff)
sha512sum0 x22, x21
SREG x22, 72(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x22, 0x0000000000000000)

inst_10:
// rs1==x22, rd==x21, 
// opcode: sha512sum0 ; op1:x22; dest:x21; op1val:0xffbfffffffffffff;
LI(x22,0xffbfffffffffffff)
sha512sum0 x21, x22
SREG x21, 80(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x21, 0x0000000000000000)

inst_11:
// rs1==x19, rd==x20, 
// opcode: sha512sum0 ; op1:x19; dest:x20; op1val:0xffdfffffffffffff;
LI(x19,0xffdfffffffffffff)
sha512sum0 x20, x19
SREG x20, 88(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x20, 0x0000000000000000)

inst_12:
// rs1==x20, rd==x19, 
// opcode: sha512sum0 ; op1:x20; dest:x19; op1val:0xffefffffffffffff;
LI(x20,0xffefffffffffffff)
sha512sum0 x19, x20
SREG x19, 96(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x19, 0x0000000000000000)

inst_13:
// rs1==x17, rd==x18, 
// opcode: sha512sum0 ; op1:x17; dest:x18; op1val:0xfff7ffffffffffff;
LI(x17,0xfff7ffffffffffff)
sha512sum0 x18, x17
SREG x18, 104(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x18, 0x0000000000000000)

inst_14:
// rs1==x18, rd==x17, 
// opcode: sha512sum0 ; op1:x18; dest:x17; op1val:0xfffbffffffffffff;
LI(x18,0xfffbffffffffffff)
sha512sum0 x17, x18
SREG x17, 112(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x17, 0x0000000000000000)

inst_15:
// rs1==x15, rd==x16, 
// opcode: sha512sum0 ; op1:x15; dest:x16; op1val:0xfffdffffffffffff;
LI(x15,0xfffdffffffffffff)
sha512sum0 x16, x15
SREG x16, 120(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x16, 0x0000000000000000)

inst_16:
// rs1==x16, rd==x15, 
// opcode: sha512sum0 ; op1:x16; dest:x15; op1val:0xfffeffffffffffff;
LI(x16,0xfffeffffffffffff)
sha512sum0 x15, x16
SREG x15, 128(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x15, 0x0000000000000000)

inst_17:
// rs1==x13, rd==x14, 
// opcode: sha512sum0 ; op1:x13; dest:x14; op1val:0xffff7fffffffffff;
LI(x13,0xffff7fffffffffff)
sha512sum0 x14, x13
SREG x14, 136(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x14, 0x0000000000000000)

inst_18:
// rs1==x14, rd==x13, 
// opcode: sha512sum0 ; op1:x14; dest:x13; op1val:0xffffbfffffffffff;
LI(x14,0xffffbfffffffffff)
sha512sum0 x13, x14
SREG x13, 144(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x13, 0x0000000000000000)

inst_19:
// rs1==x11, rd==x12, 
// opcode: sha512sum0 ; op1:x11; dest:x12; op1val:0xffffdfffffffffff;
LI(x11,0xffffdfffffffffff)
sha512sum0 x12, x11
SREG x12, 152(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x12, 0x0000000000000000)

inst_20:
// rs1==x12, rd==x11, 
// opcode: sha512sum0 ; op1:x12; dest:x11; op1val:0xffffefffffffffff;
LI(x12,0xffffefffffffffff)
sha512sum0 x11, x12
SREG x11, 160(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)

inst_21:
// rs1==x9, rd==x10, 
// opcode: sha512sum0 ; op1:x9; dest:x10; op1val:0xfffff7ffffffffff;
LI(x9,0xfffff7ffffffffff)
sha512sum0 x10, x9
SREG x10, 168(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x10, 0x0000000000000000)

inst_22:
// rs1==x10, rd==x9, 
// opcode: sha512sum0 ; op1:x10; dest:x9; op1val:0xfffffbffffffffff;
LI(x10,0xfffffbffffffffff)
sha512sum0 x9, x10
SREG x9, 176(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x9, 0x0000000000000000)

inst_23:
// rs1==x7, rd==x8, 
// opcode: sha512sum0 ; op1:x7; dest:x8; op1val:0xfffffdffffffffff;
LI(x7,0xfffffdffffffffff)
sha512sum0 x8, x7
SREG x8, 184(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x8, 0x0000000000000000)

inst_24:
// rs1==x8, rd==x7, 
// opcode: sha512sum0 ; op1:x8; dest:x7; op1val:0xfffffeffffffffff;
LI(x8,0xfffffeffffffffff)
sha512sum0 x7, x8
SREG x7, 192(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x7, 0x0000000000000000)

inst_25:
// rs1==x5, rd==x6, 
// opcode: sha512sum0 ; op1:x5; dest:x6; op1val:0xffffff7fffffffff;
LI(x5,0xffffff7fffffffff)
sha512sum0 x6, x5
SREG x6, 200(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x6, 0x0000000000000000)

inst_26:
// rs1==x6, rd==x5, 
// opcode: sha512sum0 ; op1:x6; dest:x5; op1val:0xffffffbfffffffff;
LI(x6,0xffffffbfffffffff)
sha512sum0 x5, x6
SREG x5, 208(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x5, 0x0000000000000000)

inst_27:
// rs1==x3, rd==x4, 
// opcode: sha512sum0 ; op1:x3; dest:x4; op1val:0xffffffdfffffffff;
LI(x3,0xffffffdfffffffff)
sha512sum0 x4, x3
SREG x4, 216(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x4, 0x0000000000000000)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_28:
// rs1==x4, rd==x3, 
// opcode: sha512sum0 ; op1:x4; dest:x3; op1val:0xffffffefffffffff;
LI(x4,0xffffffefffffffff)
sha512sum0 x3, x4
SREG x3, 0(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x3, 0x0000000000000000)

inst_29:
// rs1==x1, rd==x2, 
// opcode: sha512sum0 ; op1:x1; dest:x2; op1val:0xfffffff7ffffffff;
LI(x1,0xfffffff7ffffffff)
sha512sum0 x2, x1
SREG x2, 8(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x2, 0x0000000000000000)

inst_30:
// rs1==x2, rd==x1, 
// opcode: sha512sum0 ; op1:x2; dest:x1; op1val:0xfffffffbffffffff;
LI(x2,0xfffffffbffffffff)
sha512sum0 x1, x2
SREG x1, 16(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x1, 0x0000000000000000)

inst_31:
// rs1==x0, 
// opcode: sha512sum0 ; op1:x0; dest:x31; op1val:0x0;
LI(x0,0x0)
sha512sum0 x31, x0
SREG x31, 24(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_32:
// rd==x0, 
// opcode: sha512sum0 ; op1:x31; dest:x0; op1val:0xfffffffeffffffff;
LI(x31,0xfffffffeffffffff)
sha512sum0 x0, x31
SREG x0, 32(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x0, 0x0000000000000000)

inst_33:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffff7fffffff;
LI(x30,0xffffffff7fffffff)
sha512sum0 x31, x30
SREG x31, 40(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_34:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffbfffffff;
LI(x30,0xffffffffbfffffff)
sha512sum0 x31, x30
SREG x31, 48(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_35:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffdfffffff;
LI(x30,0xffffffffdfffffff)
sha512sum0 x31, x30
SREG x31, 56(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_36:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffefffffff;
LI(x30,0xffffffffefffffff)
sha512sum0 x31, x30
SREG x31, 64(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_37:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffff7ffffff;
LI(x30,0xfffffffff7ffffff)
sha512sum0 x31, x30
SREG x31, 72(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_38:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffbffffff;
LI(x30,0xfffffffffbffffff)
sha512sum0 x31, x30
SREG x31, 80(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_39:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffdffffff;
LI(x30,0xfffffffffdffffff)
sha512sum0 x31, x30
SREG x31, 88(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_40:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffeffffff;
LI(x30,0xfffffffffeffffff)
sha512sum0 x31, x30
SREG x31, 96(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_41:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffff7fffff;
LI(x30,0xffffffffff7fffff)
sha512sum0 x31, x30
SREG x31, 104(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_42:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffbfffff;
LI(x30,0xffffffffffbfffff)
sha512sum0 x31, x30
SREG x31, 112(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_43:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffdfffff;
LI(x30,0xffffffffffdfffff)
sha512sum0 x31, x30
SREG x31, 120(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_44:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffefffff;
LI(x30,0xffffffffffefffff)
sha512sum0 x31, x30
SREG x31, 128(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_45:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffff7ffff;
LI(x30,0xfffffffffff7ffff)
sha512sum0 x31, x30
SREG x31, 136(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_46:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffbffff;
LI(x30,0xfffffffffffbffff)
sha512sum0 x31, x30
SREG x31, 144(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_47:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffdffff;
LI(x30,0xfffffffffffdffff)
sha512sum0 x31, x30
SREG x31, 152(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_48:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffeffff;
LI(x30,0xfffffffffffeffff)
sha512sum0 x31, x30
SREG x31, 160(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_49:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffff7fff;
LI(x30,0xffffffffffff7fff)
sha512sum0 x31, x30
SREG x31, 168(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_50:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffbfff;
LI(x30,0xffffffffffffbfff)
sha512sum0 x31, x30
SREG x31, 176(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_51:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffdfff;
LI(x30,0xffffffffffffdfff)
sha512sum0 x31, x30
SREG x31, 184(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_52:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffefff;
LI(x30,0xffffffffffffefff)
sha512sum0 x31, x30
SREG x31, 192(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_53:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffff7ff;
LI(x30,0xfffffffffffff7ff)
sha512sum0 x31, x30
SREG x31, 200(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_54:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffbff;
LI(x30,0xfffffffffffffbff)
sha512sum0 x31, x30
SREG x31, 208(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_55:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffdff;
LI(x30,0xfffffffffffffdff)
sha512sum0 x31, x30
SREG x31, 216(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_56:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffeff;
LI(x30,0xfffffffffffffeff)
sha512sum0 x31, x30
SREG x31, 224(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_57:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffff7f;
LI(x30,0xffffffffffffff7f)
sha512sum0 x31, x30
SREG x31, 232(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_58:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffffbf;
LI(x30,0xffffffffffffffbf)
sha512sum0 x31, x30
SREG x31, 240(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_59:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffffdf;
LI(x30,0xffffffffffffffdf)
sha512sum0 x31, x30
SREG x31, 248(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_60:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xffffffffffffffef;
LI(x30,0xffffffffffffffef)
sha512sum0 x31, x30
SREG x31, 256(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_61:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffff7;
LI(x30,0xfffffffffffffff7)
sha512sum0 x31, x30
SREG x31, 264(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_62:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffffb;
LI(x30,0xfffffffffffffffb)
sha512sum0 x31, x30
SREG x31, 272(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_63:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffffd;
LI(x30,0xfffffffffffffffd)
sha512sum0 x31, x30
SREG x31, 280(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_64:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffffffffffe;
LI(x30,0xfffffffffffffffe)
sha512sum0 x31, x30
SREG x31, 288(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_65:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x8000000000000000;
LI(x30,0x8000000000000000)
sha512sum0 x31, x30
SREG x31, 296(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_66:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x4000000000000000;
LI(x30,0x4000000000000000)
sha512sum0 x31, x30
SREG x31, 304(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_67:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2000000000000000;
LI(x30,0x2000000000000000)
sha512sum0 x31, x30
SREG x31, 312(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_68:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1000000000000000;
LI(x30,0x1000000000000000)
sha512sum0 x31, x30
SREG x31, 320(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_69:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x800000000000000;
LI(x30,0x800000000000000)
sha512sum0 x31, x30
SREG x31, 328(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_70:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x400000000000000;
LI(x30,0x400000000000000)
sha512sum0 x31, x30
SREG x31, 336(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_71:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x200000000000000;
LI(x30,0x200000000000000)
sha512sum0 x31, x30
SREG x31, 344(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_72:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x100000000000000;
LI(x30,0x100000000000000)
sha512sum0 x31, x30
SREG x31, 352(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_73:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x80000000000000;
LI(x30,0x80000000000000)
sha512sum0 x31, x30
SREG x31, 360(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_74:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x40000000000000;
LI(x30,0x40000000000000)
sha512sum0 x31, x30
SREG x31, 368(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_75:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x20000000000000;
LI(x30,0x20000000000000)
sha512sum0 x31, x30
SREG x31, 376(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_76:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x10000000000000;
LI(x30,0x10000000000000)
sha512sum0 x31, x30
SREG x31, 384(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_77:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x8000000000000;
LI(x30,0x8000000000000)
sha512sum0 x31, x30
SREG x31, 392(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_78:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x4000000000000;
LI(x30,0x4000000000000)
sha512sum0 x31, x30
SREG x31, 400(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_79:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2000000000000;
LI(x30,0x2000000000000)
sha512sum0 x31, x30
SREG x31, 408(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_80:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1000000000000;
LI(x30,0x1000000000000)
sha512sum0 x31, x30
SREG x31, 416(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_81:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x800000000000;
LI(x30,0x800000000000)
sha512sum0 x31, x30
SREG x31, 424(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_82:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x400000000000;
LI(x30,0x400000000000)
sha512sum0 x31, x30
SREG x31, 432(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_83:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x200000000000;
LI(x30,0x200000000000)
sha512sum0 x31, x30
SREG x31, 440(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_84:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x100000000000;
LI(x30,0x100000000000)
sha512sum0 x31, x30
SREG x31, 448(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_85:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1;
LI(x30,0x1)
sha512sum0 x31, x30
SREG x31, 456(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_86:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xb6f9706fb4f741aa;
LI(x30,0xb6f9706fb4f741aa)
sha512sum0 x31, x30
SREG x31, 464(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_87:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x40a5ff526f38a9c7;
LI(x30,0x40a5ff526f38a9c7)
sha512sum0 x31, x30
SREG x31, 472(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_88:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xd05668ae0fdb82bc;
LI(x30,0xd05668ae0fdb82bc)
sha512sum0 x31, x30
SREG x31, 480(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_89:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x9bedfe390d6ddd9d;
LI(x30,0x9bedfe390d6ddd9d)
sha512sum0 x31, x30
SREG x31, 488(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_90:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xaa6bb2bde9ed477d;
LI(x30,0xaa6bb2bde9ed477d)
sha512sum0 x31, x30
SREG x31, 496(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_91:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xd75739f82ac177c6;
LI(x30,0xd75739f82ac177c6)
sha512sum0 x31, x30
SREG x31, 504(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_92:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x299c3bcf90efb625;
LI(x30,0x299c3bcf90efb625)
sha512sum0 x31, x30
SREG x31, 512(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_93:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x9a4e9ef10171f4df;
LI(x30,0x9a4e9ef10171f4df)
sha512sum0 x31, x30
SREG x31, 520(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_94:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1fc493caa371db42;
LI(x30,0x1fc493caa371db42)
sha512sum0 x31, x30
SREG x31, 528(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_95:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xd169a3f8cad5e297;
LI(x30,0xd169a3f8cad5e297)
sha512sum0 x31, x30
SREG x31, 536(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_96:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xf4c30307672f666d;
LI(x30,0xf4c30307672f666d)
sha512sum0 x31, x30
SREG x31, 544(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_97:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xd5b9fe5cf69bdcf3;
LI(x30,0xd5b9fe5cf69bdcf3)
sha512sum0 x31, x30
SREG x31, 552(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_98:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xa0569d765ebc64cb;
LI(x30,0xa0569d765ebc64cb)
sha512sum0 x31, x30
SREG x31, 560(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_99:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xe4921bf73047c198;
LI(x30,0xe4921bf73047c198)
sha512sum0 x31, x30
SREG x31, 568(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_100:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2daf9ac7f5faf207;
LI(x30,0x2daf9ac7f5faf207)
sha512sum0 x31, x30
SREG x31, 576(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_101:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfcc1b543c49cd65b;
LI(x30,0xfcc1b543c49cd65b)
sha512sum0 x31, x30
SREG x31, 584(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_102:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x3459294ef273b44c;
LI(x30,0x3459294ef273b44c)
sha512sum0 x31, x30
SREG x31, 592(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_103:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x436f40f274b8de87;
LI(x30,0x436f40f274b8de87)
sha512sum0 x31, x30
SREG x31, 600(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_104:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xc5521660f3a3c571;
LI(x30,0xc5521660f3a3c571)
sha512sum0 x31, x30
SREG x31, 608(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_105:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x80000000000;
LI(x30,0x80000000000)
sha512sum0 x31, x30
SREG x31, 616(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_106:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x40000000000;
LI(x30,0x40000000000)
sha512sum0 x31, x30
SREG x31, 624(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_107:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x20000000000;
LI(x30,0x20000000000)
sha512sum0 x31, x30
SREG x31, 632(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_108:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x10000000000;
LI(x30,0x10000000000)
sha512sum0 x31, x30
SREG x31, 640(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_109:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x8000000000;
LI(x30,0x8000000000)
sha512sum0 x31, x30
SREG x31, 648(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_110:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x4000000000;
LI(x30,0x4000000000)
sha512sum0 x31, x30
SREG x31, 656(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_111:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2000000000;
LI(x30,0x2000000000)
sha512sum0 x31, x30
SREG x31, 664(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_112:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1000000000;
LI(x30,0x1000000000)
sha512sum0 x31, x30
SREG x31, 672(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_113:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x800000000;
LI(x30,0x800000000)
sha512sum0 x31, x30
SREG x31, 680(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_114:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x400000000;
LI(x30,0x400000000)
sha512sum0 x31, x30
SREG x31, 688(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_115:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x200000000;
LI(x30,0x200000000)
sha512sum0 x31, x30
SREG x31, 696(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_116:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x100000000;
LI(x30,0x100000000)
sha512sum0 x31, x30
SREG x31, 704(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_117:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x80000000;
LI(x30,0x80000000)
sha512sum0 x31, x30
SREG x31, 712(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_118:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x40000000;
LI(x30,0x40000000)
sha512sum0 x31, x30
SREG x31, 720(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_119:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x20000000;
LI(x30,0x20000000)
sha512sum0 x31, x30
SREG x31, 728(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_120:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x10000000;
LI(x30,0x10000000)
sha512sum0 x31, x30
SREG x31, 736(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_121:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x8000000;
LI(x30,0x8000000)
sha512sum0 x31, x30
SREG x31, 744(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_122:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x4000000;
LI(x30,0x4000000)
sha512sum0 x31, x30
SREG x31, 752(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_123:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2000000;
LI(x30,0x2000000)
sha512sum0 x31, x30
SREG x31, 760(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_124:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1000000;
LI(x30,0x1000000)
sha512sum0 x31, x30
SREG x31, 768(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_125:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x800000;
LI(x30,0x800000)
sha512sum0 x31, x30
SREG x31, 776(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_126:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x400000;
LI(x30,0x400000)
sha512sum0 x31, x30
SREG x31, 784(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_127:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x200000;
LI(x30,0x200000)
sha512sum0 x31, x30
SREG x31, 792(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_128:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x100000;
LI(x30,0x100000)
sha512sum0 x31, x30
SREG x31, 800(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_129:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x80000;
LI(x30,0x80000)
sha512sum0 x31, x30
SREG x31, 808(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_130:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x40000;
LI(x30,0x40000)
sha512sum0 x31, x30
SREG x31, 816(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_131:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x20000;
LI(x30,0x20000)
sha512sum0 x31, x30
SREG x31, 824(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_132:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x10000;
LI(x30,0x10000)
sha512sum0 x31, x30
SREG x31, 832(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_133:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x8000;
LI(x30,0x8000)
sha512sum0 x31, x30
SREG x31, 840(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_134:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x4000;
LI(x30,0x4000)
sha512sum0 x31, x30
SREG x31, 848(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_135:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2000;
LI(x30,0x2000)
sha512sum0 x31, x30
SREG x31, 856(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_136:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x1000;
LI(x30,0x1000)
sha512sum0 x31, x30
SREG x31, 864(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_137:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x800;
LI(x30,0x800)
sha512sum0 x31, x30
SREG x31, 872(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_138:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x400;
LI(x30,0x400)
sha512sum0 x31, x30
SREG x31, 880(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_139:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x200;
LI(x30,0x200)
sha512sum0 x31, x30
SREG x31, 888(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_140:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x100;
LI(x30,0x100)
sha512sum0 x31, x30
SREG x31, 896(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_141:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x80;
LI(x30,0x80)
sha512sum0 x31, x30
SREG x31, 904(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_142:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x40;
LI(x30,0x40)
sha512sum0 x31, x30
SREG x31, 912(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_143:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x20;
LI(x30,0x20)
sha512sum0 x31, x30
SREG x31, 920(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_144:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x10;
LI(x30,0x10)
sha512sum0 x31, x30
SREG x31, 928(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_145:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x8;
LI(x30,0x8)
sha512sum0 x31, x30
SREG x31, 936(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_146:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x4;
LI(x30,0x4)
sha512sum0 x31, x30
SREG x31, 944(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_147:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0x2;
LI(x30,0x2)
sha512sum0 x31, x30
SREG x31, 952(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_148:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffdffffffff;
LI(x30,0xfffffffdffffffff)
sha512sum0 x31, x30
SREG x31, 960(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)

inst_149:
// 
// opcode: sha512sum0 ; op1:x30; dest:x31; op1val:0xfffffffeffffffff;
LI(x30,0xfffffffeffffffff)
sha512sum0 x31, x30
SREG x31, 968(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x0000000000000000)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 28*(XLEN/32),4,0xdeadbeef


signature_x5_0:
    .fill 122*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
