
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:45:11 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmsub_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmsub_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_11505:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:34515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34515*FLEN/8, x4, x1, x2)

inst_11506:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:34518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34518*FLEN/8, x4, x1, x2)

inst_11507:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:34521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34521*FLEN/8, x4, x1, x2)

inst_11508:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:34524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34524*FLEN/8, x4, x1, x2)

inst_11509:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:34527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34527*FLEN/8, x4, x1, x2)

inst_11510:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:34530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34530*FLEN/8, x4, x1, x2)

inst_11511:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:34533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34533*FLEN/8, x4, x1, x2)

inst_11512:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:34536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34536*FLEN/8, x4, x1, x2)

inst_11513:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:34539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34539*FLEN/8, x4, x1, x2)

inst_11514:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:34542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34542*FLEN/8, x4, x1, x2)

inst_11515:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:34545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34545*FLEN/8, x4, x1, x2)

inst_11516:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:34548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34548*FLEN/8, x4, x1, x2)

inst_11517:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:34551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34551*FLEN/8, x4, x1, x2)

inst_11518:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:34554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34554*FLEN/8, x4, x1, x2)

inst_11519:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfe55; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:34557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34557*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_91)
inst_11520:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:34560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34560*FLEN/8, x4, x1, x2)

inst_11521:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:34563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34563*FLEN/8, x4, x1, x2)

inst_11522:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:34566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34566*FLEN/8, x4, x1, x2)

inst_11523:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:34569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34569*FLEN/8, x4, x1, x2)

inst_11524:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:34572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34572*FLEN/8, x4, x1, x2)

inst_11525:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:34575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34575*FLEN/8, x4, x1, x2)

inst_11526:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:34578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34578*FLEN/8, x4, x1, x2)

inst_11527:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:34581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34581*FLEN/8, x4, x1, x2)

inst_11528:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:34584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34584*FLEN/8, x4, x1, x2)

inst_11529:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:34587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34587*FLEN/8, x4, x1, x2)

inst_11530:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:34590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34590*FLEN/8, x4, x1, x2)

inst_11531:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:34593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34593*FLEN/8, x4, x1, x2)

inst_11532:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:34596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34596*FLEN/8, x4, x1, x2)

inst_11533:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:34599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34599*FLEN/8, x4, x1, x2)

inst_11534:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:34602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34602*FLEN/8, x4, x1, x2)

inst_11535:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:34605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34605*FLEN/8, x4, x1, x2)

inst_11536:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:34608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34608*FLEN/8, x4, x1, x2)

inst_11537:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:34611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34611*FLEN/8, x4, x1, x2)

inst_11538:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:34614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34614*FLEN/8, x4, x1, x2)

inst_11539:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:34617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34617*FLEN/8, x4, x1, x2)

inst_11540:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:34620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34620*FLEN/8, x4, x1, x2)

inst_11541:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:34623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34623*FLEN/8, x4, x1, x2)

inst_11542:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:34626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34626*FLEN/8, x4, x1, x2)

inst_11543:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:34629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34629*FLEN/8, x4, x1, x2)

inst_11544:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:34632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34632*FLEN/8, x4, x1, x2)

inst_11545:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:34635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34635*FLEN/8, x4, x1, x2)

inst_11546:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:34638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34638*FLEN/8, x4, x1, x2)

inst_11547:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:34641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34641*FLEN/8, x4, x1, x2)

inst_11548:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:34644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34644*FLEN/8, x4, x1, x2)

inst_11549:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:34647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34647*FLEN/8, x4, x1, x2)

inst_11550:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:34650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34650*FLEN/8, x4, x1, x2)

inst_11551:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:34653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34653*FLEN/8, x4, x1, x2)

inst_11552:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:34656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34656*FLEN/8, x4, x1, x2)

inst_11553:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:34659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34659*FLEN/8, x4, x1, x2)

inst_11554:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:34662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34662*FLEN/8, x4, x1, x2)

inst_11555:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:34665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34665*FLEN/8, x4, x1, x2)

inst_11556:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:34668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34668*FLEN/8, x4, x1, x2)

inst_11557:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:34671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34671*FLEN/8, x4, x1, x2)

inst_11558:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:34674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34674*FLEN/8, x4, x1, x2)

inst_11559:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:34677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34677*FLEN/8, x4, x1, x2)

inst_11560:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:34680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34680*FLEN/8, x4, x1, x2)

inst_11561:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:34683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34683*FLEN/8, x4, x1, x2)

inst_11562:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:34686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34686*FLEN/8, x4, x1, x2)

inst_11563:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:34689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34689*FLEN/8, x4, x1, x2)

inst_11564:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:34692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34692*FLEN/8, x4, x1, x2)

inst_11565:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:34695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34695*FLEN/8, x4, x1, x2)

inst_11566:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:34698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34698*FLEN/8, x4, x1, x2)

inst_11567:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:34701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34701*FLEN/8, x4, x1, x2)

inst_11568:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:34704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34704*FLEN/8, x4, x1, x2)

inst_11569:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:34707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34707*FLEN/8, x4, x1, x2)

inst_11570:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:34710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34710*FLEN/8, x4, x1, x2)

inst_11571:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:34713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34713*FLEN/8, x4, x1, x2)

inst_11572:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:34716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34716*FLEN/8, x4, x1, x2)

inst_11573:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:34719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34719*FLEN/8, x4, x1, x2)

inst_11574:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:34722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34722*FLEN/8, x4, x1, x2)

inst_11575:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:34725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34725*FLEN/8, x4, x1, x2)

inst_11576:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:34728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34728*FLEN/8, x4, x1, x2)

inst_11577:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:34731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34731*FLEN/8, x4, x1, x2)

inst_11578:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:34734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34734*FLEN/8, x4, x1, x2)

inst_11579:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:34737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34737*FLEN/8, x4, x1, x2)

inst_11580:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:34740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34740*FLEN/8, x4, x1, x2)

inst_11581:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:34743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34743*FLEN/8, x4, x1, x2)

inst_11582:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:34746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34746*FLEN/8, x4, x1, x2)

inst_11583:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:34749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34749*FLEN/8, x4, x1, x2)

inst_11584:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:34752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34752*FLEN/8, x4, x1, x2)

inst_11585:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:34755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34755*FLEN/8, x4, x1, x2)

inst_11586:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:34758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34758*FLEN/8, x4, x1, x2)

inst_11587:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:34761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34761*FLEN/8, x4, x1, x2)

inst_11588:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:34764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34764*FLEN/8, x4, x1, x2)

inst_11589:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:34767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34767*FLEN/8, x4, x1, x2)

inst_11590:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:34770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34770*FLEN/8, x4, x1, x2)

inst_11591:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:34773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34773*FLEN/8, x4, x1, x2)

inst_11592:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:34776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34776*FLEN/8, x4, x1, x2)

inst_11593:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:34779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34779*FLEN/8, x4, x1, x2)

inst_11594:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:34782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34782*FLEN/8, x4, x1, x2)

inst_11595:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:34785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34785*FLEN/8, x4, x1, x2)

inst_11596:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:34788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34788*FLEN/8, x4, x1, x2)

inst_11597:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:34791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34791*FLEN/8, x4, x1, x2)

inst_11598:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:34794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34794*FLEN/8, x4, x1, x2)

inst_11599:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:34797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34797*FLEN/8, x4, x1, x2)

inst_11600:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:34800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34800*FLEN/8, x4, x1, x2)

inst_11601:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:34803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34803*FLEN/8, x4, x1, x2)

inst_11602:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:34806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34806*FLEN/8, x4, x1, x2)

inst_11603:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:34809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34809*FLEN/8, x4, x1, x2)

inst_11604:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:34812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34812*FLEN/8, x4, x1, x2)

inst_11605:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:34815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34815*FLEN/8, x4, x1, x2)

inst_11606:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:34818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34818*FLEN/8, x4, x1, x2)

inst_11607:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:34821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34821*FLEN/8, x4, x1, x2)

inst_11608:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:34824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34824*FLEN/8, x4, x1, x2)

inst_11609:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:34827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34827*FLEN/8, x4, x1, x2)

inst_11610:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:34830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34830*FLEN/8, x4, x1, x2)

inst_11611:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:34833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34833*FLEN/8, x4, x1, x2)

inst_11612:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:34836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34836*FLEN/8, x4, x1, x2)

inst_11613:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:34839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34839*FLEN/8, x4, x1, x2)

inst_11614:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:34842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34842*FLEN/8, x4, x1, x2)

inst_11615:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:34845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34845*FLEN/8, x4, x1, x2)

inst_11616:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:34848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34848*FLEN/8, x4, x1, x2)

inst_11617:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:34851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34851*FLEN/8, x4, x1, x2)

inst_11618:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:34854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34854*FLEN/8, x4, x1, x2)

inst_11619:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:34857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34857*FLEN/8, x4, x1, x2)

inst_11620:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:34860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34860*FLEN/8, x4, x1, x2)

inst_11621:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:34863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34863*FLEN/8, x4, x1, x2)

inst_11622:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:34866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34866*FLEN/8, x4, x1, x2)

inst_11623:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:34869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34869*FLEN/8, x4, x1, x2)

inst_11624:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:34872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34872*FLEN/8, x4, x1, x2)

inst_11625:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:34875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34875*FLEN/8, x4, x1, x2)

inst_11626:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:34878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34878*FLEN/8, x4, x1, x2)

inst_11627:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:34881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34881*FLEN/8, x4, x1, x2)

inst_11628:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:34884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34884*FLEN/8, x4, x1, x2)

inst_11629:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:34887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34887*FLEN/8, x4, x1, x2)

inst_11630:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:34890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34890*FLEN/8, x4, x1, x2)

inst_11631:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:34893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34893*FLEN/8, x4, x1, x2)

inst_11632:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:34896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34896*FLEN/8, x4, x1, x2)

inst_11633:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:34899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34899*FLEN/8, x4, x1, x2)

inst_11634:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:34902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34902*FLEN/8, x4, x1, x2)

inst_11635:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:34905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34905*FLEN/8, x4, x1, x2)

inst_11636:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:34908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34908*FLEN/8, x4, x1, x2)

inst_11637:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:34911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34911*FLEN/8, x4, x1, x2)

inst_11638:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:34914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34914*FLEN/8, x4, x1, x2)

inst_11639:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:34917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34917*FLEN/8, x4, x1, x2)

inst_11640:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:34920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34920*FLEN/8, x4, x1, x2)

inst_11641:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:34923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34923*FLEN/8, x4, x1, x2)

inst_11642:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:34926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34926*FLEN/8, x4, x1, x2)

inst_11643:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:34929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34929*FLEN/8, x4, x1, x2)

inst_11644:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:34932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34932*FLEN/8, x4, x1, x2)

inst_11645:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:34935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34935*FLEN/8, x4, x1, x2)

inst_11646:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:34938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34938*FLEN/8, x4, x1, x2)

inst_11647:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:34941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34941*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_92)
inst_11648:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:34944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34944*FLEN/8, x4, x1, x2)

inst_11649:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:34947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34947*FLEN/8, x4, x1, x2)

inst_11650:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:34950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34950*FLEN/8, x4, x1, x2)

inst_11651:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:34953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34953*FLEN/8, x4, x1, x2)

inst_11652:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:34956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34956*FLEN/8, x4, x1, x2)

inst_11653:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:34959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34959*FLEN/8, x4, x1, x2)

inst_11654:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:34962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34962*FLEN/8, x4, x1, x2)

inst_11655:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0xfc00; valaddr_reg:x3; val_offset:34965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34965*FLEN/8, x4, x1, x2)

inst_11656:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x7e00; valaddr_reg:x3; val_offset:34968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34968*FLEN/8, x4, x1, x2)

inst_11657:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0xfe00; valaddr_reg:x3; val_offset:34971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34971*FLEN/8, x4, x1, x2)

inst_11658:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x7e01; valaddr_reg:x3; val_offset:34974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34974*FLEN/8, x4, x1, x2)

inst_11659:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0xfe55; valaddr_reg:x3; val_offset:34977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34977*FLEN/8, x4, x1, x2)

inst_11660:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x7c01; valaddr_reg:x3; val_offset:34980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34980*FLEN/8, x4, x1, x2)

inst_11661:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0xfd55; valaddr_reg:x3; val_offset:34983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34983*FLEN/8, x4, x1, x2)

inst_11662:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0x3c00; valaddr_reg:x3; val_offset:34986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34986*FLEN/8, x4, x1, x2)

inst_11663:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83fe;
op3val:0xbc00; valaddr_reg:x3; val_offset:34989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34989*FLEN/8, x4, x1, x2)

inst_11664:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x0; valaddr_reg:x3; val_offset:34992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34992*FLEN/8, x4, x1, x2)

inst_11665:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x8000; valaddr_reg:x3; val_offset:34995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34995*FLEN/8, x4, x1, x2)

inst_11666:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x1; valaddr_reg:x3; val_offset:34998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 34998*FLEN/8, x4, x1, x2)

inst_11667:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x8001; valaddr_reg:x3; val_offset:35001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35001*FLEN/8, x4, x1, x2)

inst_11668:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x2; valaddr_reg:x3; val_offset:35004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35004*FLEN/8, x4, x1, x2)

inst_11669:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:35007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35007*FLEN/8, x4, x1, x2)

inst_11670:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:35010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35010*FLEN/8, x4, x1, x2)

inst_11671:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:35013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35013*FLEN/8, x4, x1, x2)

inst_11672:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x400; valaddr_reg:x3; val_offset:35016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35016*FLEN/8, x4, x1, x2)

inst_11673:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x8400; valaddr_reg:x3; val_offset:35019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35019*FLEN/8, x4, x1, x2)

inst_11674:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x401; valaddr_reg:x3; val_offset:35022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35022*FLEN/8, x4, x1, x2)

inst_11675:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x8455; valaddr_reg:x3; val_offset:35025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35025*FLEN/8, x4, x1, x2)

inst_11676:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:35028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35028*FLEN/8, x4, x1, x2)

inst_11677:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:35031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35031*FLEN/8, x4, x1, x2)

inst_11678:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:35034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35034*FLEN/8, x4, x1, x2)

inst_11679:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:35037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35037*FLEN/8, x4, x1, x2)

inst_11680:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:35040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35040*FLEN/8, x4, x1, x2)

inst_11681:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:35043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35043*FLEN/8, x4, x1, x2)

inst_11682:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:35046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35046*FLEN/8, x4, x1, x2)

inst_11683:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:35049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35049*FLEN/8, x4, x1, x2)

inst_11684:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:35052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35052*FLEN/8, x4, x1, x2)

inst_11685:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:35055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35055*FLEN/8, x4, x1, x2)

inst_11686:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:35058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35058*FLEN/8, x4, x1, x2)

inst_11687:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:35061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35061*FLEN/8, x4, x1, x2)

inst_11688:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x0; valaddr_reg:x3; val_offset:35064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35064*FLEN/8, x4, x1, x2)

inst_11689:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x8000; valaddr_reg:x3; val_offset:35067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35067*FLEN/8, x4, x1, x2)

inst_11690:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x1; valaddr_reg:x3; val_offset:35070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35070*FLEN/8, x4, x1, x2)

inst_11691:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x8001; valaddr_reg:x3; val_offset:35073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35073*FLEN/8, x4, x1, x2)

inst_11692:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x2; valaddr_reg:x3; val_offset:35076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35076*FLEN/8, x4, x1, x2)

inst_11693:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:35079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35079*FLEN/8, x4, x1, x2)

inst_11694:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:35082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35082*FLEN/8, x4, x1, x2)

inst_11695:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:35085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35085*FLEN/8, x4, x1, x2)

inst_11696:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x400; valaddr_reg:x3; val_offset:35088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35088*FLEN/8, x4, x1, x2)

inst_11697:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x8400; valaddr_reg:x3; val_offset:35091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35091*FLEN/8, x4, x1, x2)

inst_11698:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x401; valaddr_reg:x3; val_offset:35094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35094*FLEN/8, x4, x1, x2)

inst_11699:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:35097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35097*FLEN/8, x4, x1, x2)

inst_11700:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:35100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35100*FLEN/8, x4, x1, x2)

inst_11701:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:35103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35103*FLEN/8, x4, x1, x2)

inst_11702:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:35106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35106*FLEN/8, x4, x1, x2)

inst_11703:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:35109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35109*FLEN/8, x4, x1, x2)

inst_11704:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:35112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35112*FLEN/8, x4, x1, x2)

inst_11705:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:35115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35115*FLEN/8, x4, x1, x2)

inst_11706:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:35118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35118*FLEN/8, x4, x1, x2)

inst_11707:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:35121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35121*FLEN/8, x4, x1, x2)

inst_11708:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:35124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35124*FLEN/8, x4, x1, x2)

inst_11709:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:35127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35127*FLEN/8, x4, x1, x2)

inst_11710:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:35130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35130*FLEN/8, x4, x1, x2)

inst_11711:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:35133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35133*FLEN/8, x4, x1, x2)

inst_11712:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:35136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35136*FLEN/8, x4, x1, x2)

inst_11713:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:35139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35139*FLEN/8, x4, x1, x2)

inst_11714:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:35142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35142*FLEN/8, x4, x1, x2)

inst_11715:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:35145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35145*FLEN/8, x4, x1, x2)

inst_11716:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:35148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35148*FLEN/8, x4, x1, x2)

inst_11717:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:35151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35151*FLEN/8, x4, x1, x2)

inst_11718:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:35154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35154*FLEN/8, x4, x1, x2)

inst_11719:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:35157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35157*FLEN/8, x4, x1, x2)

inst_11720:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:35160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35160*FLEN/8, x4, x1, x2)

inst_11721:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:35163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35163*FLEN/8, x4, x1, x2)

inst_11722:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:35166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35166*FLEN/8, x4, x1, x2)

inst_11723:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:35169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35169*FLEN/8, x4, x1, x2)

inst_11724:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:35172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35172*FLEN/8, x4, x1, x2)

inst_11725:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:35175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35175*FLEN/8, x4, x1, x2)

inst_11726:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:35178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35178*FLEN/8, x4, x1, x2)

inst_11727:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:35181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35181*FLEN/8, x4, x1, x2)

inst_11728:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:35184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35184*FLEN/8, x4, x1, x2)

inst_11729:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:35187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35187*FLEN/8, x4, x1, x2)

inst_11730:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:35190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35190*FLEN/8, x4, x1, x2)

inst_11731:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:35193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35193*FLEN/8, x4, x1, x2)

inst_11732:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:35196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35196*FLEN/8, x4, x1, x2)

inst_11733:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:35199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35199*FLEN/8, x4, x1, x2)

inst_11734:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:35202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35202*FLEN/8, x4, x1, x2)

inst_11735:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:35205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35205*FLEN/8, x4, x1, x2)

inst_11736:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:35208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35208*FLEN/8, x4, x1, x2)

inst_11737:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:35211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35211*FLEN/8, x4, x1, x2)

inst_11738:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:35214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35214*FLEN/8, x4, x1, x2)

inst_11739:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:35217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35217*FLEN/8, x4, x1, x2)

inst_11740:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:35220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35220*FLEN/8, x4, x1, x2)

inst_11741:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:35223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35223*FLEN/8, x4, x1, x2)

inst_11742:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:35226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35226*FLEN/8, x4, x1, x2)

inst_11743:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:35229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35229*FLEN/8, x4, x1, x2)

inst_11744:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:35232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35232*FLEN/8, x4, x1, x2)

inst_11745:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:35235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35235*FLEN/8, x4, x1, x2)

inst_11746:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:35238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35238*FLEN/8, x4, x1, x2)

inst_11747:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:35241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35241*FLEN/8, x4, x1, x2)

inst_11748:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:35244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35244*FLEN/8, x4, x1, x2)

inst_11749:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:35247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35247*FLEN/8, x4, x1, x2)

inst_11750:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:35250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35250*FLEN/8, x4, x1, x2)

inst_11751:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:35253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35253*FLEN/8, x4, x1, x2)

inst_11752:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:35256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35256*FLEN/8, x4, x1, x2)

inst_11753:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:35259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35259*FLEN/8, x4, x1, x2)

inst_11754:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:35262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35262*FLEN/8, x4, x1, x2)

inst_11755:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:35265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35265*FLEN/8, x4, x1, x2)

inst_11756:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:35268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35268*FLEN/8, x4, x1, x2)

inst_11757:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:35271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35271*FLEN/8, x4, x1, x2)

inst_11758:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:35274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35274*FLEN/8, x4, x1, x2)

inst_11759:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:35277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35277*FLEN/8, x4, x1, x2)

inst_11760:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:35280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35280*FLEN/8, x4, x1, x2)

inst_11761:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:35283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35283*FLEN/8, x4, x1, x2)

inst_11762:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:35286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35286*FLEN/8, x4, x1, x2)

inst_11763:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:35289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35289*FLEN/8, x4, x1, x2)

inst_11764:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:35292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35292*FLEN/8, x4, x1, x2)

inst_11765:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:35295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35295*FLEN/8, x4, x1, x2)

inst_11766:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:35298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35298*FLEN/8, x4, x1, x2)

inst_11767:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:35301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35301*FLEN/8, x4, x1, x2)

inst_11768:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:35304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35304*FLEN/8, x4, x1, x2)

inst_11769:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:35307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35307*FLEN/8, x4, x1, x2)

inst_11770:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:35310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35310*FLEN/8, x4, x1, x2)

inst_11771:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:35313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35313*FLEN/8, x4, x1, x2)

inst_11772:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:35316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35316*FLEN/8, x4, x1, x2)

inst_11773:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:35319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35319*FLEN/8, x4, x1, x2)

inst_11774:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:35322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35322*FLEN/8, x4, x1, x2)

inst_11775:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:35325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35325*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_93)
inst_11776:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:35328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35328*FLEN/8, x4, x1, x2)

inst_11777:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:35331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35331*FLEN/8, x4, x1, x2)

inst_11778:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:35334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35334*FLEN/8, x4, x1, x2)

inst_11779:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:35337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35337*FLEN/8, x4, x1, x2)

inst_11780:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:35340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35340*FLEN/8, x4, x1, x2)

inst_11781:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:35343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35343*FLEN/8, x4, x1, x2)

inst_11782:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:35346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35346*FLEN/8, x4, x1, x2)

inst_11783:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:35349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35349*FLEN/8, x4, x1, x2)

inst_11784:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:35352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35352*FLEN/8, x4, x1, x2)

inst_11785:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:35355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35355*FLEN/8, x4, x1, x2)

inst_11786:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:35358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35358*FLEN/8, x4, x1, x2)

inst_11787:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:35361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35361*FLEN/8, x4, x1, x2)

inst_11788:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:35364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35364*FLEN/8, x4, x1, x2)

inst_11789:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:35367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35367*FLEN/8, x4, x1, x2)

inst_11790:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:35370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35370*FLEN/8, x4, x1, x2)

inst_11791:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:35373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35373*FLEN/8, x4, x1, x2)

inst_11792:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:35376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35376*FLEN/8, x4, x1, x2)

inst_11793:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:35379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35379*FLEN/8, x4, x1, x2)

inst_11794:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:35382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35382*FLEN/8, x4, x1, x2)

inst_11795:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:35385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35385*FLEN/8, x4, x1, x2)

inst_11796:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:35388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35388*FLEN/8, x4, x1, x2)

inst_11797:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:35391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35391*FLEN/8, x4, x1, x2)

inst_11798:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:35394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35394*FLEN/8, x4, x1, x2)

inst_11799:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:35397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35397*FLEN/8, x4, x1, x2)

inst_11800:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:35400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35400*FLEN/8, x4, x1, x2)

inst_11801:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:35403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35403*FLEN/8, x4, x1, x2)

inst_11802:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:35406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35406*FLEN/8, x4, x1, x2)

inst_11803:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:35409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35409*FLEN/8, x4, x1, x2)

inst_11804:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:35412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35412*FLEN/8, x4, x1, x2)

inst_11805:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:35415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35415*FLEN/8, x4, x1, x2)

inst_11806:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:35418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35418*FLEN/8, x4, x1, x2)

inst_11807:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:35421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35421*FLEN/8, x4, x1, x2)

inst_11808:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:35424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35424*FLEN/8, x4, x1, x2)

inst_11809:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:35427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35427*FLEN/8, x4, x1, x2)

inst_11810:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:35430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35430*FLEN/8, x4, x1, x2)

inst_11811:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:35433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35433*FLEN/8, x4, x1, x2)

inst_11812:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:35436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35436*FLEN/8, x4, x1, x2)

inst_11813:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:35439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35439*FLEN/8, x4, x1, x2)

inst_11814:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:35442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35442*FLEN/8, x4, x1, x2)

inst_11815:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:35445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35445*FLEN/8, x4, x1, x2)

inst_11816:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:35448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35448*FLEN/8, x4, x1, x2)

inst_11817:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:35451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35451*FLEN/8, x4, x1, x2)

inst_11818:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:35454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35454*FLEN/8, x4, x1, x2)

inst_11819:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:35457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35457*FLEN/8, x4, x1, x2)

inst_11820:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:35460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35460*FLEN/8, x4, x1, x2)

inst_11821:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:35463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35463*FLEN/8, x4, x1, x2)

inst_11822:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:35466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35466*FLEN/8, x4, x1, x2)

inst_11823:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:35469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35469*FLEN/8, x4, x1, x2)

inst_11824:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:35472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35472*FLEN/8, x4, x1, x2)

inst_11825:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:35475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35475*FLEN/8, x4, x1, x2)

inst_11826:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:35478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35478*FLEN/8, x4, x1, x2)

inst_11827:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:35481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35481*FLEN/8, x4, x1, x2)

inst_11828:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:35484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35484*FLEN/8, x4, x1, x2)

inst_11829:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:35487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35487*FLEN/8, x4, x1, x2)

inst_11830:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:35490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35490*FLEN/8, x4, x1, x2)

inst_11831:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:35493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35493*FLEN/8, x4, x1, x2)

inst_11832:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:35496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35496*FLEN/8, x4, x1, x2)

inst_11833:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:35499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35499*FLEN/8, x4, x1, x2)

inst_11834:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:35502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35502*FLEN/8, x4, x1, x2)

inst_11835:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:35505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35505*FLEN/8, x4, x1, x2)

inst_11836:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:35508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35508*FLEN/8, x4, x1, x2)

inst_11837:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:35511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35511*FLEN/8, x4, x1, x2)

inst_11838:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:35514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35514*FLEN/8, x4, x1, x2)

inst_11839:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:35517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35517*FLEN/8, x4, x1, x2)

inst_11840:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:35520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35520*FLEN/8, x4, x1, x2)

inst_11841:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:35523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35523*FLEN/8, x4, x1, x2)

inst_11842:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:35526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35526*FLEN/8, x4, x1, x2)

inst_11843:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:35529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35529*FLEN/8, x4, x1, x2)

inst_11844:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:35532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35532*FLEN/8, x4, x1, x2)

inst_11845:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:35535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35535*FLEN/8, x4, x1, x2)

inst_11846:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:35538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35538*FLEN/8, x4, x1, x2)

inst_11847:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:35541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35541*FLEN/8, x4, x1, x2)

inst_11848:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:35544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35544*FLEN/8, x4, x1, x2)

inst_11849:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:35547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35547*FLEN/8, x4, x1, x2)

inst_11850:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:35550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35550*FLEN/8, x4, x1, x2)

inst_11851:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:35553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35553*FLEN/8, x4, x1, x2)

inst_11852:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:35556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35556*FLEN/8, x4, x1, x2)

inst_11853:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:35559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35559*FLEN/8, x4, x1, x2)

inst_11854:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:35562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35562*FLEN/8, x4, x1, x2)

inst_11855:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:35565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35565*FLEN/8, x4, x1, x2)

inst_11856:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:35568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35568*FLEN/8, x4, x1, x2)

inst_11857:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:35571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35571*FLEN/8, x4, x1, x2)

inst_11858:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x1; valaddr_reg:x3; val_offset:35574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35574*FLEN/8, x4, x1, x2)

inst_11859:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x8001; valaddr_reg:x3; val_offset:35577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35577*FLEN/8, x4, x1, x2)

inst_11860:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x2; valaddr_reg:x3; val_offset:35580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35580*FLEN/8, x4, x1, x2)

inst_11861:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:35583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35583*FLEN/8, x4, x1, x2)

inst_11862:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:35586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35586*FLEN/8, x4, x1, x2)

inst_11863:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:35589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35589*FLEN/8, x4, x1, x2)

inst_11864:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x400; valaddr_reg:x3; val_offset:35592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35592*FLEN/8, x4, x1, x2)

inst_11865:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x8400; valaddr_reg:x3; val_offset:35595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35595*FLEN/8, x4, x1, x2)

inst_11866:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x401; valaddr_reg:x3; val_offset:35598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35598*FLEN/8, x4, x1, x2)

inst_11867:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x8455; valaddr_reg:x3; val_offset:35601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35601*FLEN/8, x4, x1, x2)

inst_11868:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:35604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35604*FLEN/8, x4, x1, x2)

inst_11869:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:35607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35607*FLEN/8, x4, x1, x2)

inst_11870:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:35610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35610*FLEN/8, x4, x1, x2)

inst_11871:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:35613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35613*FLEN/8, x4, x1, x2)

inst_11872:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:35616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35616*FLEN/8, x4, x1, x2)

inst_11873:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:35619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35619*FLEN/8, x4, x1, x2)

inst_11874:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:35622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35622*FLEN/8, x4, x1, x2)

inst_11875:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:35625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35625*FLEN/8, x4, x1, x2)

inst_11876:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:35628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35628*FLEN/8, x4, x1, x2)

inst_11877:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:35631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35631*FLEN/8, x4, x1, x2)

inst_11878:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:35634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35634*FLEN/8, x4, x1, x2)

inst_11879:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:35637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35637*FLEN/8, x4, x1, x2)

inst_11880:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x0; valaddr_reg:x3; val_offset:35640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35640*FLEN/8, x4, x1, x2)

inst_11881:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x8000; valaddr_reg:x3; val_offset:35643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35643*FLEN/8, x4, x1, x2)

inst_11882:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x1; valaddr_reg:x3; val_offset:35646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35646*FLEN/8, x4, x1, x2)

inst_11883:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x8001; valaddr_reg:x3; val_offset:35649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35649*FLEN/8, x4, x1, x2)

inst_11884:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x2; valaddr_reg:x3; val_offset:35652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35652*FLEN/8, x4, x1, x2)

inst_11885:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:35655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35655*FLEN/8, x4, x1, x2)

inst_11886:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:35658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35658*FLEN/8, x4, x1, x2)

inst_11887:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:35661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35661*FLEN/8, x4, x1, x2)

inst_11888:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x400; valaddr_reg:x3; val_offset:35664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35664*FLEN/8, x4, x1, x2)

inst_11889:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x8400; valaddr_reg:x3; val_offset:35667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35667*FLEN/8, x4, x1, x2)

inst_11890:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x401; valaddr_reg:x3; val_offset:35670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35670*FLEN/8, x4, x1, x2)

inst_11891:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x8455; valaddr_reg:x3; val_offset:35673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35673*FLEN/8, x4, x1, x2)

inst_11892:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:35676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35676*FLEN/8, x4, x1, x2)

inst_11893:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:35679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35679*FLEN/8, x4, x1, x2)

inst_11894:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:35682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35682*FLEN/8, x4, x1, x2)

inst_11895:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:35685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35685*FLEN/8, x4, x1, x2)

inst_11896:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:35688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35688*FLEN/8, x4, x1, x2)

inst_11897:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:35691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35691*FLEN/8, x4, x1, x2)

inst_11898:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:35694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35694*FLEN/8, x4, x1, x2)

inst_11899:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:35697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35697*FLEN/8, x4, x1, x2)

inst_11900:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:35700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35700*FLEN/8, x4, x1, x2)

inst_11901:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:35703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35703*FLEN/8, x4, x1, x2)

inst_11902:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:35706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35706*FLEN/8, x4, x1, x2)

inst_11903:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:35709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35709*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_94)
inst_11904:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:35712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35712*FLEN/8, x4, x1, x2)

inst_11905:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:35715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35715*FLEN/8, x4, x1, x2)

inst_11906:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:35718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35718*FLEN/8, x4, x1, x2)

inst_11907:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:35721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35721*FLEN/8, x4, x1, x2)

inst_11908:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:35724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35724*FLEN/8, x4, x1, x2)

inst_11909:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:35727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35727*FLEN/8, x4, x1, x2)

inst_11910:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:35730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35730*FLEN/8, x4, x1, x2)

inst_11911:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:35733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35733*FLEN/8, x4, x1, x2)

inst_11912:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:35736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35736*FLEN/8, x4, x1, x2)

inst_11913:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:35739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35739*FLEN/8, x4, x1, x2)

inst_11914:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:35742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35742*FLEN/8, x4, x1, x2)

inst_11915:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:35745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35745*FLEN/8, x4, x1, x2)

inst_11916:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:35748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35748*FLEN/8, x4, x1, x2)

inst_11917:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:35751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35751*FLEN/8, x4, x1, x2)

inst_11918:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:35754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35754*FLEN/8, x4, x1, x2)

inst_11919:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:35757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35757*FLEN/8, x4, x1, x2)

inst_11920:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:35760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35760*FLEN/8, x4, x1, x2)

inst_11921:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:35763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35763*FLEN/8, x4, x1, x2)

inst_11922:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:35766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35766*FLEN/8, x4, x1, x2)

inst_11923:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:35769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35769*FLEN/8, x4, x1, x2)

inst_11924:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:35772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35772*FLEN/8, x4, x1, x2)

inst_11925:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:35775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35775*FLEN/8, x4, x1, x2)

inst_11926:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:35778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35778*FLEN/8, x4, x1, x2)

inst_11927:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:35781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35781*FLEN/8, x4, x1, x2)

inst_11928:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:35784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35784*FLEN/8, x4, x1, x2)

inst_11929:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:35787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35787*FLEN/8, x4, x1, x2)

inst_11930:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:35790*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35790*FLEN/8, x4, x1, x2)

inst_11931:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:35793*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35793*FLEN/8, x4, x1, x2)

inst_11932:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:35796*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35796*FLEN/8, x4, x1, x2)

inst_11933:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:35799*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35799*FLEN/8, x4, x1, x2)

inst_11934:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:35802*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35802*FLEN/8, x4, x1, x2)

inst_11935:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:35805*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35805*FLEN/8, x4, x1, x2)

inst_11936:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:35808*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35808*FLEN/8, x4, x1, x2)

inst_11937:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:35811*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35811*FLEN/8, x4, x1, x2)

inst_11938:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:35814*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35814*FLEN/8, x4, x1, x2)

inst_11939:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:35817*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35817*FLEN/8, x4, x1, x2)

inst_11940:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:35820*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35820*FLEN/8, x4, x1, x2)

inst_11941:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:35823*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35823*FLEN/8, x4, x1, x2)

inst_11942:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:35826*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35826*FLEN/8, x4, x1, x2)

inst_11943:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:35829*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35829*FLEN/8, x4, x1, x2)

inst_11944:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:35832*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35832*FLEN/8, x4, x1, x2)

inst_11945:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:35835*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35835*FLEN/8, x4, x1, x2)

inst_11946:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:35838*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35838*FLEN/8, x4, x1, x2)

inst_11947:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:35841*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35841*FLEN/8, x4, x1, x2)

inst_11948:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:35844*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35844*FLEN/8, x4, x1, x2)

inst_11949:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:35847*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35847*FLEN/8, x4, x1, x2)

inst_11950:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:35850*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35850*FLEN/8, x4, x1, x2)

inst_11951:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:35853*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35853*FLEN/8, x4, x1, x2)

inst_11952:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:35856*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35856*FLEN/8, x4, x1, x2)

inst_11953:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:35859*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35859*FLEN/8, x4, x1, x2)

inst_11954:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:35862*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35862*FLEN/8, x4, x1, x2)

inst_11955:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:35865*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35865*FLEN/8, x4, x1, x2)

inst_11956:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:35868*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35868*FLEN/8, x4, x1, x2)

inst_11957:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:35871*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35871*FLEN/8, x4, x1, x2)

inst_11958:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:35874*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35874*FLEN/8, x4, x1, x2)

inst_11959:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:35877*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35877*FLEN/8, x4, x1, x2)

inst_11960:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:35880*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35880*FLEN/8, x4, x1, x2)

inst_11961:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:35883*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35883*FLEN/8, x4, x1, x2)

inst_11962:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:35886*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35886*FLEN/8, x4, x1, x2)

inst_11963:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:35889*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35889*FLEN/8, x4, x1, x2)

inst_11964:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:35892*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35892*FLEN/8, x4, x1, x2)

inst_11965:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:35895*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35895*FLEN/8, x4, x1, x2)

inst_11966:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:35898*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35898*FLEN/8, x4, x1, x2)

inst_11967:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:35901*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35901*FLEN/8, x4, x1, x2)

inst_11968:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:35904*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35904*FLEN/8, x4, x1, x2)

inst_11969:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:35907*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35907*FLEN/8, x4, x1, x2)

inst_11970:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:35910*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35910*FLEN/8, x4, x1, x2)

inst_11971:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:35913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35913*FLEN/8, x4, x1, x2)

inst_11972:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:35916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35916*FLEN/8, x4, x1, x2)

inst_11973:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:35919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35919*FLEN/8, x4, x1, x2)

inst_11974:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:35922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35922*FLEN/8, x4, x1, x2)

inst_11975:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:35925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35925*FLEN/8, x4, x1, x2)

inst_11976:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:35928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35928*FLEN/8, x4, x1, x2)

inst_11977:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:35931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35931*FLEN/8, x4, x1, x2)

inst_11978:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:35934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35934*FLEN/8, x4, x1, x2)

inst_11979:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:35937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35937*FLEN/8, x4, x1, x2)

inst_11980:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:35940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35940*FLEN/8, x4, x1, x2)

inst_11981:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:35943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35943*FLEN/8, x4, x1, x2)

inst_11982:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:35946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35946*FLEN/8, x4, x1, x2)

inst_11983:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:35949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35949*FLEN/8, x4, x1, x2)

inst_11984:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:35952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35952*FLEN/8, x4, x1, x2)

inst_11985:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:35955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35955*FLEN/8, x4, x1, x2)

inst_11986:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:35958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35958*FLEN/8, x4, x1, x2)

inst_11987:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:35961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35961*FLEN/8, x4, x1, x2)

inst_11988:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:35964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35964*FLEN/8, x4, x1, x2)

inst_11989:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:35967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35967*FLEN/8, x4, x1, x2)

inst_11990:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:35970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35970*FLEN/8, x4, x1, x2)

inst_11991:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:35973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35973*FLEN/8, x4, x1, x2)

inst_11992:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:35976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35976*FLEN/8, x4, x1, x2)

inst_11993:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:35979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35979*FLEN/8, x4, x1, x2)

inst_11994:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:35982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35982*FLEN/8, x4, x1, x2)

inst_11995:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:35985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35985*FLEN/8, x4, x1, x2)

inst_11996:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:35988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35988*FLEN/8, x4, x1, x2)

inst_11997:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:35991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35991*FLEN/8, x4, x1, x2)

inst_11998:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:35994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35994*FLEN/8, x4, x1, x2)

inst_11999:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:35997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 35997*FLEN/8, x4, x1, x2)

inst_12000:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:36000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36000*FLEN/8, x4, x1, x2)

inst_12001:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:36003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36003*FLEN/8, x4, x1, x2)

inst_12002:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:36006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36006*FLEN/8, x4, x1, x2)

inst_12003:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:36009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36009*FLEN/8, x4, x1, x2)

inst_12004:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:36012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36012*FLEN/8, x4, x1, x2)

inst_12005:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:36015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36015*FLEN/8, x4, x1, x2)

inst_12006:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:36018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36018*FLEN/8, x4, x1, x2)

inst_12007:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:36021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36021*FLEN/8, x4, x1, x2)

inst_12008:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:36024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36024*FLEN/8, x4, x1, x2)

inst_12009:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:36027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36027*FLEN/8, x4, x1, x2)

inst_12010:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:36030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36030*FLEN/8, x4, x1, x2)

inst_12011:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:36033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36033*FLEN/8, x4, x1, x2)

inst_12012:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:36036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36036*FLEN/8, x4, x1, x2)

inst_12013:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:36039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36039*FLEN/8, x4, x1, x2)

inst_12014:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:36042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36042*FLEN/8, x4, x1, x2)

inst_12015:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:36045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36045*FLEN/8, x4, x1, x2)

inst_12016:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:36048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36048*FLEN/8, x4, x1, x2)

inst_12017:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:36051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36051*FLEN/8, x4, x1, x2)

inst_12018:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:36054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36054*FLEN/8, x4, x1, x2)

inst_12019:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:36057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36057*FLEN/8, x4, x1, x2)

inst_12020:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:36060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36060*FLEN/8, x4, x1, x2)

inst_12021:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:36063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36063*FLEN/8, x4, x1, x2)

inst_12022:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:36066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36066*FLEN/8, x4, x1, x2)

inst_12023:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:36069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36069*FLEN/8, x4, x1, x2)

inst_12024:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:36072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36072*FLEN/8, x4, x1, x2)

inst_12025:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:36075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36075*FLEN/8, x4, x1, x2)

inst_12026:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:36078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36078*FLEN/8, x4, x1, x2)

inst_12027:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:36081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36081*FLEN/8, x4, x1, x2)

inst_12028:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:36084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36084*FLEN/8, x4, x1, x2)

inst_12029:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:36087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36087*FLEN/8, x4, x1, x2)

inst_12030:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:36090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36090*FLEN/8, x4, x1, x2)

inst_12031:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:36093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36093*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_95)
inst_12032:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:36096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36096*FLEN/8, x4, x1, x2)

inst_12033:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:36099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36099*FLEN/8, x4, x1, x2)

inst_12034:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:36102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36102*FLEN/8, x4, x1, x2)

inst_12035:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:36105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36105*FLEN/8, x4, x1, x2)

inst_12036:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:36108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36108*FLEN/8, x4, x1, x2)

inst_12037:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:36111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36111*FLEN/8, x4, x1, x2)

inst_12038:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:36114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36114*FLEN/8, x4, x1, x2)

inst_12039:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:36117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36117*FLEN/8, x4, x1, x2)

inst_12040:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:36120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36120*FLEN/8, x4, x1, x2)

inst_12041:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:36123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36123*FLEN/8, x4, x1, x2)

inst_12042:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:36126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36126*FLEN/8, x4, x1, x2)

inst_12043:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:36129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36129*FLEN/8, x4, x1, x2)

inst_12044:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:36132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36132*FLEN/8, x4, x1, x2)

inst_12045:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:36135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36135*FLEN/8, x4, x1, x2)

inst_12046:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:36138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36138*FLEN/8, x4, x1, x2)

inst_12047:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:36141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36141*FLEN/8, x4, x1, x2)

inst_12048:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:36144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36144*FLEN/8, x4, x1, x2)

inst_12049:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:36147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36147*FLEN/8, x4, x1, x2)

inst_12050:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:36150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36150*FLEN/8, x4, x1, x2)

inst_12051:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:36153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36153*FLEN/8, x4, x1, x2)

inst_12052:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x2; valaddr_reg:x3; val_offset:36156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36156*FLEN/8, x4, x1, x2)

inst_12053:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:36159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36159*FLEN/8, x4, x1, x2)

inst_12054:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:36162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36162*FLEN/8, x4, x1, x2)

inst_12055:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:36165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36165*FLEN/8, x4, x1, x2)

inst_12056:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x400; valaddr_reg:x3; val_offset:36168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36168*FLEN/8, x4, x1, x2)

inst_12057:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x8400; valaddr_reg:x3; val_offset:36171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36171*FLEN/8, x4, x1, x2)

inst_12058:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x401; valaddr_reg:x3; val_offset:36174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36174*FLEN/8, x4, x1, x2)

inst_12059:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x8455; valaddr_reg:x3; val_offset:36177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36177*FLEN/8, x4, x1, x2)

inst_12060:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:36180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36180*FLEN/8, x4, x1, x2)

inst_12061:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:36183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36183*FLEN/8, x4, x1, x2)

inst_12062:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:36186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36186*FLEN/8, x4, x1, x2)

inst_12063:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:36189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36189*FLEN/8, x4, x1, x2)

inst_12064:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:36192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36192*FLEN/8, x4, x1, x2)

inst_12065:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:36195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36195*FLEN/8, x4, x1, x2)

inst_12066:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:36198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36198*FLEN/8, x4, x1, x2)

inst_12067:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:36201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36201*FLEN/8, x4, x1, x2)

inst_12068:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:36204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36204*FLEN/8, x4, x1, x2)

inst_12069:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:36207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36207*FLEN/8, x4, x1, x2)

inst_12070:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:36210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36210*FLEN/8, x4, x1, x2)

inst_12071:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0x3c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:36213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36213*FLEN/8, x4, x1, x2)

inst_12072:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x0; valaddr_reg:x3; val_offset:36216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36216*FLEN/8, x4, x1, x2)

inst_12073:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x8000; valaddr_reg:x3; val_offset:36219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36219*FLEN/8, x4, x1, x2)

inst_12074:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x1; valaddr_reg:x3; val_offset:36222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36222*FLEN/8, x4, x1, x2)

inst_12075:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x8001; valaddr_reg:x3; val_offset:36225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36225*FLEN/8, x4, x1, x2)

inst_12076:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x2; valaddr_reg:x3; val_offset:36228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36228*FLEN/8, x4, x1, x2)

inst_12077:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:36231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36231*FLEN/8, x4, x1, x2)

inst_12078:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:36234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36234*FLEN/8, x4, x1, x2)

inst_12079:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:36237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36237*FLEN/8, x4, x1, x2)

inst_12080:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x400; valaddr_reg:x3; val_offset:36240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36240*FLEN/8, x4, x1, x2)

inst_12081:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:36243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36243*FLEN/8, x4, x1, x2)

inst_12082:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:36246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36246*FLEN/8, x4, x1, x2)

inst_12083:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:36249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36249*FLEN/8, x4, x1, x2)

inst_12084:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:36252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36252*FLEN/8, x4, x1, x2)

inst_12085:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:36255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36255*FLEN/8, x4, x1, x2)

inst_12086:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:36258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36258*FLEN/8, x4, x1, x2)

inst_12087:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:36261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36261*FLEN/8, x4, x1, x2)

inst_12088:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:36264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36264*FLEN/8, x4, x1, x2)

inst_12089:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:36267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36267*FLEN/8, x4, x1, x2)

inst_12090:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:36270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36270*FLEN/8, x4, x1, x2)

inst_12091:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:36273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36273*FLEN/8, x4, x1, x2)

inst_12092:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:36276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36276*FLEN/8, x4, x1, x2)

inst_12093:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:36279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36279*FLEN/8, x4, x1, x2)

inst_12094:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:36282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36282*FLEN/8, x4, x1, x2)

inst_12095:
// fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c01; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:36285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36285*FLEN/8, x4, x1, x2)

inst_12096:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:36288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36288*FLEN/8, x4, x1, x2)

inst_12097:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:36291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36291*FLEN/8, x4, x1, x2)

inst_12098:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:36294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36294*FLEN/8, x4, x1, x2)

inst_12099:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:36297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36297*FLEN/8, x4, x1, x2)

inst_12100:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:36300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36300*FLEN/8, x4, x1, x2)

inst_12101:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:36303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36303*FLEN/8, x4, x1, x2)

inst_12102:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:36306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36306*FLEN/8, x4, x1, x2)

inst_12103:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:36309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36309*FLEN/8, x4, x1, x2)

inst_12104:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:36312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36312*FLEN/8, x4, x1, x2)

inst_12105:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:36315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36315*FLEN/8, x4, x1, x2)

inst_12106:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:36318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36318*FLEN/8, x4, x1, x2)

inst_12107:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:36321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36321*FLEN/8, x4, x1, x2)

inst_12108:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:36324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36324*FLEN/8, x4, x1, x2)

inst_12109:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:36327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36327*FLEN/8, x4, x1, x2)

inst_12110:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:36330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36330*FLEN/8, x4, x1, x2)

inst_12111:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:36333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36333*FLEN/8, x4, x1, x2)

inst_12112:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:36336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36336*FLEN/8, x4, x1, x2)

inst_12113:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:36339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36339*FLEN/8, x4, x1, x2)

inst_12114:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:36342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36342*FLEN/8, x4, x1, x2)

inst_12115:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:36345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36345*FLEN/8, x4, x1, x2)

inst_12116:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:36348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36348*FLEN/8, x4, x1, x2)

inst_12117:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:36351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36351*FLEN/8, x4, x1, x2)

inst_12118:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:36354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36354*FLEN/8, x4, x1, x2)

inst_12119:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:36357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36357*FLEN/8, x4, x1, x2)

inst_12120:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:36360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36360*FLEN/8, x4, x1, x2)

inst_12121:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:36363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36363*FLEN/8, x4, x1, x2)

inst_12122:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:36366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36366*FLEN/8, x4, x1, x2)

inst_12123:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:36369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36369*FLEN/8, x4, x1, x2)

inst_12124:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:36372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36372*FLEN/8, x4, x1, x2)

inst_12125:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:36375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36375*FLEN/8, x4, x1, x2)

inst_12126:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:36378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36378*FLEN/8, x4, x1, x2)

inst_12127:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:36381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36381*FLEN/8, x4, x1, x2)

inst_12128:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:36384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36384*FLEN/8, x4, x1, x2)

inst_12129:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:36387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36387*FLEN/8, x4, x1, x2)

inst_12130:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:36390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36390*FLEN/8, x4, x1, x2)

inst_12131:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:36393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36393*FLEN/8, x4, x1, x2)

inst_12132:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:36396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36396*FLEN/8, x4, x1, x2)

inst_12133:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:36399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36399*FLEN/8, x4, x1, x2)

inst_12134:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:36402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36402*FLEN/8, x4, x1, x2)

inst_12135:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:36405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36405*FLEN/8, x4, x1, x2)

inst_12136:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:36408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36408*FLEN/8, x4, x1, x2)

inst_12137:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:36411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36411*FLEN/8, x4, x1, x2)

inst_12138:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:36414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36414*FLEN/8, x4, x1, x2)

inst_12139:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:36417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36417*FLEN/8, x4, x1, x2)

inst_12140:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:36420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36420*FLEN/8, x4, x1, x2)

inst_12141:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:36423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36423*FLEN/8, x4, x1, x2)

inst_12142:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:36426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36426*FLEN/8, x4, x1, x2)

inst_12143:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:36429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36429*FLEN/8, x4, x1, x2)

inst_12144:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:36432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36432*FLEN/8, x4, x1, x2)

inst_12145:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:36435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36435*FLEN/8, x4, x1, x2)

inst_12146:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:36438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36438*FLEN/8, x4, x1, x2)

inst_12147:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:36441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36441*FLEN/8, x4, x1, x2)

inst_12148:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:36444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36444*FLEN/8, x4, x1, x2)

inst_12149:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:36447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36447*FLEN/8, x4, x1, x2)

inst_12150:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:36450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36450*FLEN/8, x4, x1, x2)

inst_12151:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:36453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36453*FLEN/8, x4, x1, x2)

inst_12152:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:36456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36456*FLEN/8, x4, x1, x2)

inst_12153:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:36459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36459*FLEN/8, x4, x1, x2)

inst_12154:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:36462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36462*FLEN/8, x4, x1, x2)

inst_12155:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:36465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36465*FLEN/8, x4, x1, x2)

inst_12156:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:36468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36468*FLEN/8, x4, x1, x2)

inst_12157:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:36471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36471*FLEN/8, x4, x1, x2)

inst_12158:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:36474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36474*FLEN/8, x4, x1, x2)

inst_12159:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:36477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36477*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_96)
inst_12160:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:36480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36480*FLEN/8, x4, x1, x2)

inst_12161:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:36483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36483*FLEN/8, x4, x1, x2)

inst_12162:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:36486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36486*FLEN/8, x4, x1, x2)

inst_12163:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:36489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36489*FLEN/8, x4, x1, x2)

inst_12164:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:36492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36492*FLEN/8, x4, x1, x2)

inst_12165:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:36495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36495*FLEN/8, x4, x1, x2)

inst_12166:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:36498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36498*FLEN/8, x4, x1, x2)

inst_12167:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:36501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36501*FLEN/8, x4, x1, x2)

inst_12168:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:36504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36504*FLEN/8, x4, x1, x2)

inst_12169:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:36507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36507*FLEN/8, x4, x1, x2)

inst_12170:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:36510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36510*FLEN/8, x4, x1, x2)

inst_12171:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:36513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36513*FLEN/8, x4, x1, x2)

inst_12172:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:36516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36516*FLEN/8, x4, x1, x2)

inst_12173:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:36519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36519*FLEN/8, x4, x1, x2)

inst_12174:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:36522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36522*FLEN/8, x4, x1, x2)

inst_12175:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:36525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36525*FLEN/8, x4, x1, x2)

inst_12176:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:36528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36528*FLEN/8, x4, x1, x2)

inst_12177:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:36531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36531*FLEN/8, x4, x1, x2)

inst_12178:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:36534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36534*FLEN/8, x4, x1, x2)

inst_12179:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:36537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36537*FLEN/8, x4, x1, x2)

inst_12180:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:36540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36540*FLEN/8, x4, x1, x2)

inst_12181:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:36543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36543*FLEN/8, x4, x1, x2)

inst_12182:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:36546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36546*FLEN/8, x4, x1, x2)

inst_12183:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:36549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36549*FLEN/8, x4, x1, x2)

inst_12184:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:36552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36552*FLEN/8, x4, x1, x2)

inst_12185:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:36555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36555*FLEN/8, x4, x1, x2)

inst_12186:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:36558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36558*FLEN/8, x4, x1, x2)

inst_12187:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:36561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36561*FLEN/8, x4, x1, x2)

inst_12188:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:36564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36564*FLEN/8, x4, x1, x2)

inst_12189:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:36567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36567*FLEN/8, x4, x1, x2)

inst_12190:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:36570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36570*FLEN/8, x4, x1, x2)

inst_12191:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:36573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36573*FLEN/8, x4, x1, x2)

inst_12192:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:36576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36576*FLEN/8, x4, x1, x2)

inst_12193:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:36579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36579*FLEN/8, x4, x1, x2)

inst_12194:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:36582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36582*FLEN/8, x4, x1, x2)

inst_12195:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:36585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36585*FLEN/8, x4, x1, x2)

inst_12196:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:36588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36588*FLEN/8, x4, x1, x2)

inst_12197:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:36591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36591*FLEN/8, x4, x1, x2)

inst_12198:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:36594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36594*FLEN/8, x4, x1, x2)

inst_12199:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:36597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36597*FLEN/8, x4, x1, x2)

inst_12200:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:36600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36600*FLEN/8, x4, x1, x2)

inst_12201:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:36603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36603*FLEN/8, x4, x1, x2)

inst_12202:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:36606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36606*FLEN/8, x4, x1, x2)

inst_12203:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:36609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36609*FLEN/8, x4, x1, x2)

inst_12204:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:36612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36612*FLEN/8, x4, x1, x2)

inst_12205:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:36615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36615*FLEN/8, x4, x1, x2)

inst_12206:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:36618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36618*FLEN/8, x4, x1, x2)

inst_12207:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:36621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36621*FLEN/8, x4, x1, x2)

inst_12208:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:36624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36624*FLEN/8, x4, x1, x2)

inst_12209:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:36627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36627*FLEN/8, x4, x1, x2)

inst_12210:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:36630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36630*FLEN/8, x4, x1, x2)

inst_12211:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:36633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36633*FLEN/8, x4, x1, x2)

inst_12212:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:36636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36636*FLEN/8, x4, x1, x2)

inst_12213:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:36639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36639*FLEN/8, x4, x1, x2)

inst_12214:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:36642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36642*FLEN/8, x4, x1, x2)

inst_12215:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:36645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36645*FLEN/8, x4, x1, x2)

inst_12216:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:36648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36648*FLEN/8, x4, x1, x2)

inst_12217:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:36651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36651*FLEN/8, x4, x1, x2)

inst_12218:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:36654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36654*FLEN/8, x4, x1, x2)

inst_12219:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:36657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36657*FLEN/8, x4, x1, x2)

inst_12220:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:36660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36660*FLEN/8, x4, x1, x2)

inst_12221:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:36663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36663*FLEN/8, x4, x1, x2)

inst_12222:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:36666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36666*FLEN/8, x4, x1, x2)

inst_12223:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:36669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36669*FLEN/8, x4, x1, x2)

inst_12224:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:36672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36672*FLEN/8, x4, x1, x2)

inst_12225:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:36675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36675*FLEN/8, x4, x1, x2)

inst_12226:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:36678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36678*FLEN/8, x4, x1, x2)

inst_12227:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:36681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36681*FLEN/8, x4, x1, x2)

inst_12228:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:36684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36684*FLEN/8, x4, x1, x2)

inst_12229:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:36687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36687*FLEN/8, x4, x1, x2)

inst_12230:
// fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xfd55; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:36690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 36690*FLEN/8, x4, x1, x2)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31745,16,FLEN)
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NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(32257,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_109:
    .fill 14*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
