
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 05:33:17 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmsub_b6 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmsub_b6)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x7,test_dataset_0)
RVTEST_SIGBASE(x4,signature_x4_1)

inst_0:
// rs1 == rs2 == rs3 != rd, rs1==x22, rs2==x22, rs3==x22, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x22; op2:x22; op3:x22; dest:x30; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x30, x22, x22, x22, dyn, 0, 0, x7, 0*FLEN/8, x10, x4, x5)

inst_1:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x25, rs2==x3, rs3==x7, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x25; op2:x3; op3:x7; dest:x24; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, x24, x25, x3, x7, dyn, 32, 0, x7, 3*FLEN/8, x10, x4, x5)

inst_2:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x8, rs2==x8, rs3==x10, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x8; op2:x8; op3:x10; dest:x23; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, x23, x8, x8, x10, dyn, 64, 0, x7, 6*FLEN/8, x10, x4, x5)

inst_3:
// rd == rs2 == rs3 != rs1, rs1==x0, rs2==x6, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x0; op2:x6; op3:x6; dest:x6; op1val:0x0; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, x6, x0, x6, x6, dyn, 96, 0, x7, 9*FLEN/8, x10, x4, x5)

inst_4:
// rs1 == rs2 == rs3 == rd, rs1==x21, rs2==x21, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x21; op2:x21; op3:x21; dest:x21; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, x21, x21, x21, x21, dyn, 128, 0, x7, 12*FLEN/8, x10, x4, x5)

inst_5:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x11, rs2==x17, rs3==x31, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x11; op2:x17; op3:x31; dest:x17; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x17, x11, x17, x31, dyn, 0, 0, x7, 15*FLEN/8, x10, x4, x5)

inst_6:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x17, rs2==x28, rs3==x15, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x17; op2:x28; op3:x15; dest:x15; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, x15, x17, x28, x15, dyn, 32, 0, x7, 18*FLEN/8, x10, x4, x5)

inst_7:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x26, rs2==x13, rs3==x30, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x26; op2:x13; op3:x30; dest:x26; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, x26, x26, x13, x30, dyn, 64, 0, x7, 21*FLEN/8, x10, x4, x5)

inst_8:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x9, rs2==x16, rs3==x16, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x9; op2:x16; op3:x16; dest:x2; op1val:0x0; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, x2, x9, x16, x16, dyn, 96, 0, x7, 24*FLEN/8, x10, x4, x5)

inst_9:
// rs1 == rs2 == rd != rs3, rs1==x14, rs2==x14, rs3==x11, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x14; op2:x14; op3:x11; dest:x14; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, x14, x14, x14, x11, dyn, 128, 0, x7, 27*FLEN/8, x10, x4, x5)

inst_10:
// rs1 == rd == rs3 != rs2, rs1==x29, rs2==x27, rs3==x29, rd==x29,
/* opcode: fmsub.h ; op1:x29; op2:x27; op3:x29; dest:x29; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x29, x29, x27, x29, dyn, 0, 0, x7, 30*FLEN/8, x10, x4, x5)

inst_11:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x19, rs2==x0, rs3==x19, rd==x1,
/* opcode: fmsub.h ; op1:x19; op2:x0; op3:x19; dest:x1; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x1, x19, x0, x19, dyn, 0, 0, x7, 33*FLEN/8, x10, x4, x5)
RVTEST_VALBASEUPD(x8,test_dataset_1)

inst_12:
// rs1==x3, rs2==x25, rs3==x18, rd==x7,
/* opcode: fmsub.h ; op1:x3; op2:x25; op3:x18; dest:x7; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x7, x3, x25, x18, dyn, 0, 0, x8, 0*FLEN/8, x14, x4, x5)

inst_13:
// rs1==x18, rs2==x12, rs3==x24, rd==x31,
/* opcode: fmsub.h ; op1:x18; op2:x12; op3:x24; dest:x31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x31, x18, x12, x24, dyn, 0, 0, x8, 3*FLEN/8, x14, x4, x6)
RVTEST_SIGBASE(x3,signature_x3_0)

inst_14:
// rs1==x27, rs2==x31, rs3==x8, rd==x22,
/* opcode: fmsub.h ; op1:x27; op2:x31; op3:x8; dest:x22; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x22, x27, x31, x8, dyn, 0, 0, x8, 6*FLEN/8, x14, x3, x6)

inst_15:
// rs1==x30, rs2==x10, rs3==x0, rd==x18,
/* opcode: fmsub.h ; op1:x30; op2:x10; op3:x0; dest:x18; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x18, x30, x10, x0, dyn, 0, 0, x8, 9*FLEN/8, x14, x3, x6)

inst_16:
// rs1==x15, rs2==x5, rs3==x28, rd==x4,
/* opcode: fmsub.h ; op1:x15; op2:x5; op3:x28; dest:x4; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x4, x15, x5, x28, dyn, 0, 0, x8, 12*FLEN/8, x14, x3, x6)

inst_17:
// rs1==x28, rs2==x20, rs3==x5, rd==x25,
/* opcode: fmsub.h ; op1:x28; op2:x20; op3:x5; dest:x25; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x25, x28, x20, x5, dyn, 0, 0, x8, 15*FLEN/8, x14, x3, x6)

inst_18:
// rs1==x10, rs2==x9, rs3==x13, rd==x19,
/* opcode: fmsub.h ; op1:x10; op2:x9; op3:x13; dest:x19; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x19, x10, x9, x13, dyn, 0, 0, x8, 18*FLEN/8, x14, x3, x6)

inst_19:
// rs1==x20, rs2==x15, rs3==x4, rd==x12,
/* opcode: fmsub.h ; op1:x20; op2:x15; op3:x4; dest:x12; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x12, x20, x15, x4, dyn, 0, 0, x8, 21*FLEN/8, x14, x3, x6)

inst_20:
// rs1==x1, rs2==x18, rs3==x9, rd==x13,
/* opcode: fmsub.h ; op1:x1; op2:x18; op3:x9; dest:x13; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x13, x1, x18, x9, dyn, 0, 0, x8, 24*FLEN/8, x14, x3, x6)

inst_21:
// rs1==x24, rs2==x4, rs3==x12, rd==x20,
/* opcode: fmsub.h ; op1:x24; op2:x4; op3:x12; dest:x20; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x20, x24, x4, x12, dyn, 0, 0, x8, 27*FLEN/8, x14, x3, x6)

inst_22:
// rs1==x31, rs2==x24, rs3==x25, rd==x11,
/* opcode: fmsub.h ; op1:x31; op2:x24; op3:x25; dest:x11; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x11, x31, x24, x25, dyn, 0, 0, x8, 30*FLEN/8, x14, x3, x6)

inst_23:
// rs1==x4, rs2==x1, rs3==x2, rd==x9,
/* opcode: fmsub.h ; op1:x4; op2:x1; op3:x2; dest:x9; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x9, x4, x1, x2, dyn, 0, 0, x8, 33*FLEN/8, x14, x3, x6)

inst_24:
// rs1==x12, rs2==x7, rs3==x17, rd==x16,
/* opcode: fmsub.h ; op1:x12; op2:x7; op3:x17; dest:x16; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x16, x12, x7, x17, dyn, 0, 0, x8, 36*FLEN/8, x14, x3, x6)

inst_25:
// rs1==x13, rs2==x19, rs3==x23, rd==x10,
/* opcode: fmsub.h ; op1:x13; op2:x19; op3:x23; dest:x10; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x10, x13, x19, x23, dyn, 0, 0, x8, 39*FLEN/8, x14, x3, x6)

inst_26:
// rs1==x16, rs2==x11, rs3==x14, rd==x28,
/* opcode: fmsub.h ; op1:x16; op2:x11; op3:x14; dest:x28; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x28, x16, x11, x14, dyn, 0, 0, x8, 42*FLEN/8, x14, x3, x6)

inst_27:
// rs1==x2, rs2==x26, rs3==x27, rd==x5,
/* opcode: fmsub.h ; op1:x2; op2:x26; op3:x27; dest:x5; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x5, x2, x26, x27, dyn, 0, 0, x8, 45*FLEN/8, x14, x3, x6)
RVTEST_VALBASEUPD(x4,test_dataset_2)

inst_28:
// rs1==x7, rs2==x2, rs3==x26, rd==x8,
/* opcode: fmsub.h ; op1:x7; op2:x2; op3:x26; dest:x8; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x8, x7, x2, x26, dyn, 0, 0, x4, 0*FLEN/8, x9, x3, x6)

inst_29:
// rs1==x5, rs2==x23, rs3==x1, rd==x0,
/* opcode: fmsub.h ; op1:x5; op2:x23; op3:x1; dest:x0; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x4; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x0, x5, x23, x1, dyn, 0, 0, x4, 3*FLEN/8, x9, x3, x2)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_30:
// rs1==x23, rs2==x29, rs3==x3, rd==x27,
/* opcode: fmsub.h ; op1:x23; op2:x29; op3:x3; dest:x27; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x27, x23, x29, x3, dyn, 0, 0, x4, 6*FLEN/8, x9, x1, x2)

inst_31:
// rs1==x6, rs2==x30, rs3==x20, rd==x3,
/* opcode: fmsub.h ; op1:x6; op2:x30; op3:x20; dest:x3; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x4; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x3, x6, x30, x20, dyn, 0, 0, x4, 9*FLEN/8, x9, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 0, 0, x4, 12*FLEN/8, x9, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x4; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 64, 0, x4, 15*FLEN/8, x9, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x4, 18*FLEN/8, x9, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x4; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x4, 21*FLEN/8, x9, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 96, 0, x4, 24*FLEN/8, x9, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x4; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, x31, x30, x29, x28, dyn, 128, 0, x4, 27*FLEN/8, x9, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64511,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31743,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31743,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31743,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31743,32,FLEN)
NAN_BOXED(31743,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_2:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x4_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x4_1:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_0:
    .fill 32*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 16*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
