
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:45:11 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmsub_b14 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmsub_b14)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 == rs3 == rd, rs1==f31, rs2==f31, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f31; op2:f31; op3:f31; dest:f31; op1val:0x739c; op2val:0x739c;
op3val:0x739c; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd == rs3 != rs2, rs1==f30, rs2==f29, rs3==f30, rd==f30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f30; dest:f30; op1val:0x739c; op2val:0x785a;
op3val:0x739c; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f30, f30, f29, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f30, rs3==f28, rd==f29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f29; op2:f30; op3:f28; dest:f29; op1val:0x739c; op2val:0x785a;
op3val:0x41ea; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f29, f29, f30, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f28, rs3==f29, rd==f28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f27; op2:f28; op3:f29; dest:f28; op1val:0x739c; op2val:0x785a;
op3val:0x45ea; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f28, f27, f28, f29, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rd == rs2 == rs3 != rs1, rs1==f28, rs2==f27, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f28; op2:f27; op3:f27; dest:f27; op1val:0x739c; op2val:0x785a;
op3val:0x785a; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f27, f28, f27, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f25, rs2==f24, rs3==f26, rd==f26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f25; op2:f24; op3:f26; dest:f26; op1val:0x739c; op2val:0x785a;
op3val:0x4dea; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f26, f25, f24, f26, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f24, rs2==f26, rs3==f24, rd==f25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f24; op2:f26; op3:f24; dest:f25; op1val:0x739c; op2val:0x785a;
op3val:0x739c; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f25, f24, f26, f24, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rs3 != rd, rs1==f23, rs2==f23, rs3==f23, rd==f24,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x15 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f23; op2:f23; op3:f23; dest:f24; op1val:0x739c; op2val:0x739c;
op3val:0x739c; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f24, f23, f23, f23, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f25, rs3==f25, rd==f23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x16 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f26; op2:f25; op3:f25; dest:f23; op1val:0x739c; op2val:0x785a;
op3val:0x785a; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f23, f26, f25, f25, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f20, rd==f22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f21; op2:f21; op3:f20; dest:f22; op1val:0x739c; op2val:0x739c;
op3val:0x5dea; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f22, f21, f21, f20, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs2 == rd != rs3, rs1==f20, rs2==f20, rs3==f22, rd==f20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x18 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f20; op2:f20; op3:f22; dest:f20; op1val:0x739c; op2val:0x739c;
op3val:0x61ea; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f20, f20, f20, f22, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f22, rs2==f19, rs3==f18, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f22; op2:f19; op3:f18; dest:f21; op1val:0x739c; op2val:0x785a;
op3val:0x65ea; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f21, f22, f19, f18, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f22, rs3==f21, rd==f19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f18; op2:f22; op3:f21; dest:f19; op1val:0x739c; op2val:0x785a;
op3val:0x69ea; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f19, f18, f22, f21, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x739c; op2val:0x785a;
op3val:0x6dea; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x739c; op2val:0x785a;
op3val:0x71ea; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f14, rd==f16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f17; op2:f15; op3:f14; dest:f16; op1val:0x739c; op2val:0x785a;
op3val:0x75ea; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f16, f17, f15, f14, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f17, rd==f15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f14; op2:f16; op3:f17; dest:f15; op1val:0x739c; op2val:0x785a;
op3val:0x79ea; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f15, f14, f16, f17, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x739c; op2val:0x785a;
op3val:0x7bff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,
/* opcode: fnmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f10, rd==f12,
/* opcode: fnmsub.h ; op1:f13; op2:f11; op3:f10; dest:f12; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f12, f13, f11, f10, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f13, rd==f11,
/* opcode: fnmsub.h ; op1:f10; op2:f12; op3:f13; dest:f11; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f11, f10, f12, f13, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,
/* opcode: fnmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,
/* opcode: fnmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f6, rd==f8,
/* opcode: fnmsub.h ; op1:f9; op2:f7; op3:f6; dest:f8; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f8, f9, f7, f6, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f9, rd==f7,
/* opcode: fnmsub.h ; op1:f6; op2:f8; op3:f9; dest:f7; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f7, f6, f8, f9, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,
/* opcode: fnmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,
/* opcode: fnmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f2, rd==f4,
/* opcode: fnmsub.h ; op1:f5; op2:f3; op3:f2; dest:f4; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f4, f5, f3, f2, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f5, rd==f3,
/* opcode: fnmsub.h ; op1:f2; op2:f4; op3:f5; dest:f3; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f3, f2, f4, f5, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,
/* opcode: fnmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,
/* opcode: fnmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,
/* opcode: fnmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,
/* opcode: fnmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f1,
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f1; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f1, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f0,
/* opcode: fnmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x39ea; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x3dea; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x49ea; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x51ea; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x15 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x55ea; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x16 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x59ea; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x5dea; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x05a and fs3 == 0 and fe3 == 0x18 and fm3 == 0x1ea and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x739c; op2val:0x785a;
op3val:0x61ea; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(16874,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(17898,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(19946,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(24042,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(25066,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(26090,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(27114,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(28138,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(29162,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(30186,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(14826,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(15850,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(18922,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(20970,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(21994,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(23018,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(24042,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(25066,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 86*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
