
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fsub.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsub.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fsub_b5 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fsub_b5)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 != rd, rs1==f24, rs2==f24, rd==f17,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f24; op2:f24; dest:f17; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f17, f24, f24, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd != rs2, rs1==f29, rs2==f2, rd==f29,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f29; op2:f2; dest:f29; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f29, f29, f2, dyn, 32, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_2:
// rs2 == rd != rs1, rs1==f19, rs2==f7, rd==f7,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f19; op2:f7; dest:f7; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f7, f19, f7, dyn, 64, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rs2 == rd, rs1==f10, rs2==f10, rd==f10,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f10; op2:f10; dest:f10; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f10, f10, f10, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_4:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f27, rs2==f29, rd==f12,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f27; op2:f29; dest:f12; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f12, f27, f29, dyn, 128, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_5:
// rs1==f16, rs2==f6, rd==f26,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f16; op2:f6; dest:f26; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f26, f16, f6, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_6:
// rs1==f30, rs2==f12, rd==f2,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f12; dest:f2; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f2, f30, f12, dyn, 32, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_7:
// rs1==f25, rs2==f22, rd==f18,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f25; op2:f22; dest:f18; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f18, f25, f22, dyn, 64, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_8:
// rs1==f3, rs2==f19, rd==f21,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f3; op2:f19; dest:f21; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f21, f3, f19, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_9:
// rs1==f9, rs2==f3, rd==f0,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f9; op2:f3; dest:f0; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f0, f9, f3, dyn, 128, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_10:
// rs1==f2, rs2==f23, rd==f13,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f2; op2:f23; dest:f13; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f13, f2, f23, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_11:
// rs1==f23, rs2==f13, rd==f15,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f23; op2:f13; dest:f15; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f15, f23, f13, dyn, 32, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f4, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f4; op2:f27; dest:f28; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f28, f4, f27, dyn, 64, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f8, rs2==f20, rd==f14,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f8; op2:f20; dest:f14; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f14, f8, f20, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f15, rs2==f28, rd==f25,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f15; op2:f28; dest:f25; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f25, f15, f28, dyn, 128, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f14, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f14; op2:f21; dest:f20; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f20, f14, f21, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f11, rs2==f9, rd==f31,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f11; op2:f9; dest:f31; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f11, f9, dyn, 32, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f26, rs2==f30, rd==f4,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f26; op2:f30; dest:f4; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f4, f26, f30, dyn, 64, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f1, rs2==f18, rd==f5,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f1; op2:f18; dest:f5; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f5, f1, f18, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f18, rs2==f26, rd==f11,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f18; op2:f26; dest:f11; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f11, f18, f26, dyn, 128, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f17, rs2==f11, rd==f8,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f17; op2:f11; dest:f8; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f8, f17, f11, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f21, rs2==f0, rd==f22,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f21; op2:f0; dest:f22; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f22, f21, f0, dyn, 32, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f7, rs2==f16, rd==f9,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f7; op2:f16; dest:f9; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f9, f7, f16, dyn, 64, 0, x3, 44*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f13, rs2==f4, rd==f6,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f13; op2:f4; dest:f6; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f6, f13, f4, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f5, rs2==f17, rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f5; op2:f17; dest:f1; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f1, f5, f17, dyn, 128, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f12, rs2==f5, rd==f30,fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f12; op2:f5; dest:f30; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f30, f12, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f6, rs2==f14, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f6; op2:f14; dest:f3; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f3, f6, f14, dyn, 32, 0, x3, 52*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f31, rs2==f1, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f31; op2:f1; dest:f16; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f16, f31, f1, dyn, 64, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f22, rs2==f31, rd==f27,fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f22; op2:f31; dest:f27; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f27, f22, f31, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f20, rs2==f15, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f20; op2:f15; dest:f24; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f24, f20, f15, dyn, 128, 0, x3, 58*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f25, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f0; op2:f25; dest:f23; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f23, f0, f25, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f28, rs2==f8, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f28; op2:f8; dest:f19; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f19, f28, f8, dyn, 32, 0, x3, 62*FLEN/8, x4, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 64*FLEN/8, x4, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 68*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 74*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 82*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 88*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 92*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 94*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 98*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 104*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 112*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 116*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 118*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 122*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 124*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 128*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 134*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 136*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 142*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 146*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 148*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 152*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 154*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 158*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 164*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 166*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 172*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 176*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 178*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 182*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 184*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 188*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 190*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 194*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 196*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 200*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 202*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 206*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 208*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 212*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 214*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 218*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 220*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 224*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 226*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 230*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 232*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 236*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 238*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 242*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x3; val_offset:244*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 244*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x3; val_offset:248*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 248*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x3; val_offset:250*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 250*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x3; val_offset:254*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 254*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x3; val_offset:256*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 256*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x3; val_offset:260*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 260*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x3; val_offset:262*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 262*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x3; val_offset:266*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 266*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x3; val_offset:268*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 268*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:272*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 272*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:274*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 274*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:278*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 278*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x3; val_offset:280*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 280*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x3; val_offset:284*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 284*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x3; val_offset:286*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 286*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x3; val_offset:290*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 290*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x3; val_offset:292*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 292*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x3; val_offset:296*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 296*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x3; val_offset:298*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 298*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x3; val_offset:302*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 302*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x3; val_offset:304*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 304*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x3; val_offset:308*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 308*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:310*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 310*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:314*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 314*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:316*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 316*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x3; val_offset:320*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 320*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x3; val_offset:322*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 322*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x3; val_offset:326*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 326*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x3; val_offset:328*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 328*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x3; val_offset:332*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 332*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x3; val_offset:334*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 334*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x3; val_offset:338*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 338*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x3; val_offset:340*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 340*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x3; val_offset:344*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 344*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x3; val_offset:346*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 346*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x3; val_offset:350*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 350*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x3; val_offset:352*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 352*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x3; val_offset:356*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 356*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x3; val_offset:358*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 358*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x3; val_offset:362*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 362*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x3; val_offset:364*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 364*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x3; val_offset:368*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 368*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x3; val_offset:370*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 370*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x3; val_offset:374*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 374*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x3; val_offset:376*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 376*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x3; val_offset:380*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 380*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x3; val_offset:382*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 382*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x3; val_offset:386*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 386*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x3; val_offset:388*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 388*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x3; val_offset:392*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 392*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x3; val_offset:394*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 394*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x3; val_offset:398*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 398*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x3; val_offset:400*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 400*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x3; val_offset:404*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 404*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x3; val_offset:406*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 406*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x3; val_offset:410*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 410*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x3; val_offset:412*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 412*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x3; val_offset:416*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 416*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x3; val_offset:418*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 418*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x3; val_offset:422*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 422*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x3; val_offset:424*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 424*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x3; val_offset:428*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 428*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x3; val_offset:430*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 430*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x3; val_offset:434*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 434*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x3; val_offset:436*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 436*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x80 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 128, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:440*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 0, 0, x3, 440*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:442*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 32, 0, x3, 442*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 64, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fsub.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x3; val_offset:446*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fsub.s, f31, f30, f29, dyn, 96, 0, x3, 446*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cb26d35,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7cd4206e,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d0597cb,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7d902b16,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7db9afdd,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7dce622b,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e04dea3,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e26592c,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e280619,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e2fb07b,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e330244,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e5e8d61,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e68fcac,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e8fe2cd,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7e97246c,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7ea82619,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7eab0757,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebc0ad4,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ebe3f3f,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec0dc0e,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec2076b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec33c5b,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec549ce,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7ec80a54,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7edddf89,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7ef6a41a,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7efa3631,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f06fbdb,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f0a8666,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f125b96,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f12a50c,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f13f0c0,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f191a03,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f1f5de9,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f207786,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f20d0a1,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f252cf6,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f296f9b,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f2d12f5,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f33cbed,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f34510e,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3cc5a4,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7f3e917d,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
NAN_BOXED(0x7c9c56e0,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 192*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
