
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Feb  5 07:30:48 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fnmadd_b15)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)

inst_7670:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39700000; valaddr_reg:x12; val_offset:22947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22947*FLEN/8, x13, x9, x10)

inst_7671:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x390fffff; valaddr_reg:x12; val_offset:22950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22950*FLEN/8, x13, x9, x10)

inst_7672:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39780000; valaddr_reg:x12; val_offset:22953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22953*FLEN/8, x13, x9, x10)

inst_7673:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3907ffff; valaddr_reg:x12; val_offset:22956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22956*FLEN/8, x13, x9, x10)

inst_7674:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397c0000; valaddr_reg:x12; val_offset:22959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22959*FLEN/8, x13, x9, x10)

inst_7675:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3903ffff; valaddr_reg:x12; val_offset:22962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22962*FLEN/8, x13, x9, x10)

inst_7676:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397e0000; valaddr_reg:x12; val_offset:22965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22965*FLEN/8, x13, x9, x10)

inst_7677:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3901ffff; valaddr_reg:x12; val_offset:22968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22968*FLEN/8, x13, x9, x10)

inst_7678:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397f0000; valaddr_reg:x12; val_offset:22971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22971*FLEN/8, x13, x9, x10)

inst_7679:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3900ffff; valaddr_reg:x12; val_offset:22974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22974*FLEN/8, x13, x9, x10)

inst_7680:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397f8000; valaddr_reg:x12; val_offset:22977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22977*FLEN/8, x13, x9, x10)

inst_7681:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39007fff; valaddr_reg:x12; val_offset:22980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22980*FLEN/8, x13, x9, x10)

inst_7682:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397fc000; valaddr_reg:x12; val_offset:22983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22983*FLEN/8, x13, x9, x10)

inst_7683:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39003fff; valaddr_reg:x12; val_offset:22986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22986*FLEN/8, x13, x9, x10)

inst_7684:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397fe000; valaddr_reg:x12; val_offset:22989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22989*FLEN/8, x13, x9, x10)

inst_7685:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39001fff; valaddr_reg:x12; val_offset:22992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22992*FLEN/8, x13, x9, x10)

inst_7686:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ff000; valaddr_reg:x12; val_offset:22995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22995*FLEN/8, x13, x9, x10)

inst_7687:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39000fff; valaddr_reg:x12; val_offset:22998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 22998*FLEN/8, x13, x9, x10)

inst_7688:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ff800; valaddr_reg:x12; val_offset:23001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23001*FLEN/8, x13, x9, x10)

inst_7689:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x390007ff; valaddr_reg:x12; val_offset:23004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23004*FLEN/8, x13, x9, x10)

inst_7690:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ffc00; valaddr_reg:x12; val_offset:23007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23007*FLEN/8, x13, x9, x10)

inst_7691:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x390003ff; valaddr_reg:x12; val_offset:23010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23010*FLEN/8, x13, x9, x10)

inst_7692:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ffe00; valaddr_reg:x12; val_offset:23013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23013*FLEN/8, x13, x9, x10)

inst_7693:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x390001ff; valaddr_reg:x12; val_offset:23016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23016*FLEN/8, x13, x9, x10)

inst_7694:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397fff00; valaddr_reg:x12; val_offset:23019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23019*FLEN/8, x13, x9, x10)

inst_7695:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x390000ff; valaddr_reg:x12; val_offset:23022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23022*FLEN/8, x13, x9, x10)

inst_7696:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397fff80; valaddr_reg:x12; val_offset:23025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23025*FLEN/8, x13, x9, x10)

inst_7697:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3900007f; valaddr_reg:x12; val_offset:23028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23028*FLEN/8, x13, x9, x10)

inst_7698:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397fffc0; valaddr_reg:x12; val_offset:23031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23031*FLEN/8, x13, x9, x10)

inst_7699:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3900003f; valaddr_reg:x12; val_offset:23034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23034*FLEN/8, x13, x9, x10)

inst_7700:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397fffe0; valaddr_reg:x12; val_offset:23037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23037*FLEN/8, x13, x9, x10)

inst_7701:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3900001f; valaddr_reg:x12; val_offset:23040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23040*FLEN/8, x13, x9, x10)

inst_7702:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ffff0; valaddr_reg:x12; val_offset:23043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23043*FLEN/8, x13, x9, x10)

inst_7703:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3900000f; valaddr_reg:x12; val_offset:23046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23046*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_60)
inst_7704:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ffff8; valaddr_reg:x12; val_offset:23049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23049*FLEN/8, x13, x9, x10)

inst_7705:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39000007; valaddr_reg:x12; val_offset:23052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23052*FLEN/8, x13, x9, x10)

inst_7706:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ffffc; valaddr_reg:x12; val_offset:23055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23055*FLEN/8, x13, x9, x10)

inst_7707:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39000003; valaddr_reg:x12; val_offset:23058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23058*FLEN/8, x13, x9, x10)

inst_7708:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x397ffffe; valaddr_reg:x12; val_offset:23061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23061*FLEN/8, x13, x9, x10)

inst_7709:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x72 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x39000001; valaddr_reg:x12; val_offset:23064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23064*FLEN/8, x13, x9, x10)

inst_7710:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:23067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23067*FLEN/8, x13, x9, x10)

inst_7711:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3f800007; valaddr_reg:x12; val_offset:23070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23070*FLEN/8, x13, x9, x10)

inst_7712:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:23073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23073*FLEN/8, x13, x9, x10)

inst_7713:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3f800003; valaddr_reg:x12; val_offset:23076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23076*FLEN/8, x13, x9, x10)

inst_7714:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:23079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23079*FLEN/8, x13, x9, x10)

inst_7715:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3f800001; valaddr_reg:x12; val_offset:23082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23082*FLEN/8, x13, x9, x10)

inst_7716:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:23085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23085*FLEN/8, x13, x9, x10)

inst_7717:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:23088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23088*FLEN/8, x13, x9, x10)

inst_7718:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3f999999; valaddr_reg:x12; val_offset:23091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23091*FLEN/8, x13, x9, x10)

inst_7719:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:23094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23094*FLEN/8, x13, x9, x10)

inst_7720:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:23097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23097*FLEN/8, x13, x9, x10)

inst_7721:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:23100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23100*FLEN/8, x13, x9, x10)

inst_7722:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:23103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23103*FLEN/8, x13, x9, x10)

inst_7723:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:23106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23106*FLEN/8, x13, x9, x10)

inst_7724:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:23109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23109*FLEN/8, x13, x9, x10)

inst_7725:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57f583 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x17bb83 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e57f583; op2val:0x97bb83;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:23112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23112*FLEN/8, x13, x9, x10)

inst_7726:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39800000; valaddr_reg:x12; val_offset:23115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23115*FLEN/8, x13, x9, x10)

inst_7727:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffffff; valaddr_reg:x12; val_offset:23118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23118*FLEN/8, x13, x9, x10)

inst_7728:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39c00000; valaddr_reg:x12; val_offset:23121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23121*FLEN/8, x13, x9, x10)

inst_7729:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39bfffff; valaddr_reg:x12; val_offset:23124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23124*FLEN/8, x13, x9, x10)

inst_7730:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39e00000; valaddr_reg:x12; val_offset:23127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23127*FLEN/8, x13, x9, x10)

inst_7731:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x399fffff; valaddr_reg:x12; val_offset:23130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23130*FLEN/8, x13, x9, x10)

inst_7732:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39f00000; valaddr_reg:x12; val_offset:23133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23133*FLEN/8, x13, x9, x10)

inst_7733:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x398fffff; valaddr_reg:x12; val_offset:23136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23136*FLEN/8, x13, x9, x10)

inst_7734:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39f80000; valaddr_reg:x12; val_offset:23139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23139*FLEN/8, x13, x9, x10)

inst_7735:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3987ffff; valaddr_reg:x12; val_offset:23142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23142*FLEN/8, x13, x9, x10)

inst_7736:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fc0000; valaddr_reg:x12; val_offset:23145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23145*FLEN/8, x13, x9, x10)

inst_7737:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3983ffff; valaddr_reg:x12; val_offset:23148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23148*FLEN/8, x13, x9, x10)

inst_7738:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fe0000; valaddr_reg:x12; val_offset:23151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23151*FLEN/8, x13, x9, x10)

inst_7739:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3981ffff; valaddr_reg:x12; val_offset:23154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23154*FLEN/8, x13, x9, x10)

inst_7740:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ff0000; valaddr_reg:x12; val_offset:23157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23157*FLEN/8, x13, x9, x10)

inst_7741:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3980ffff; valaddr_reg:x12; val_offset:23160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23160*FLEN/8, x13, x9, x10)

inst_7742:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ff8000; valaddr_reg:x12; val_offset:23163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23163*FLEN/8, x13, x9, x10)

inst_7743:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39807fff; valaddr_reg:x12; val_offset:23166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23166*FLEN/8, x13, x9, x10)

inst_7744:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffc000; valaddr_reg:x12; val_offset:23169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23169*FLEN/8, x13, x9, x10)

inst_7745:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39803fff; valaddr_reg:x12; val_offset:23172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23172*FLEN/8, x13, x9, x10)

inst_7746:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffe000; valaddr_reg:x12; val_offset:23175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23175*FLEN/8, x13, x9, x10)

inst_7747:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39801fff; valaddr_reg:x12; val_offset:23178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23178*FLEN/8, x13, x9, x10)

inst_7748:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fff000; valaddr_reg:x12; val_offset:23181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23181*FLEN/8, x13, x9, x10)

inst_7749:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39800fff; valaddr_reg:x12; val_offset:23184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23184*FLEN/8, x13, x9, x10)

inst_7750:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fff800; valaddr_reg:x12; val_offset:23187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23187*FLEN/8, x13, x9, x10)

inst_7751:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x398007ff; valaddr_reg:x12; val_offset:23190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23190*FLEN/8, x13, x9, x10)

inst_7752:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fffc00; valaddr_reg:x12; val_offset:23193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23193*FLEN/8, x13, x9, x10)

inst_7753:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x398003ff; valaddr_reg:x12; val_offset:23196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23196*FLEN/8, x13, x9, x10)

inst_7754:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fffe00; valaddr_reg:x12; val_offset:23199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23199*FLEN/8, x13, x9, x10)

inst_7755:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x398001ff; valaddr_reg:x12; val_offset:23202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23202*FLEN/8, x13, x9, x10)

inst_7756:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffff00; valaddr_reg:x12; val_offset:23205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23205*FLEN/8, x13, x9, x10)

inst_7757:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x398000ff; valaddr_reg:x12; val_offset:23208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23208*FLEN/8, x13, x9, x10)

inst_7758:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffff80; valaddr_reg:x12; val_offset:23211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23211*FLEN/8, x13, x9, x10)

inst_7759:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3980007f; valaddr_reg:x12; val_offset:23214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23214*FLEN/8, x13, x9, x10)

inst_7760:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffffc0; valaddr_reg:x12; val_offset:23217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23217*FLEN/8, x13, x9, x10)

inst_7761:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3980003f; valaddr_reg:x12; val_offset:23220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23220*FLEN/8, x13, x9, x10)

inst_7762:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39ffffe0; valaddr_reg:x12; val_offset:23223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23223*FLEN/8, x13, x9, x10)

inst_7763:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3980001f; valaddr_reg:x12; val_offset:23226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23226*FLEN/8, x13, x9, x10)

inst_7764:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fffff0; valaddr_reg:x12; val_offset:23229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23229*FLEN/8, x13, x9, x10)

inst_7765:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3980000f; valaddr_reg:x12; val_offset:23232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23232*FLEN/8, x13, x9, x10)

inst_7766:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fffff8; valaddr_reg:x12; val_offset:23235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23235*FLEN/8, x13, x9, x10)

inst_7767:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39800007; valaddr_reg:x12; val_offset:23238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23238*FLEN/8, x13, x9, x10)

inst_7768:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fffffc; valaddr_reg:x12; val_offset:23241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23241*FLEN/8, x13, x9, x10)

inst_7769:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39800003; valaddr_reg:x12; val_offset:23244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23244*FLEN/8, x13, x9, x10)

inst_7770:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39fffffe; valaddr_reg:x12; val_offset:23247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23247*FLEN/8, x13, x9, x10)

inst_7771:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x73 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x39800001; valaddr_reg:x12; val_offset:23250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23250*FLEN/8, x13, x9, x10)

inst_7772:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:23253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23253*FLEN/8, x13, x9, x10)

inst_7773:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3f800007; valaddr_reg:x12; val_offset:23256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23256*FLEN/8, x13, x9, x10)

inst_7774:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:23259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23259*FLEN/8, x13, x9, x10)

inst_7775:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3f800003; valaddr_reg:x12; val_offset:23262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23262*FLEN/8, x13, x9, x10)

inst_7776:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:23265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23265*FLEN/8, x13, x9, x10)

inst_7777:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3f800001; valaddr_reg:x12; val_offset:23268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23268*FLEN/8, x13, x9, x10)

inst_7778:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:23271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23271*FLEN/8, x13, x9, x10)

inst_7779:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:23274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23274*FLEN/8, x13, x9, x10)

inst_7780:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3f999999; valaddr_reg:x12; val_offset:23277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23277*FLEN/8, x13, x9, x10)

inst_7781:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:23280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23280*FLEN/8, x13, x9, x10)

inst_7782:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:23283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23283*FLEN/8, x13, x9, x10)

inst_7783:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:23286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23286*FLEN/8, x13, x9, x10)

inst_7784:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:23289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23289*FLEN/8, x13, x9, x10)

inst_7785:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:23292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23292*FLEN/8, x13, x9, x10)

inst_7786:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:23295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23295*FLEN/8, x13, x9, x10)

inst_7787:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x4e511c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x1ed2dc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e4e511c; op2val:0x9ed2dc;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:23298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23298*FLEN/8, x13, x9, x10)

inst_7788:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a000000; valaddr_reg:x12; val_offset:23301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23301*FLEN/8, x13, x9, x10)

inst_7789:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fffff; valaddr_reg:x12; val_offset:23304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23304*FLEN/8, x13, x9, x10)

inst_7790:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a400000; valaddr_reg:x12; val_offset:23307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23307*FLEN/8, x13, x9, x10)

inst_7791:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a3fffff; valaddr_reg:x12; val_offset:23310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23310*FLEN/8, x13, x9, x10)

inst_7792:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a600000; valaddr_reg:x12; val_offset:23313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23313*FLEN/8, x13, x9, x10)

inst_7793:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a1fffff; valaddr_reg:x12; val_offset:23316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23316*FLEN/8, x13, x9, x10)

inst_7794:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a700000; valaddr_reg:x12; val_offset:23319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23319*FLEN/8, x13, x9, x10)

inst_7795:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a0fffff; valaddr_reg:x12; val_offset:23322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23322*FLEN/8, x13, x9, x10)

inst_7796:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a780000; valaddr_reg:x12; val_offset:23325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23325*FLEN/8, x13, x9, x10)

inst_7797:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a07ffff; valaddr_reg:x12; val_offset:23328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23328*FLEN/8, x13, x9, x10)

inst_7798:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7c0000; valaddr_reg:x12; val_offset:23331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23331*FLEN/8, x13, x9, x10)

inst_7799:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a03ffff; valaddr_reg:x12; val_offset:23334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23334*FLEN/8, x13, x9, x10)

inst_7800:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7e0000; valaddr_reg:x12; val_offset:23337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23337*FLEN/8, x13, x9, x10)

inst_7801:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a01ffff; valaddr_reg:x12; val_offset:23340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23340*FLEN/8, x13, x9, x10)

inst_7802:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7f0000; valaddr_reg:x12; val_offset:23343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23343*FLEN/8, x13, x9, x10)

inst_7803:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a00ffff; valaddr_reg:x12; val_offset:23346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23346*FLEN/8, x13, x9, x10)

inst_7804:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7f8000; valaddr_reg:x12; val_offset:23349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23349*FLEN/8, x13, x9, x10)

inst_7805:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a007fff; valaddr_reg:x12; val_offset:23352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23352*FLEN/8, x13, x9, x10)

inst_7806:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fc000; valaddr_reg:x12; val_offset:23355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23355*FLEN/8, x13, x9, x10)

inst_7807:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a003fff; valaddr_reg:x12; val_offset:23358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23358*FLEN/8, x13, x9, x10)

inst_7808:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fe000; valaddr_reg:x12; val_offset:23361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23361*FLEN/8, x13, x9, x10)

inst_7809:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a001fff; valaddr_reg:x12; val_offset:23364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23364*FLEN/8, x13, x9, x10)

inst_7810:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ff000; valaddr_reg:x12; val_offset:23367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23367*FLEN/8, x13, x9, x10)

inst_7811:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a000fff; valaddr_reg:x12; val_offset:23370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23370*FLEN/8, x13, x9, x10)

inst_7812:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ff800; valaddr_reg:x12; val_offset:23373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23373*FLEN/8, x13, x9, x10)

inst_7813:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a0007ff; valaddr_reg:x12; val_offset:23376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23376*FLEN/8, x13, x9, x10)

inst_7814:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ffc00; valaddr_reg:x12; val_offset:23379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23379*FLEN/8, x13, x9, x10)

inst_7815:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a0003ff; valaddr_reg:x12; val_offset:23382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23382*FLEN/8, x13, x9, x10)

inst_7816:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ffe00; valaddr_reg:x12; val_offset:23385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23385*FLEN/8, x13, x9, x10)

inst_7817:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a0001ff; valaddr_reg:x12; val_offset:23388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23388*FLEN/8, x13, x9, x10)

inst_7818:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fff00; valaddr_reg:x12; val_offset:23391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23391*FLEN/8, x13, x9, x10)

inst_7819:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a0000ff; valaddr_reg:x12; val_offset:23394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23394*FLEN/8, x13, x9, x10)

inst_7820:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fff80; valaddr_reg:x12; val_offset:23397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23397*FLEN/8, x13, x9, x10)

inst_7821:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a00007f; valaddr_reg:x12; val_offset:23400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23400*FLEN/8, x13, x9, x10)

inst_7822:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fffc0; valaddr_reg:x12; val_offset:23403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23403*FLEN/8, x13, x9, x10)

inst_7823:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a00003f; valaddr_reg:x12; val_offset:23406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23406*FLEN/8, x13, x9, x10)

inst_7824:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7fffe0; valaddr_reg:x12; val_offset:23409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23409*FLEN/8, x13, x9, x10)

inst_7825:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a00001f; valaddr_reg:x12; val_offset:23412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23412*FLEN/8, x13, x9, x10)

inst_7826:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ffff0; valaddr_reg:x12; val_offset:23415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23415*FLEN/8, x13, x9, x10)

inst_7827:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a00000f; valaddr_reg:x12; val_offset:23418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23418*FLEN/8, x13, x9, x10)

inst_7828:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ffff8; valaddr_reg:x12; val_offset:23421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23421*FLEN/8, x13, x9, x10)

inst_7829:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a000007; valaddr_reg:x12; val_offset:23424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23424*FLEN/8, x13, x9, x10)

inst_7830:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ffffc; valaddr_reg:x12; val_offset:23427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23427*FLEN/8, x13, x9, x10)

inst_7831:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a000003; valaddr_reg:x12; val_offset:23430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23430*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_61)
inst_7832:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a7ffffe; valaddr_reg:x12; val_offset:23433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23433*FLEN/8, x13, x9, x10)

inst_7833:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x74 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3a000001; valaddr_reg:x12; val_offset:23436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23436*FLEN/8, x13, x9, x10)

inst_7834:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:23439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23439*FLEN/8, x13, x9, x10)

inst_7835:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3f800007; valaddr_reg:x12; val_offset:23442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23442*FLEN/8, x13, x9, x10)

inst_7836:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:23445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23445*FLEN/8, x13, x9, x10)

inst_7837:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3f800003; valaddr_reg:x12; val_offset:23448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23448*FLEN/8, x13, x9, x10)

inst_7838:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:23451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23451*FLEN/8, x13, x9, x10)

inst_7839:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3f800001; valaddr_reg:x12; val_offset:23454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23454*FLEN/8, x13, x9, x10)

inst_7840:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:23457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23457*FLEN/8, x13, x9, x10)

inst_7841:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:23460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23460*FLEN/8, x13, x9, x10)

inst_7842:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3f999999; valaddr_reg:x12; val_offset:23463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23463*FLEN/8, x13, x9, x10)

inst_7843:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:23466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23466*FLEN/8, x13, x9, x10)

inst_7844:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:23469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23469*FLEN/8, x13, x9, x10)

inst_7845:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:23472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23472*FLEN/8, x13, x9, x10)

inst_7846:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:23475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23475*FLEN/8, x13, x9, x10)

inst_7847:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:23478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23478*FLEN/8, x13, x9, x10)

inst_7848:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:23481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23481*FLEN/8, x13, x9, x10)

inst_7849:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3583c7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f191448; op2val:0x3583c7;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:23484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23484*FLEN/8, x13, x9, x10)

inst_7850:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a800000; valaddr_reg:x12; val_offset:23487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23487*FLEN/8, x13, x9, x10)

inst_7851:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affffff; valaddr_reg:x12; val_offset:23490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23490*FLEN/8, x13, x9, x10)

inst_7852:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3ac00000; valaddr_reg:x12; val_offset:23493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23493*FLEN/8, x13, x9, x10)

inst_7853:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3abfffff; valaddr_reg:x12; val_offset:23496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23496*FLEN/8, x13, x9, x10)

inst_7854:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3ae00000; valaddr_reg:x12; val_offset:23499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23499*FLEN/8, x13, x9, x10)

inst_7855:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a9fffff; valaddr_reg:x12; val_offset:23502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23502*FLEN/8, x13, x9, x10)

inst_7856:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3af00000; valaddr_reg:x12; val_offset:23505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23505*FLEN/8, x13, x9, x10)

inst_7857:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a8fffff; valaddr_reg:x12; val_offset:23508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23508*FLEN/8, x13, x9, x10)

inst_7858:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3af80000; valaddr_reg:x12; val_offset:23511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23511*FLEN/8, x13, x9, x10)

inst_7859:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a87ffff; valaddr_reg:x12; val_offset:23514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23514*FLEN/8, x13, x9, x10)

inst_7860:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afc0000; valaddr_reg:x12; val_offset:23517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23517*FLEN/8, x13, x9, x10)

inst_7861:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a83ffff; valaddr_reg:x12; val_offset:23520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23520*FLEN/8, x13, x9, x10)

inst_7862:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afe0000; valaddr_reg:x12; val_offset:23523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23523*FLEN/8, x13, x9, x10)

inst_7863:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a81ffff; valaddr_reg:x12; val_offset:23526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23526*FLEN/8, x13, x9, x10)

inst_7864:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3aff0000; valaddr_reg:x12; val_offset:23529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23529*FLEN/8, x13, x9, x10)

inst_7865:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a80ffff; valaddr_reg:x12; val_offset:23532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23532*FLEN/8, x13, x9, x10)

inst_7866:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3aff8000; valaddr_reg:x12; val_offset:23535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23535*FLEN/8, x13, x9, x10)

inst_7867:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a807fff; valaddr_reg:x12; val_offset:23538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23538*FLEN/8, x13, x9, x10)

inst_7868:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affc000; valaddr_reg:x12; val_offset:23541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23541*FLEN/8, x13, x9, x10)

inst_7869:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a803fff; valaddr_reg:x12; val_offset:23544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23544*FLEN/8, x13, x9, x10)

inst_7870:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affe000; valaddr_reg:x12; val_offset:23547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23547*FLEN/8, x13, x9, x10)

inst_7871:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a801fff; valaddr_reg:x12; val_offset:23550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23550*FLEN/8, x13, x9, x10)

inst_7872:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afff000; valaddr_reg:x12; val_offset:23553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23553*FLEN/8, x13, x9, x10)

inst_7873:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a800fff; valaddr_reg:x12; val_offset:23556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23556*FLEN/8, x13, x9, x10)

inst_7874:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afff800; valaddr_reg:x12; val_offset:23559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23559*FLEN/8, x13, x9, x10)

inst_7875:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a8007ff; valaddr_reg:x12; val_offset:23562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23562*FLEN/8, x13, x9, x10)

inst_7876:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afffc00; valaddr_reg:x12; val_offset:23565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23565*FLEN/8, x13, x9, x10)

inst_7877:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a8003ff; valaddr_reg:x12; val_offset:23568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23568*FLEN/8, x13, x9, x10)

inst_7878:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afffe00; valaddr_reg:x12; val_offset:23571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23571*FLEN/8, x13, x9, x10)

inst_7879:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a8001ff; valaddr_reg:x12; val_offset:23574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23574*FLEN/8, x13, x9, x10)

inst_7880:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affff00; valaddr_reg:x12; val_offset:23577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23577*FLEN/8, x13, x9, x10)

inst_7881:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a8000ff; valaddr_reg:x12; val_offset:23580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23580*FLEN/8, x13, x9, x10)

inst_7882:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affff80; valaddr_reg:x12; val_offset:23583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23583*FLEN/8, x13, x9, x10)

inst_7883:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a80007f; valaddr_reg:x12; val_offset:23586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23586*FLEN/8, x13, x9, x10)

inst_7884:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affffc0; valaddr_reg:x12; val_offset:23589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23589*FLEN/8, x13, x9, x10)

inst_7885:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a80003f; valaddr_reg:x12; val_offset:23592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23592*FLEN/8, x13, x9, x10)

inst_7886:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3affffe0; valaddr_reg:x12; val_offset:23595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23595*FLEN/8, x13, x9, x10)

inst_7887:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a80001f; valaddr_reg:x12; val_offset:23598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23598*FLEN/8, x13, x9, x10)

inst_7888:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afffff0; valaddr_reg:x12; val_offset:23601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23601*FLEN/8, x13, x9, x10)

inst_7889:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a80000f; valaddr_reg:x12; val_offset:23604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23604*FLEN/8, x13, x9, x10)

inst_7890:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afffff8; valaddr_reg:x12; val_offset:23607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23607*FLEN/8, x13, x9, x10)

inst_7891:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a800007; valaddr_reg:x12; val_offset:23610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23610*FLEN/8, x13, x9, x10)

inst_7892:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afffffc; valaddr_reg:x12; val_offset:23613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23613*FLEN/8, x13, x9, x10)

inst_7893:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a800003; valaddr_reg:x12; val_offset:23616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23616*FLEN/8, x13, x9, x10)

inst_7894:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3afffffe; valaddr_reg:x12; val_offset:23619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23619*FLEN/8, x13, x9, x10)

inst_7895:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x75 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3a800001; valaddr_reg:x12; val_offset:23622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23622*FLEN/8, x13, x9, x10)

inst_7896:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:23625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23625*FLEN/8, x13, x9, x10)

inst_7897:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3f800007; valaddr_reg:x12; val_offset:23628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23628*FLEN/8, x13, x9, x10)

inst_7898:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:23631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23631*FLEN/8, x13, x9, x10)

inst_7899:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3f800003; valaddr_reg:x12; val_offset:23634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23634*FLEN/8, x13, x9, x10)

inst_7900:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:23637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23637*FLEN/8, x13, x9, x10)

inst_7901:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3f800001; valaddr_reg:x12; val_offset:23640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23640*FLEN/8, x13, x9, x10)

inst_7902:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:23643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23643*FLEN/8, x13, x9, x10)

inst_7903:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:23646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23646*FLEN/8, x13, x9, x10)

inst_7904:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3f999999; valaddr_reg:x12; val_offset:23649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23649*FLEN/8, x13, x9, x10)

inst_7905:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:23652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23652*FLEN/8, x13, x9, x10)

inst_7906:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:23655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23655*FLEN/8, x13, x9, x10)

inst_7907:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:23658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23658*FLEN/8, x13, x9, x10)

inst_7908:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:23661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23661*FLEN/8, x13, x9, x10)

inst_7909:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:23664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23664*FLEN/8, x13, x9, x10)

inst_7910:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:23667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23667*FLEN/8, x13, x9, x10)

inst_7911:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0dc7d6 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x671e1d and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e0dc7d6; op2val:0xe71e1d;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:23670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23670*FLEN/8, x13, x9, x10)

inst_7912:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b000000; valaddr_reg:x12; val_offset:23673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23673*FLEN/8, x13, x9, x10)

inst_7913:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fffff; valaddr_reg:x12; val_offset:23676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23676*FLEN/8, x13, x9, x10)

inst_7914:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b400000; valaddr_reg:x12; val_offset:23679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23679*FLEN/8, x13, x9, x10)

inst_7915:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b3fffff; valaddr_reg:x12; val_offset:23682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23682*FLEN/8, x13, x9, x10)

inst_7916:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b600000; valaddr_reg:x12; val_offset:23685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23685*FLEN/8, x13, x9, x10)

inst_7917:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b1fffff; valaddr_reg:x12; val_offset:23688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23688*FLEN/8, x13, x9, x10)

inst_7918:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b700000; valaddr_reg:x12; val_offset:23691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23691*FLEN/8, x13, x9, x10)

inst_7919:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b0fffff; valaddr_reg:x12; val_offset:23694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23694*FLEN/8, x13, x9, x10)

inst_7920:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b780000; valaddr_reg:x12; val_offset:23697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23697*FLEN/8, x13, x9, x10)

inst_7921:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b07ffff; valaddr_reg:x12; val_offset:23700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23700*FLEN/8, x13, x9, x10)

inst_7922:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7c0000; valaddr_reg:x12; val_offset:23703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23703*FLEN/8, x13, x9, x10)

inst_7923:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b03ffff; valaddr_reg:x12; val_offset:23706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23706*FLEN/8, x13, x9, x10)

inst_7924:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7e0000; valaddr_reg:x12; val_offset:23709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23709*FLEN/8, x13, x9, x10)

inst_7925:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b01ffff; valaddr_reg:x12; val_offset:23712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23712*FLEN/8, x13, x9, x10)

inst_7926:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7f0000; valaddr_reg:x12; val_offset:23715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23715*FLEN/8, x13, x9, x10)

inst_7927:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b00ffff; valaddr_reg:x12; val_offset:23718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23718*FLEN/8, x13, x9, x10)

inst_7928:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7f8000; valaddr_reg:x12; val_offset:23721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23721*FLEN/8, x13, x9, x10)

inst_7929:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b007fff; valaddr_reg:x12; val_offset:23724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23724*FLEN/8, x13, x9, x10)

inst_7930:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fc000; valaddr_reg:x12; val_offset:23727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23727*FLEN/8, x13, x9, x10)

inst_7931:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b003fff; valaddr_reg:x12; val_offset:23730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23730*FLEN/8, x13, x9, x10)

inst_7932:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fe000; valaddr_reg:x12; val_offset:23733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23733*FLEN/8, x13, x9, x10)

inst_7933:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b001fff; valaddr_reg:x12; val_offset:23736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23736*FLEN/8, x13, x9, x10)

inst_7934:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ff000; valaddr_reg:x12; val_offset:23739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23739*FLEN/8, x13, x9, x10)

inst_7935:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b000fff; valaddr_reg:x12; val_offset:23742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23742*FLEN/8, x13, x9, x10)

inst_7936:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ff800; valaddr_reg:x12; val_offset:23745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23745*FLEN/8, x13, x9, x10)

inst_7937:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b0007ff; valaddr_reg:x12; val_offset:23748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23748*FLEN/8, x13, x9, x10)

inst_7938:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ffc00; valaddr_reg:x12; val_offset:23751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23751*FLEN/8, x13, x9, x10)

inst_7939:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b0003ff; valaddr_reg:x12; val_offset:23754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23754*FLEN/8, x13, x9, x10)

inst_7940:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ffe00; valaddr_reg:x12; val_offset:23757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23757*FLEN/8, x13, x9, x10)

inst_7941:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b0001ff; valaddr_reg:x12; val_offset:23760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23760*FLEN/8, x13, x9, x10)

inst_7942:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fff00; valaddr_reg:x12; val_offset:23763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23763*FLEN/8, x13, x9, x10)

inst_7943:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b0000ff; valaddr_reg:x12; val_offset:23766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23766*FLEN/8, x13, x9, x10)

inst_7944:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fff80; valaddr_reg:x12; val_offset:23769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23769*FLEN/8, x13, x9, x10)

inst_7945:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b00007f; valaddr_reg:x12; val_offset:23772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23772*FLEN/8, x13, x9, x10)

inst_7946:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fffc0; valaddr_reg:x12; val_offset:23775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23775*FLEN/8, x13, x9, x10)

inst_7947:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b00003f; valaddr_reg:x12; val_offset:23778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23778*FLEN/8, x13, x9, x10)

inst_7948:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7fffe0; valaddr_reg:x12; val_offset:23781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23781*FLEN/8, x13, x9, x10)

inst_7949:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b00001f; valaddr_reg:x12; val_offset:23784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23784*FLEN/8, x13, x9, x10)

inst_7950:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ffff0; valaddr_reg:x12; val_offset:23787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23787*FLEN/8, x13, x9, x10)

inst_7951:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b00000f; valaddr_reg:x12; val_offset:23790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23790*FLEN/8, x13, x9, x10)

inst_7952:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ffff8; valaddr_reg:x12; val_offset:23793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23793*FLEN/8, x13, x9, x10)

inst_7953:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b000007; valaddr_reg:x12; val_offset:23796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23796*FLEN/8, x13, x9, x10)

inst_7954:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ffffc; valaddr_reg:x12; val_offset:23799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23799*FLEN/8, x13, x9, x10)

inst_7955:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b000003; valaddr_reg:x12; val_offset:23802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23802*FLEN/8, x13, x9, x10)

inst_7956:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b7ffffe; valaddr_reg:x12; val_offset:23805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23805*FLEN/8, x13, x9, x10)

inst_7957:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x76 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3b000001; valaddr_reg:x12; val_offset:23808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23808*FLEN/8, x13, x9, x10)

inst_7958:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:23811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23811*FLEN/8, x13, x9, x10)

inst_7959:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3f800007; valaddr_reg:x12; val_offset:23814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23814*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_62)
inst_7960:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:23817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23817*FLEN/8, x13, x9, x10)

inst_7961:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3f800003; valaddr_reg:x12; val_offset:23820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23820*FLEN/8, x13, x9, x10)

inst_7962:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:23823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23823*FLEN/8, x13, x9, x10)

inst_7963:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3f800001; valaddr_reg:x12; val_offset:23826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23826*FLEN/8, x13, x9, x10)

inst_7964:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:23829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23829*FLEN/8, x13, x9, x10)

inst_7965:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:23832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23832*FLEN/8, x13, x9, x10)

inst_7966:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3f999999; valaddr_reg:x12; val_offset:23835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23835*FLEN/8, x13, x9, x10)

inst_7967:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:23838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23838*FLEN/8, x13, x9, x10)

inst_7968:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:23841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23841*FLEN/8, x13, x9, x10)

inst_7969:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:23844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23844*FLEN/8, x13, x9, x10)

inst_7970:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:23847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23847*FLEN/8, x13, x9, x10)

inst_7971:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:23850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23850*FLEN/8, x13, x9, x10)

inst_7972:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:23853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23853*FLEN/8, x13, x9, x10)

inst_7973:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef037 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x12fb7a and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e5ef037; op2val:0x92fb7a;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:23856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23856*FLEN/8, x13, x9, x10)

inst_7974:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b800000; valaddr_reg:x12; val_offset:23859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23859*FLEN/8, x13, x9, x10)

inst_7975:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffffff; valaddr_reg:x12; val_offset:23862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23862*FLEN/8, x13, x9, x10)

inst_7976:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bc00000; valaddr_reg:x12; val_offset:23865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23865*FLEN/8, x13, x9, x10)

inst_7977:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bbfffff; valaddr_reg:x12; val_offset:23868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23868*FLEN/8, x13, x9, x10)

inst_7978:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3be00000; valaddr_reg:x12; val_offset:23871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23871*FLEN/8, x13, x9, x10)

inst_7979:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b9fffff; valaddr_reg:x12; val_offset:23874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23874*FLEN/8, x13, x9, x10)

inst_7980:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bf00000; valaddr_reg:x12; val_offset:23877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23877*FLEN/8, x13, x9, x10)

inst_7981:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b8fffff; valaddr_reg:x12; val_offset:23880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23880*FLEN/8, x13, x9, x10)

inst_7982:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bf80000; valaddr_reg:x12; val_offset:23883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23883*FLEN/8, x13, x9, x10)

inst_7983:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b87ffff; valaddr_reg:x12; val_offset:23886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23886*FLEN/8, x13, x9, x10)

inst_7984:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfc0000; valaddr_reg:x12; val_offset:23889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23889*FLEN/8, x13, x9, x10)

inst_7985:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b83ffff; valaddr_reg:x12; val_offset:23892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23892*FLEN/8, x13, x9, x10)

inst_7986:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfe0000; valaddr_reg:x12; val_offset:23895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23895*FLEN/8, x13, x9, x10)

inst_7987:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b81ffff; valaddr_reg:x12; val_offset:23898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23898*FLEN/8, x13, x9, x10)

inst_7988:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bff0000; valaddr_reg:x12; val_offset:23901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23901*FLEN/8, x13, x9, x10)

inst_7989:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b80ffff; valaddr_reg:x12; val_offset:23904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23904*FLEN/8, x13, x9, x10)

inst_7990:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bff8000; valaddr_reg:x12; val_offset:23907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23907*FLEN/8, x13, x9, x10)

inst_7991:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b807fff; valaddr_reg:x12; val_offset:23910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23910*FLEN/8, x13, x9, x10)

inst_7992:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffc000; valaddr_reg:x12; val_offset:23913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23913*FLEN/8, x13, x9, x10)

inst_7993:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b803fff; valaddr_reg:x12; val_offset:23916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23916*FLEN/8, x13, x9, x10)

inst_7994:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffe000; valaddr_reg:x12; val_offset:23919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23919*FLEN/8, x13, x9, x10)

inst_7995:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b801fff; valaddr_reg:x12; val_offset:23922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23922*FLEN/8, x13, x9, x10)

inst_7996:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfff000; valaddr_reg:x12; val_offset:23925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23925*FLEN/8, x13, x9, x10)

inst_7997:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b800fff; valaddr_reg:x12; val_offset:23928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23928*FLEN/8, x13, x9, x10)

inst_7998:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfff800; valaddr_reg:x12; val_offset:23931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23931*FLEN/8, x13, x9, x10)

inst_7999:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b8007ff; valaddr_reg:x12; val_offset:23934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23934*FLEN/8, x13, x9, x10)

inst_8000:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfffc00; valaddr_reg:x12; val_offset:23937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23937*FLEN/8, x13, x9, x10)

inst_8001:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b8003ff; valaddr_reg:x12; val_offset:23940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23940*FLEN/8, x13, x9, x10)

inst_8002:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfffe00; valaddr_reg:x12; val_offset:23943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23943*FLEN/8, x13, x9, x10)

inst_8003:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b8001ff; valaddr_reg:x12; val_offset:23946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23946*FLEN/8, x13, x9, x10)

inst_8004:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffff00; valaddr_reg:x12; val_offset:23949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23949*FLEN/8, x13, x9, x10)

inst_8005:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b8000ff; valaddr_reg:x12; val_offset:23952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23952*FLEN/8, x13, x9, x10)

inst_8006:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffff80; valaddr_reg:x12; val_offset:23955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23955*FLEN/8, x13, x9, x10)

inst_8007:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b80007f; valaddr_reg:x12; val_offset:23958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23958*FLEN/8, x13, x9, x10)

inst_8008:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffffc0; valaddr_reg:x12; val_offset:23961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23961*FLEN/8, x13, x9, x10)

inst_8009:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b80003f; valaddr_reg:x12; val_offset:23964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23964*FLEN/8, x13, x9, x10)

inst_8010:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bffffe0; valaddr_reg:x12; val_offset:23967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23967*FLEN/8, x13, x9, x10)

inst_8011:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b80001f; valaddr_reg:x12; val_offset:23970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23970*FLEN/8, x13, x9, x10)

inst_8012:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfffff0; valaddr_reg:x12; val_offset:23973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23973*FLEN/8, x13, x9, x10)

inst_8013:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b80000f; valaddr_reg:x12; val_offset:23976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23976*FLEN/8, x13, x9, x10)

inst_8014:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfffff8; valaddr_reg:x12; val_offset:23979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23979*FLEN/8, x13, x9, x10)

inst_8015:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b800007; valaddr_reg:x12; val_offset:23982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23982*FLEN/8, x13, x9, x10)

inst_8016:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfffffc; valaddr_reg:x12; val_offset:23985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23985*FLEN/8, x13, x9, x10)

inst_8017:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b800003; valaddr_reg:x12; val_offset:23988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23988*FLEN/8, x13, x9, x10)

inst_8018:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3bfffffe; valaddr_reg:x12; val_offset:23991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23991*FLEN/8, x13, x9, x10)

inst_8019:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x77 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3b800001; valaddr_reg:x12; val_offset:23994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23994*FLEN/8, x13, x9, x10)

inst_8020:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:23997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 23997*FLEN/8, x13, x9, x10)

inst_8021:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3f800007; valaddr_reg:x12; val_offset:24000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24000*FLEN/8, x13, x9, x10)

inst_8022:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:24003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24003*FLEN/8, x13, x9, x10)

inst_8023:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3f800003; valaddr_reg:x12; val_offset:24006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24006*FLEN/8, x13, x9, x10)

inst_8024:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:24009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24009*FLEN/8, x13, x9, x10)

inst_8025:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3f800001; valaddr_reg:x12; val_offset:24012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24012*FLEN/8, x13, x9, x10)

inst_8026:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:24015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24015*FLEN/8, x13, x9, x10)

inst_8027:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:24018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24018*FLEN/8, x13, x9, x10)

inst_8028:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3f999999; valaddr_reg:x12; val_offset:24021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24021*FLEN/8, x13, x9, x10)

inst_8029:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:24024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24024*FLEN/8, x13, x9, x10)

inst_8030:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:24027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24027*FLEN/8, x13, x9, x10)

inst_8031:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:24030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24030*FLEN/8, x13, x9, x10)

inst_8032:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:24033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24033*FLEN/8, x13, x9, x10)

inst_8033:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:24036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24036*FLEN/8, x13, x9, x10)

inst_8034:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:24039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24039*FLEN/8, x13, x9, x10)

inst_8035:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x009e00 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x7ec583 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e009e00; op2val:0xfec583;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:24042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24042*FLEN/8, x13, x9, x10)

inst_8036:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c000000; valaddr_reg:x12; val_offset:24045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24045*FLEN/8, x13, x9, x10)

inst_8037:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fffff; valaddr_reg:x12; val_offset:24048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24048*FLEN/8, x13, x9, x10)

inst_8038:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c400000; valaddr_reg:x12; val_offset:24051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24051*FLEN/8, x13, x9, x10)

inst_8039:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c3fffff; valaddr_reg:x12; val_offset:24054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24054*FLEN/8, x13, x9, x10)

inst_8040:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c600000; valaddr_reg:x12; val_offset:24057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24057*FLEN/8, x13, x9, x10)

inst_8041:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c1fffff; valaddr_reg:x12; val_offset:24060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24060*FLEN/8, x13, x9, x10)

inst_8042:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c700000; valaddr_reg:x12; val_offset:24063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24063*FLEN/8, x13, x9, x10)

inst_8043:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c0fffff; valaddr_reg:x12; val_offset:24066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24066*FLEN/8, x13, x9, x10)

inst_8044:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c780000; valaddr_reg:x12; val_offset:24069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24069*FLEN/8, x13, x9, x10)

inst_8045:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c07ffff; valaddr_reg:x12; val_offset:24072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24072*FLEN/8, x13, x9, x10)

inst_8046:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7c0000; valaddr_reg:x12; val_offset:24075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24075*FLEN/8, x13, x9, x10)

inst_8047:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c03ffff; valaddr_reg:x12; val_offset:24078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24078*FLEN/8, x13, x9, x10)

inst_8048:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7e0000; valaddr_reg:x12; val_offset:24081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24081*FLEN/8, x13, x9, x10)

inst_8049:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c01ffff; valaddr_reg:x12; val_offset:24084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24084*FLEN/8, x13, x9, x10)

inst_8050:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7f0000; valaddr_reg:x12; val_offset:24087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24087*FLEN/8, x13, x9, x10)

inst_8051:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c00ffff; valaddr_reg:x12; val_offset:24090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24090*FLEN/8, x13, x9, x10)

inst_8052:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7f8000; valaddr_reg:x12; val_offset:24093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24093*FLEN/8, x13, x9, x10)

inst_8053:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c007fff; valaddr_reg:x12; val_offset:24096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24096*FLEN/8, x13, x9, x10)

inst_8054:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fc000; valaddr_reg:x12; val_offset:24099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24099*FLEN/8, x13, x9, x10)

inst_8055:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c003fff; valaddr_reg:x12; val_offset:24102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24102*FLEN/8, x13, x9, x10)

inst_8056:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fe000; valaddr_reg:x12; val_offset:24105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24105*FLEN/8, x13, x9, x10)

inst_8057:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c001fff; valaddr_reg:x12; val_offset:24108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24108*FLEN/8, x13, x9, x10)

inst_8058:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ff000; valaddr_reg:x12; val_offset:24111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24111*FLEN/8, x13, x9, x10)

inst_8059:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c000fff; valaddr_reg:x12; val_offset:24114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24114*FLEN/8, x13, x9, x10)

inst_8060:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ff800; valaddr_reg:x12; val_offset:24117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24117*FLEN/8, x13, x9, x10)

inst_8061:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c0007ff; valaddr_reg:x12; val_offset:24120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24120*FLEN/8, x13, x9, x10)

inst_8062:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ffc00; valaddr_reg:x12; val_offset:24123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24123*FLEN/8, x13, x9, x10)

inst_8063:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c0003ff; valaddr_reg:x12; val_offset:24126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24126*FLEN/8, x13, x9, x10)

inst_8064:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ffe00; valaddr_reg:x12; val_offset:24129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24129*FLEN/8, x13, x9, x10)

inst_8065:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c0001ff; valaddr_reg:x12; val_offset:24132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24132*FLEN/8, x13, x9, x10)

inst_8066:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fff00; valaddr_reg:x12; val_offset:24135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24135*FLEN/8, x13, x9, x10)

inst_8067:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c0000ff; valaddr_reg:x12; val_offset:24138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24138*FLEN/8, x13, x9, x10)

inst_8068:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fff80; valaddr_reg:x12; val_offset:24141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24141*FLEN/8, x13, x9, x10)

inst_8069:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c00007f; valaddr_reg:x12; val_offset:24144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24144*FLEN/8, x13, x9, x10)

inst_8070:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fffc0; valaddr_reg:x12; val_offset:24147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24147*FLEN/8, x13, x9, x10)

inst_8071:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c00003f; valaddr_reg:x12; val_offset:24150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24150*FLEN/8, x13, x9, x10)

inst_8072:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7fffe0; valaddr_reg:x12; val_offset:24153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24153*FLEN/8, x13, x9, x10)

inst_8073:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c00001f; valaddr_reg:x12; val_offset:24156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24156*FLEN/8, x13, x9, x10)

inst_8074:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ffff0; valaddr_reg:x12; val_offset:24159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24159*FLEN/8, x13, x9, x10)

inst_8075:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c00000f; valaddr_reg:x12; val_offset:24162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24162*FLEN/8, x13, x9, x10)

inst_8076:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ffff8; valaddr_reg:x12; val_offset:24165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24165*FLEN/8, x13, x9, x10)

inst_8077:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c000007; valaddr_reg:x12; val_offset:24168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24168*FLEN/8, x13, x9, x10)

inst_8078:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ffffc; valaddr_reg:x12; val_offset:24171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24171*FLEN/8, x13, x9, x10)

inst_8079:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c000003; valaddr_reg:x12; val_offset:24174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24174*FLEN/8, x13, x9, x10)

inst_8080:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c7ffffe; valaddr_reg:x12; val_offset:24177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24177*FLEN/8, x13, x9, x10)

inst_8081:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x78 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3c000001; valaddr_reg:x12; val_offset:24180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24180*FLEN/8, x13, x9, x10)

inst_8082:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:24183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24183*FLEN/8, x13, x9, x10)

inst_8083:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3f800007; valaddr_reg:x12; val_offset:24186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24186*FLEN/8, x13, x9, x10)

inst_8084:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:24189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24189*FLEN/8, x13, x9, x10)

inst_8085:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3f800003; valaddr_reg:x12; val_offset:24192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24192*FLEN/8, x13, x9, x10)

inst_8086:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:24195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24195*FLEN/8, x13, x9, x10)

inst_8087:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3f800001; valaddr_reg:x12; val_offset:24198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24198*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_63)
inst_8088:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:24201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24201*FLEN/8, x13, x9, x10)

inst_8089:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:24204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24204*FLEN/8, x13, x9, x10)

inst_8090:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3f999999; valaddr_reg:x12; val_offset:24207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24207*FLEN/8, x13, x9, x10)

inst_8091:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:24210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24210*FLEN/8, x13, x9, x10)

inst_8092:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:24213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24213*FLEN/8, x13, x9, x10)

inst_8093:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:24216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24216*FLEN/8, x13, x9, x10)

inst_8094:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:24219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24219*FLEN/8, x13, x9, x10)

inst_8095:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:24222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24222*FLEN/8, x13, x9, x10)

inst_8096:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:24225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24225*FLEN/8, x13, x9, x10)

inst_8097:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x440187 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x272db7 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e440187; op2val:0xa72db7;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:24228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24228*FLEN/8, x13, x9, x10)

inst_8098:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c800000; valaddr_reg:x12; val_offset:24231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24231*FLEN/8, x13, x9, x10)

inst_8099:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffffff; valaddr_reg:x12; val_offset:24234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24234*FLEN/8, x13, x9, x10)

inst_8100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cc00000; valaddr_reg:x12; val_offset:24237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24237*FLEN/8, x13, x9, x10)

inst_8101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cbfffff; valaddr_reg:x12; val_offset:24240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24240*FLEN/8, x13, x9, x10)

inst_8102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3ce00000; valaddr_reg:x12; val_offset:24243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24243*FLEN/8, x13, x9, x10)

inst_8103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c9fffff; valaddr_reg:x12; val_offset:24246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24246*FLEN/8, x13, x9, x10)

inst_8104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cf00000; valaddr_reg:x12; val_offset:24249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24249*FLEN/8, x13, x9, x10)

inst_8105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c8fffff; valaddr_reg:x12; val_offset:24252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24252*FLEN/8, x13, x9, x10)

inst_8106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cf80000; valaddr_reg:x12; val_offset:24255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24255*FLEN/8, x13, x9, x10)

inst_8107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c87ffff; valaddr_reg:x12; val_offset:24258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24258*FLEN/8, x13, x9, x10)

inst_8108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfc0000; valaddr_reg:x12; val_offset:24261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24261*FLEN/8, x13, x9, x10)

inst_8109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c83ffff; valaddr_reg:x12; val_offset:24264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24264*FLEN/8, x13, x9, x10)

inst_8110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfe0000; valaddr_reg:x12; val_offset:24267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24267*FLEN/8, x13, x9, x10)

inst_8111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c81ffff; valaddr_reg:x12; val_offset:24270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24270*FLEN/8, x13, x9, x10)

inst_8112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cff0000; valaddr_reg:x12; val_offset:24273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24273*FLEN/8, x13, x9, x10)

inst_8113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c80ffff; valaddr_reg:x12; val_offset:24276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24276*FLEN/8, x13, x9, x10)

inst_8114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cff8000; valaddr_reg:x12; val_offset:24279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24279*FLEN/8, x13, x9, x10)

inst_8115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c807fff; valaddr_reg:x12; val_offset:24282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24282*FLEN/8, x13, x9, x10)

inst_8116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffc000; valaddr_reg:x12; val_offset:24285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24285*FLEN/8, x13, x9, x10)

inst_8117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c803fff; valaddr_reg:x12; val_offset:24288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24288*FLEN/8, x13, x9, x10)

inst_8118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffe000; valaddr_reg:x12; val_offset:24291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24291*FLEN/8, x13, x9, x10)

inst_8119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c801fff; valaddr_reg:x12; val_offset:24294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24294*FLEN/8, x13, x9, x10)

inst_8120:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfff000; valaddr_reg:x12; val_offset:24297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24297*FLEN/8, x13, x9, x10)

inst_8121:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c800fff; valaddr_reg:x12; val_offset:24300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24300*FLEN/8, x13, x9, x10)

inst_8122:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfff800; valaddr_reg:x12; val_offset:24303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24303*FLEN/8, x13, x9, x10)

inst_8123:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c8007ff; valaddr_reg:x12; val_offset:24306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24306*FLEN/8, x13, x9, x10)

inst_8124:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfffc00; valaddr_reg:x12; val_offset:24309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24309*FLEN/8, x13, x9, x10)

inst_8125:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c8003ff; valaddr_reg:x12; val_offset:24312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24312*FLEN/8, x13, x9, x10)

inst_8126:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfffe00; valaddr_reg:x12; val_offset:24315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24315*FLEN/8, x13, x9, x10)

inst_8127:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c8001ff; valaddr_reg:x12; val_offset:24318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24318*FLEN/8, x13, x9, x10)

inst_8128:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffff00; valaddr_reg:x12; val_offset:24321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24321*FLEN/8, x13, x9, x10)

inst_8129:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c8000ff; valaddr_reg:x12; val_offset:24324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24324*FLEN/8, x13, x9, x10)

inst_8130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffff80; valaddr_reg:x12; val_offset:24327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24327*FLEN/8, x13, x9, x10)

inst_8131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c80007f; valaddr_reg:x12; val_offset:24330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24330*FLEN/8, x13, x9, x10)

inst_8132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffffc0; valaddr_reg:x12; val_offset:24333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24333*FLEN/8, x13, x9, x10)

inst_8133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c80003f; valaddr_reg:x12; val_offset:24336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24336*FLEN/8, x13, x9, x10)

inst_8134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cffffe0; valaddr_reg:x12; val_offset:24339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24339*FLEN/8, x13, x9, x10)

inst_8135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c80001f; valaddr_reg:x12; val_offset:24342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24342*FLEN/8, x13, x9, x10)

inst_8136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfffff0; valaddr_reg:x12; val_offset:24345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24345*FLEN/8, x13, x9, x10)

inst_8137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c80000f; valaddr_reg:x12; val_offset:24348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24348*FLEN/8, x13, x9, x10)

inst_8138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfffff8; valaddr_reg:x12; val_offset:24351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24351*FLEN/8, x13, x9, x10)

inst_8139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c800007; valaddr_reg:x12; val_offset:24354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24354*FLEN/8, x13, x9, x10)

inst_8140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfffffc; valaddr_reg:x12; val_offset:24357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24357*FLEN/8, x13, x9, x10)

inst_8141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c800003; valaddr_reg:x12; val_offset:24360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24360*FLEN/8, x13, x9, x10)

inst_8142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3cfffffe; valaddr_reg:x12; val_offset:24363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24363*FLEN/8, x13, x9, x10)

inst_8143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3c800001; valaddr_reg:x12; val_offset:24366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24366*FLEN/8, x13, x9, x10)

inst_8144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:24369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24369*FLEN/8, x13, x9, x10)

inst_8145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3f800007; valaddr_reg:x12; val_offset:24372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24372*FLEN/8, x13, x9, x10)

inst_8146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:24375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24375*FLEN/8, x13, x9, x10)

inst_8147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3f800003; valaddr_reg:x12; val_offset:24378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24378*FLEN/8, x13, x9, x10)

inst_8148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:24381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24381*FLEN/8, x13, x9, x10)

inst_8149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3f800001; valaddr_reg:x12; val_offset:24384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24384*FLEN/8, x13, x9, x10)

inst_8150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:24387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24387*FLEN/8, x13, x9, x10)

inst_8151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:24390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24390*FLEN/8, x13, x9, x10)

inst_8152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3f999999; valaddr_reg:x12; val_offset:24393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24393*FLEN/8, x13, x9, x10)

inst_8153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:24396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24396*FLEN/8, x13, x9, x10)

inst_8154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:24399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24399*FLEN/8, x13, x9, x10)

inst_8155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:24402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24402*FLEN/8, x13, x9, x10)

inst_8156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:24405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24405*FLEN/8, x13, x9, x10)

inst_8157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:24408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24408*FLEN/8, x13, x9, x10)

inst_8158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:24411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24411*FLEN/8, x13, x9, x10)

inst_8159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x36c69e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2cd1e6 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f36c69e; op2val:0x2cd1e6;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:24414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24414*FLEN/8, x13, x9, x10)

inst_8160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d000000; valaddr_reg:x12; val_offset:24417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24417*FLEN/8, x13, x9, x10)

inst_8161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fffff; valaddr_reg:x12; val_offset:24420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24420*FLEN/8, x13, x9, x10)

inst_8162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d400000; valaddr_reg:x12; val_offset:24423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24423*FLEN/8, x13, x9, x10)

inst_8163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d3fffff; valaddr_reg:x12; val_offset:24426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24426*FLEN/8, x13, x9, x10)

inst_8164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d600000; valaddr_reg:x12; val_offset:24429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24429*FLEN/8, x13, x9, x10)

inst_8165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d1fffff; valaddr_reg:x12; val_offset:24432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24432*FLEN/8, x13, x9, x10)

inst_8166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d700000; valaddr_reg:x12; val_offset:24435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24435*FLEN/8, x13, x9, x10)

inst_8167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d0fffff; valaddr_reg:x12; val_offset:24438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24438*FLEN/8, x13, x9, x10)

inst_8168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d780000; valaddr_reg:x12; val_offset:24441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24441*FLEN/8, x13, x9, x10)

inst_8169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d07ffff; valaddr_reg:x12; val_offset:24444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24444*FLEN/8, x13, x9, x10)

inst_8170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7c0000; valaddr_reg:x12; val_offset:24447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24447*FLEN/8, x13, x9, x10)

inst_8171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d03ffff; valaddr_reg:x12; val_offset:24450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24450*FLEN/8, x13, x9, x10)

inst_8172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7e0000; valaddr_reg:x12; val_offset:24453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24453*FLEN/8, x13, x9, x10)

inst_8173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d01ffff; valaddr_reg:x12; val_offset:24456*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24456*FLEN/8, x13, x9, x10)

inst_8174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7f0000; valaddr_reg:x12; val_offset:24459*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24459*FLEN/8, x13, x9, x10)

inst_8175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d00ffff; valaddr_reg:x12; val_offset:24462*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24462*FLEN/8, x13, x9, x10)

inst_8176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7f8000; valaddr_reg:x12; val_offset:24465*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24465*FLEN/8, x13, x9, x10)

inst_8177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d007fff; valaddr_reg:x12; val_offset:24468*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24468*FLEN/8, x13, x9, x10)

inst_8178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fc000; valaddr_reg:x12; val_offset:24471*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24471*FLEN/8, x13, x9, x10)

inst_8179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d003fff; valaddr_reg:x12; val_offset:24474*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24474*FLEN/8, x13, x9, x10)

inst_8180:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fe000; valaddr_reg:x12; val_offset:24477*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24477*FLEN/8, x13, x9, x10)

inst_8181:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d001fff; valaddr_reg:x12; val_offset:24480*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24480*FLEN/8, x13, x9, x10)

inst_8182:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ff000; valaddr_reg:x12; val_offset:24483*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24483*FLEN/8, x13, x9, x10)

inst_8183:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d000fff; valaddr_reg:x12; val_offset:24486*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24486*FLEN/8, x13, x9, x10)

inst_8184:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ff800; valaddr_reg:x12; val_offset:24489*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24489*FLEN/8, x13, x9, x10)

inst_8185:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d0007ff; valaddr_reg:x12; val_offset:24492*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24492*FLEN/8, x13, x9, x10)

inst_8186:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ffc00; valaddr_reg:x12; val_offset:24495*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24495*FLEN/8, x13, x9, x10)

inst_8187:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d0003ff; valaddr_reg:x12; val_offset:24498*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24498*FLEN/8, x13, x9, x10)

inst_8188:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ffe00; valaddr_reg:x12; val_offset:24501*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24501*FLEN/8, x13, x9, x10)

inst_8189:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d0001ff; valaddr_reg:x12; val_offset:24504*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24504*FLEN/8, x13, x9, x10)

inst_8190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fff00; valaddr_reg:x12; val_offset:24507*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24507*FLEN/8, x13, x9, x10)

inst_8191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d0000ff; valaddr_reg:x12; val_offset:24510*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24510*FLEN/8, x13, x9, x10)

inst_8192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fff80; valaddr_reg:x12; val_offset:24513*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24513*FLEN/8, x13, x9, x10)

inst_8193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d00007f; valaddr_reg:x12; val_offset:24516*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24516*FLEN/8, x13, x9, x10)

inst_8194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fffc0; valaddr_reg:x12; val_offset:24519*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24519*FLEN/8, x13, x9, x10)

inst_8195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d00003f; valaddr_reg:x12; val_offset:24522*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24522*FLEN/8, x13, x9, x10)

inst_8196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7fffe0; valaddr_reg:x12; val_offset:24525*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24525*FLEN/8, x13, x9, x10)

inst_8197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d00001f; valaddr_reg:x12; val_offset:24528*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24528*FLEN/8, x13, x9, x10)

inst_8198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ffff0; valaddr_reg:x12; val_offset:24531*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24531*FLEN/8, x13, x9, x10)

inst_8199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d00000f; valaddr_reg:x12; val_offset:24534*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24534*FLEN/8, x13, x9, x10)

inst_8200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ffff8; valaddr_reg:x12; val_offset:24537*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24537*FLEN/8, x13, x9, x10)

inst_8201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d000007; valaddr_reg:x12; val_offset:24540*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24540*FLEN/8, x13, x9, x10)

inst_8202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ffffc; valaddr_reg:x12; val_offset:24543*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24543*FLEN/8, x13, x9, x10)

inst_8203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d000003; valaddr_reg:x12; val_offset:24546*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24546*FLEN/8, x13, x9, x10)

inst_8204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d7ffffe; valaddr_reg:x12; val_offset:24549*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24549*FLEN/8, x13, x9, x10)

inst_8205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7a and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3d000001; valaddr_reg:x12; val_offset:24552*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24552*FLEN/8, x13, x9, x10)

inst_8206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:24555*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24555*FLEN/8, x13, x9, x10)

inst_8207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3f800007; valaddr_reg:x12; val_offset:24558*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24558*FLEN/8, x13, x9, x10)

inst_8208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:24561*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24561*FLEN/8, x13, x9, x10)

inst_8209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3f800003; valaddr_reg:x12; val_offset:24564*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24564*FLEN/8, x13, x9, x10)

inst_8210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:24567*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24567*FLEN/8, x13, x9, x10)

inst_8211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3f800001; valaddr_reg:x12; val_offset:24570*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24570*FLEN/8, x13, x9, x10)

inst_8212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:24573*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24573*FLEN/8, x13, x9, x10)

inst_8213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:24576*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24576*FLEN/8, x13, x9, x10)

inst_8214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3f999999; valaddr_reg:x12; val_offset:24579*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24579*FLEN/8, x13, x9, x10)

inst_8215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:24582*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24582*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_64)
inst_8216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:24585*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24585*FLEN/8, x13, x9, x10)

inst_8217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:24588*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24588*FLEN/8, x13, x9, x10)

inst_8218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:24591*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24591*FLEN/8, x13, x9, x10)

inst_8219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:24594*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24594*FLEN/8, x13, x9, x10)

inst_8220:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:24597*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24597*FLEN/8, x13, x9, x10)

inst_8221:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c27f5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x40f9c2 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7efc27f5; op2val:0x40f9c2;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:24600*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24600*FLEN/8, x13, x9, x10)

inst_8222:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d800000; valaddr_reg:x12; val_offset:24603*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24603*FLEN/8, x13, x9, x10)

inst_8223:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffffff; valaddr_reg:x12; val_offset:24606*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24606*FLEN/8, x13, x9, x10)

inst_8224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dc00000; valaddr_reg:x12; val_offset:24609*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24609*FLEN/8, x13, x9, x10)

inst_8225:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dbfffff; valaddr_reg:x12; val_offset:24612*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24612*FLEN/8, x13, x9, x10)

inst_8226:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3de00000; valaddr_reg:x12; val_offset:24615*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24615*FLEN/8, x13, x9, x10)

inst_8227:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d9fffff; valaddr_reg:x12; val_offset:24618*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24618*FLEN/8, x13, x9, x10)

inst_8228:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3df00000; valaddr_reg:x12; val_offset:24621*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24621*FLEN/8, x13, x9, x10)

inst_8229:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d8fffff; valaddr_reg:x12; val_offset:24624*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24624*FLEN/8, x13, x9, x10)

inst_8230:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3df80000; valaddr_reg:x12; val_offset:24627*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24627*FLEN/8, x13, x9, x10)

inst_8231:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d87ffff; valaddr_reg:x12; val_offset:24630*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24630*FLEN/8, x13, x9, x10)

inst_8232:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfc0000; valaddr_reg:x12; val_offset:24633*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24633*FLEN/8, x13, x9, x10)

inst_8233:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d83ffff; valaddr_reg:x12; val_offset:24636*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24636*FLEN/8, x13, x9, x10)

inst_8234:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfe0000; valaddr_reg:x12; val_offset:24639*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24639*FLEN/8, x13, x9, x10)

inst_8235:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d81ffff; valaddr_reg:x12; val_offset:24642*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24642*FLEN/8, x13, x9, x10)

inst_8236:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dff0000; valaddr_reg:x12; val_offset:24645*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24645*FLEN/8, x13, x9, x10)

inst_8237:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d80ffff; valaddr_reg:x12; val_offset:24648*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24648*FLEN/8, x13, x9, x10)

inst_8238:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dff8000; valaddr_reg:x12; val_offset:24651*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24651*FLEN/8, x13, x9, x10)

inst_8239:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d807fff; valaddr_reg:x12; val_offset:24654*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24654*FLEN/8, x13, x9, x10)

inst_8240:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffc000; valaddr_reg:x12; val_offset:24657*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24657*FLEN/8, x13, x9, x10)

inst_8241:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d803fff; valaddr_reg:x12; val_offset:24660*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24660*FLEN/8, x13, x9, x10)

inst_8242:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffe000; valaddr_reg:x12; val_offset:24663*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24663*FLEN/8, x13, x9, x10)

inst_8243:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d801fff; valaddr_reg:x12; val_offset:24666*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24666*FLEN/8, x13, x9, x10)

inst_8244:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfff000; valaddr_reg:x12; val_offset:24669*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24669*FLEN/8, x13, x9, x10)

inst_8245:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d800fff; valaddr_reg:x12; val_offset:24672*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24672*FLEN/8, x13, x9, x10)

inst_8246:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfff800; valaddr_reg:x12; val_offset:24675*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24675*FLEN/8, x13, x9, x10)

inst_8247:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d8007ff; valaddr_reg:x12; val_offset:24678*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24678*FLEN/8, x13, x9, x10)

inst_8248:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfffc00; valaddr_reg:x12; val_offset:24681*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24681*FLEN/8, x13, x9, x10)

inst_8249:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d8003ff; valaddr_reg:x12; val_offset:24684*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24684*FLEN/8, x13, x9, x10)

inst_8250:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfffe00; valaddr_reg:x12; val_offset:24687*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24687*FLEN/8, x13, x9, x10)

inst_8251:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d8001ff; valaddr_reg:x12; val_offset:24690*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24690*FLEN/8, x13, x9, x10)

inst_8252:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffff00; valaddr_reg:x12; val_offset:24693*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24693*FLEN/8, x13, x9, x10)

inst_8253:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d8000ff; valaddr_reg:x12; val_offset:24696*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24696*FLEN/8, x13, x9, x10)

inst_8254:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffff80; valaddr_reg:x12; val_offset:24699*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24699*FLEN/8, x13, x9, x10)

inst_8255:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d80007f; valaddr_reg:x12; val_offset:24702*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24702*FLEN/8, x13, x9, x10)

inst_8256:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffffc0; valaddr_reg:x12; val_offset:24705*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24705*FLEN/8, x13, x9, x10)

inst_8257:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d80003f; valaddr_reg:x12; val_offset:24708*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24708*FLEN/8, x13, x9, x10)

inst_8258:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dffffe0; valaddr_reg:x12; val_offset:24711*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24711*FLEN/8, x13, x9, x10)

inst_8259:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d80001f; valaddr_reg:x12; val_offset:24714*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24714*FLEN/8, x13, x9, x10)

inst_8260:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfffff0; valaddr_reg:x12; val_offset:24717*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24717*FLEN/8, x13, x9, x10)

inst_8261:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d80000f; valaddr_reg:x12; val_offset:24720*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24720*FLEN/8, x13, x9, x10)

inst_8262:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfffff8; valaddr_reg:x12; val_offset:24723*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24723*FLEN/8, x13, x9, x10)

inst_8263:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d800007; valaddr_reg:x12; val_offset:24726*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24726*FLEN/8, x13, x9, x10)

inst_8264:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfffffc; valaddr_reg:x12; val_offset:24729*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24729*FLEN/8, x13, x9, x10)

inst_8265:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d800003; valaddr_reg:x12; val_offset:24732*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24732*FLEN/8, x13, x9, x10)

inst_8266:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3dfffffe; valaddr_reg:x12; val_offset:24735*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24735*FLEN/8, x13, x9, x10)

inst_8267:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7b and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3d800001; valaddr_reg:x12; val_offset:24738*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24738*FLEN/8, x13, x9, x10)

inst_8268:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:24741*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24741*FLEN/8, x13, x9, x10)

inst_8269:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3f800007; valaddr_reg:x12; val_offset:24744*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24744*FLEN/8, x13, x9, x10)

inst_8270:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:24747*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24747*FLEN/8, x13, x9, x10)

inst_8271:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3f800003; valaddr_reg:x12; val_offset:24750*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24750*FLEN/8, x13, x9, x10)

inst_8272:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:24753*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24753*FLEN/8, x13, x9, x10)

inst_8273:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3f800001; valaddr_reg:x12; val_offset:24756*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24756*FLEN/8, x13, x9, x10)

inst_8274:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:24759*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24759*FLEN/8, x13, x9, x10)

inst_8275:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:24762*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24762*FLEN/8, x13, x9, x10)

inst_8276:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3f999999; valaddr_reg:x12; val_offset:24765*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24765*FLEN/8, x13, x9, x10)

inst_8277:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:24768*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24768*FLEN/8, x13, x9, x10)

inst_8278:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:24771*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24771*FLEN/8, x13, x9, x10)

inst_8279:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:24774*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24774*FLEN/8, x13, x9, x10)

inst_8280:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:24777*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24777*FLEN/8, x13, x9, x10)

inst_8281:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:24780*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24780*FLEN/8, x13, x9, x10)

inst_8282:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:24783*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24783*FLEN/8, x13, x9, x10)

inst_8283:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x78e8ed and fs2 == 0 and fe2 == 0x00 and fm2 == 0x41d2b1 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ef8e8ed; op2val:0x41d2b1;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:24786*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24786*FLEN/8, x13, x9, x10)

inst_8284:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e000000; valaddr_reg:x12; val_offset:24789*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24789*FLEN/8, x13, x9, x10)

inst_8285:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fffff; valaddr_reg:x12; val_offset:24792*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24792*FLEN/8, x13, x9, x10)

inst_8286:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e400000; valaddr_reg:x12; val_offset:24795*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24795*FLEN/8, x13, x9, x10)

inst_8287:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e3fffff; valaddr_reg:x12; val_offset:24798*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24798*FLEN/8, x13, x9, x10)

inst_8288:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e600000; valaddr_reg:x12; val_offset:24801*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24801*FLEN/8, x13, x9, x10)

inst_8289:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e1fffff; valaddr_reg:x12; val_offset:24804*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24804*FLEN/8, x13, x9, x10)

inst_8290:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e700000; valaddr_reg:x12; val_offset:24807*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24807*FLEN/8, x13, x9, x10)

inst_8291:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e0fffff; valaddr_reg:x12; val_offset:24810*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24810*FLEN/8, x13, x9, x10)

inst_8292:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e780000; valaddr_reg:x12; val_offset:24813*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24813*FLEN/8, x13, x9, x10)

inst_8293:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e07ffff; valaddr_reg:x12; val_offset:24816*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24816*FLEN/8, x13, x9, x10)

inst_8294:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7c0000; valaddr_reg:x12; val_offset:24819*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24819*FLEN/8, x13, x9, x10)

inst_8295:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e03ffff; valaddr_reg:x12; val_offset:24822*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24822*FLEN/8, x13, x9, x10)

inst_8296:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7e0000; valaddr_reg:x12; val_offset:24825*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24825*FLEN/8, x13, x9, x10)

inst_8297:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e01ffff; valaddr_reg:x12; val_offset:24828*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24828*FLEN/8, x13, x9, x10)

inst_8298:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7f0000; valaddr_reg:x12; val_offset:24831*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24831*FLEN/8, x13, x9, x10)

inst_8299:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e00ffff; valaddr_reg:x12; val_offset:24834*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24834*FLEN/8, x13, x9, x10)

inst_8300:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7f8000; valaddr_reg:x12; val_offset:24837*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24837*FLEN/8, x13, x9, x10)

inst_8301:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e007fff; valaddr_reg:x12; val_offset:24840*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24840*FLEN/8, x13, x9, x10)

inst_8302:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fc000; valaddr_reg:x12; val_offset:24843*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24843*FLEN/8, x13, x9, x10)

inst_8303:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e003fff; valaddr_reg:x12; val_offset:24846*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24846*FLEN/8, x13, x9, x10)

inst_8304:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fe000; valaddr_reg:x12; val_offset:24849*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24849*FLEN/8, x13, x9, x10)

inst_8305:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e001fff; valaddr_reg:x12; val_offset:24852*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24852*FLEN/8, x13, x9, x10)

inst_8306:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ff000; valaddr_reg:x12; val_offset:24855*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24855*FLEN/8, x13, x9, x10)

inst_8307:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e000fff; valaddr_reg:x12; val_offset:24858*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24858*FLEN/8, x13, x9, x10)

inst_8308:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ff800; valaddr_reg:x12; val_offset:24861*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24861*FLEN/8, x13, x9, x10)

inst_8309:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e0007ff; valaddr_reg:x12; val_offset:24864*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24864*FLEN/8, x13, x9, x10)

inst_8310:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ffc00; valaddr_reg:x12; val_offset:24867*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24867*FLEN/8, x13, x9, x10)

inst_8311:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e0003ff; valaddr_reg:x12; val_offset:24870*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24870*FLEN/8, x13, x9, x10)

inst_8312:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ffe00; valaddr_reg:x12; val_offset:24873*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24873*FLEN/8, x13, x9, x10)

inst_8313:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e0001ff; valaddr_reg:x12; val_offset:24876*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24876*FLEN/8, x13, x9, x10)

inst_8314:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fff00; valaddr_reg:x12; val_offset:24879*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24879*FLEN/8, x13, x9, x10)

inst_8315:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e0000ff; valaddr_reg:x12; val_offset:24882*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24882*FLEN/8, x13, x9, x10)

inst_8316:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fff80; valaddr_reg:x12; val_offset:24885*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24885*FLEN/8, x13, x9, x10)

inst_8317:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e00007f; valaddr_reg:x12; val_offset:24888*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24888*FLEN/8, x13, x9, x10)

inst_8318:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fffc0; valaddr_reg:x12; val_offset:24891*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24891*FLEN/8, x13, x9, x10)

inst_8319:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e00003f; valaddr_reg:x12; val_offset:24894*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24894*FLEN/8, x13, x9, x10)

inst_8320:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7fffe0; valaddr_reg:x12; val_offset:24897*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24897*FLEN/8, x13, x9, x10)

inst_8321:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e00001f; valaddr_reg:x12; val_offset:24900*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24900*FLEN/8, x13, x9, x10)

inst_8322:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ffff0; valaddr_reg:x12; val_offset:24903*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24903*FLEN/8, x13, x9, x10)

inst_8323:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e00000f; valaddr_reg:x12; val_offset:24906*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24906*FLEN/8, x13, x9, x10)

inst_8324:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ffff8; valaddr_reg:x12; val_offset:24909*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24909*FLEN/8, x13, x9, x10)

inst_8325:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e000007; valaddr_reg:x12; val_offset:24912*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24912*FLEN/8, x13, x9, x10)

inst_8326:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ffffc; valaddr_reg:x12; val_offset:24915*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24915*FLEN/8, x13, x9, x10)

inst_8327:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e000003; valaddr_reg:x12; val_offset:24918*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24918*FLEN/8, x13, x9, x10)

inst_8328:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e7ffffe; valaddr_reg:x12; val_offset:24921*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24921*FLEN/8, x13, x9, x10)

inst_8329:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7c and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3e000001; valaddr_reg:x12; val_offset:24924*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24924*FLEN/8, x13, x9, x10)

inst_8330:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:24927*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24927*FLEN/8, x13, x9, x10)

inst_8331:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3f800007; valaddr_reg:x12; val_offset:24930*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24930*FLEN/8, x13, x9, x10)

inst_8332:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:24933*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24933*FLEN/8, x13, x9, x10)

inst_8333:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3f800003; valaddr_reg:x12; val_offset:24936*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24936*FLEN/8, x13, x9, x10)

inst_8334:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3ffffffe; valaddr_reg:x12; val_offset:24939*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24939*FLEN/8, x13, x9, x10)

inst_8335:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3f800001; valaddr_reg:x12; val_offset:24942*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24942*FLEN/8, x13, x9, x10)

inst_8336:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fb6db6d; valaddr_reg:x12; val_offset:24945*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24945*FLEN/8, x13, x9, x10)

inst_8337:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fedb6db; valaddr_reg:x12; val_offset:24948*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24948*FLEN/8, x13, x9, x10)

inst_8338:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3f999999; valaddr_reg:x12; val_offset:24951*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24951*FLEN/8, x13, x9, x10)

inst_8339:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fe66666; valaddr_reg:x12; val_offset:24954*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24954*FLEN/8, x13, x9, x10)

inst_8340:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fbbbbbb; valaddr_reg:x12; val_offset:24957*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24957*FLEN/8, x13, x9, x10)

inst_8341:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fc44444; valaddr_reg:x12; val_offset:24960*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24960*FLEN/8, x13, x9, x10)

inst_8342:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fa49249; valaddr_reg:x12; val_offset:24963*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24963*FLEN/8, x13, x9, x10)

inst_8343:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fdb6db6; valaddr_reg:x12; val_offset:24966*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24966*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_65)
inst_8344:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fb33333; valaddr_reg:x12; val_offset:24969*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24969*FLEN/8, x13, x9, x10)

inst_8345:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x622ba2 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x10e1c3 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e622ba2; op2val:0x90e1c3;
op3val:0x3fcccccc; valaddr_reg:x12; val_offset:24972*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24972*FLEN/8, x13, x9, x10)

inst_8346:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e800000; valaddr_reg:x12; val_offset:24975*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24975*FLEN/8, x13, x9, x10)

inst_8347:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effffff; valaddr_reg:x12; val_offset:24978*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24978*FLEN/8, x13, x9, x10)

inst_8348:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ec00000; valaddr_reg:x12; val_offset:24981*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24981*FLEN/8, x13, x9, x10)

inst_8349:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ebfffff; valaddr_reg:x12; val_offset:24984*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24984*FLEN/8, x13, x9, x10)

inst_8350:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ee00000; valaddr_reg:x12; val_offset:24987*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24987*FLEN/8, x13, x9, x10)

inst_8351:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e9fffff; valaddr_reg:x12; val_offset:24990*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24990*FLEN/8, x13, x9, x10)

inst_8352:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ef00000; valaddr_reg:x12; val_offset:24993*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24993*FLEN/8, x13, x9, x10)

inst_8353:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e8fffff; valaddr_reg:x12; val_offset:24996*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24996*FLEN/8, x13, x9, x10)

inst_8354:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ef80000; valaddr_reg:x12; val_offset:24999*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 24999*FLEN/8, x13, x9, x10)

inst_8355:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e87ffff; valaddr_reg:x12; val_offset:25002*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25002*FLEN/8, x13, x9, x10)

inst_8356:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efc0000; valaddr_reg:x12; val_offset:25005*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25005*FLEN/8, x13, x9, x10)

inst_8357:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e83ffff; valaddr_reg:x12; val_offset:25008*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25008*FLEN/8, x13, x9, x10)

inst_8358:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efe0000; valaddr_reg:x12; val_offset:25011*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25011*FLEN/8, x13, x9, x10)

inst_8359:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e81ffff; valaddr_reg:x12; val_offset:25014*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25014*FLEN/8, x13, x9, x10)

inst_8360:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3eff0000; valaddr_reg:x12; val_offset:25017*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25017*FLEN/8, x13, x9, x10)

inst_8361:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e80ffff; valaddr_reg:x12; val_offset:25020*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25020*FLEN/8, x13, x9, x10)

inst_8362:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3eff8000; valaddr_reg:x12; val_offset:25023*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25023*FLEN/8, x13, x9, x10)

inst_8363:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e807fff; valaddr_reg:x12; val_offset:25026*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25026*FLEN/8, x13, x9, x10)

inst_8364:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effc000; valaddr_reg:x12; val_offset:25029*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25029*FLEN/8, x13, x9, x10)

inst_8365:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e803fff; valaddr_reg:x12; val_offset:25032*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25032*FLEN/8, x13, x9, x10)

inst_8366:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effe000; valaddr_reg:x12; val_offset:25035*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25035*FLEN/8, x13, x9, x10)

inst_8367:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e801fff; valaddr_reg:x12; val_offset:25038*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25038*FLEN/8, x13, x9, x10)

inst_8368:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efff000; valaddr_reg:x12; val_offset:25041*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25041*FLEN/8, x13, x9, x10)

inst_8369:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e800fff; valaddr_reg:x12; val_offset:25044*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25044*FLEN/8, x13, x9, x10)

inst_8370:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efff800; valaddr_reg:x12; val_offset:25047*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25047*FLEN/8, x13, x9, x10)

inst_8371:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e8007ff; valaddr_reg:x12; val_offset:25050*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25050*FLEN/8, x13, x9, x10)

inst_8372:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efffc00; valaddr_reg:x12; val_offset:25053*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25053*FLEN/8, x13, x9, x10)

inst_8373:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e8003ff; valaddr_reg:x12; val_offset:25056*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25056*FLEN/8, x13, x9, x10)

inst_8374:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efffe00; valaddr_reg:x12; val_offset:25059*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25059*FLEN/8, x13, x9, x10)

inst_8375:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e8001ff; valaddr_reg:x12; val_offset:25062*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25062*FLEN/8, x13, x9, x10)

inst_8376:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effff00; valaddr_reg:x12; val_offset:25065*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25065*FLEN/8, x13, x9, x10)

inst_8377:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e8000ff; valaddr_reg:x12; val_offset:25068*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25068*FLEN/8, x13, x9, x10)

inst_8378:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effff80; valaddr_reg:x12; val_offset:25071*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25071*FLEN/8, x13, x9, x10)

inst_8379:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e80007f; valaddr_reg:x12; val_offset:25074*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25074*FLEN/8, x13, x9, x10)

inst_8380:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effffc0; valaddr_reg:x12; val_offset:25077*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25077*FLEN/8, x13, x9, x10)

inst_8381:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e80003f; valaddr_reg:x12; val_offset:25080*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25080*FLEN/8, x13, x9, x10)

inst_8382:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3effffe0; valaddr_reg:x12; val_offset:25083*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25083*FLEN/8, x13, x9, x10)

inst_8383:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e80001f; valaddr_reg:x12; val_offset:25086*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25086*FLEN/8, x13, x9, x10)

inst_8384:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efffff0; valaddr_reg:x12; val_offset:25089*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25089*FLEN/8, x13, x9, x10)

inst_8385:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e80000f; valaddr_reg:x12; val_offset:25092*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25092*FLEN/8, x13, x9, x10)

inst_8386:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efffff8; valaddr_reg:x12; val_offset:25095*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25095*FLEN/8, x13, x9, x10)

inst_8387:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e800007; valaddr_reg:x12; val_offset:25098*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25098*FLEN/8, x13, x9, x10)

inst_8388:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efffffc; valaddr_reg:x12; val_offset:25101*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25101*FLEN/8, x13, x9, x10)

inst_8389:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e800003; valaddr_reg:x12; val_offset:25104*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25104*FLEN/8, x13, x9, x10)

inst_8390:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3efffffe; valaddr_reg:x12; val_offset:25107*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25107*FLEN/8, x13, x9, x10)

inst_8391:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7d and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3e800001; valaddr_reg:x12; val_offset:25110*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25110*FLEN/8, x13, x9, x10)

inst_8392:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ffffff8; valaddr_reg:x12; val_offset:25113*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25113*FLEN/8, x13, x9, x10)

inst_8393:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3f800007; valaddr_reg:x12; val_offset:25116*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25116*FLEN/8, x13, x9, x10)

inst_8394:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3ffffffc; valaddr_reg:x12; val_offset:25119*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25119*FLEN/8, x13, x9, x10)

inst_8395:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06e773 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3cb980 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06e773; op2val:0x3cb980;
op3val:0x3f800003; valaddr_reg:x12; val_offset:25122*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 25122*FLEN/8, x13, x9, x10)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(964558848,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956432383,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964624384,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956366847,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964657152,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956334079,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964673536,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956317695,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964681728,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956309503,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964685824,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956305407,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964687872,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956303359,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964688896,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956302335,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689408,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301823,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689664,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301567,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689792,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301439,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689856,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301375,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689888,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301343,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689904,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301327,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689912,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301319,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689916,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301315,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(964689918,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(956301313,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1073741816,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1065353223,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1073741820,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1065353219,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1073741822,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1065353217,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1068948333,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1072543451,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1067030937,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1072064102,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1069267899,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1069827140,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1067749961,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1071345078,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1068708659,32,FLEN)
NAN_BOXED(2119693699,32,FLEN)
NAN_BOXED(9943939,32,FLEN)
NAN_BOXED(1070386380,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964689920,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973078527,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(968884224,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(968884223,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(970981376,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(966787071,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(972029952,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(965738495,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(972554240,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(965214207,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(972816384,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964952063,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(972947456,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964820991,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973012992,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964755455,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973045760,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964722687,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973062144,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964706303,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973070336,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964698111,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973074432,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964694015,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973076480,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964691967,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973077504,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964690943,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973078016,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964690431,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973078272,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964690175,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973078400,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(964690047,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
NAN_BOXED(973078464,32,FLEN)
NAN_BOXED(2119061788,32,FLEN)
NAN_BOXED(10408668,32,FLEN)
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NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056956416,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048584191,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056960512,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048580095,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056962560,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048578047,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056963584,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048577023,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964096,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576511,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964352,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576255,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964480,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576127,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964544,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576063,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964576,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576031,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964592,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576015,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964600,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576007,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964604,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576003,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1056964606,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1048576001,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1073741816,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1065353223,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1073741820,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1065353219,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1073741822,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1065353217,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1068948333,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1072543451,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1067030937,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1072064102,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1069267899,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1069827140,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1067749961,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1071345078,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1068708659,32,FLEN)
NAN_BOXED(2131158899,32,FLEN)
NAN_BOXED(3979648,32,FLEN)
NAN_BOXED(1070386380,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056964608,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065353215,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1061158912,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1061158911,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1063256064,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1059061759,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1064304640,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1058013183,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1064828928,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1057488895,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065091072,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1057226751,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065222144,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1057095679,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065287680,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1057030143,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065320448,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056997375,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065336832,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056980991,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065345024,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056972799,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065349120,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056968703,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065351168,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056966655,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065352192,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056965631,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065352704,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056965119,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065352960,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056964863,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065353088,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056964735,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1065353152,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
NAN_BOXED(1056964671,32,FLEN)
NAN_BOXED(2126423887,32,FLEN)
NAN_BOXED(5631900,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_109:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_110:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_111:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_112:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_113:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_114:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_115:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_116:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_117:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_118:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_119:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_120:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_121:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_122:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_123:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_124:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_125:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_126:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_127:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_128:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_129:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_130:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_131:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_132:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_133:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_134:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_135:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_136:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_137:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_138:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_139:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_140:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_141:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_142:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_143:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_144:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_145:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_146:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_147:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_148:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_149:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_150:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_151:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_152:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_153:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_154:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_155:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_156:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_157:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_158:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_159:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_160:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_161:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_162:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_163:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_164:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_165:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_166:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_167:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_168:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_169:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_170:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_171:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_172:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_173:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_174:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_175:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_176:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_177:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_178:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_179:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_180:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_181:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_182:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_183:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_184:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_185:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_186:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_187:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_188:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_189:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_190:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_191:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_192:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_193:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_194:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_195:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_196:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_197:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_198:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_199:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_200:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_201:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_202:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_203:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_204:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_205:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_206:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_207:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_208:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_209:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_210:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_211:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_212:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_213:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_214:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_215:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_216:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_217:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_218:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_219:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_220:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_221:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_222:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_223:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_224:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_225:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_226:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_227:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_228:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_229:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_230:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_231:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_232:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_233:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_234:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_235:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_236:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_237:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_238:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_239:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_240:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_241:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_242:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_243:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_244:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_245:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_246:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_247:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_248:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_249:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_250:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_251:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_252:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_253:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_254:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_255:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_256:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_257:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_258:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_259:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_260:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_261:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_262:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_263:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_264:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_265:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_266:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_267:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_268:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_269:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_270:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_271:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_272:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_273:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_274:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_275:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_276:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_277:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_278:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_279:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_280:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_281:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_282:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_283:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_284:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_285:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_286:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_287:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_288:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_289:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_290:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_291:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_292:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_293:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_294:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_295:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_296:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_297:
    .fill 180*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
