
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Sun Aug  7 17:10:46 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/anku/work2/bmanip/64/dataset.yaml \
//                  --cgf /home/anku/work2/bmanip/64/rv64ib.yaml \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the bext instruction of the RISC-V RV64Zbs extension for the bext covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IZbs,RV64IB")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*Zbs.*);def TEST_CASE_1=True;",bext)
RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*B.*);def TEST_CASE_1=True;",bext)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs2 == rd != rs1, rs1==x30, rs2==x31, rd==x31, 
// opcode: bext ; op1:x30; op2:x31; dest:x31; op1val:0x5555555555555555;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x31, 0x0000000000000000, 0x5555555555555555, 0xfffffffffffffbff, x1, 0, x2)

inst_1:
// rs1 == rd != rs2, rs1==x29, rs2==x30, rd==x29, 
// opcode: bext ; op1:x29; op2:x30; dest:x29; op1val:0xfffffffffffffbff;  op2val:0x7fffffffffffffff
TEST_RR_OP(bext, x29, x29, x30, 0x0000000000000000, 0xfffffffffffffbff, 0x7fffffffffffffff, x1, 8, x2)

inst_2:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x31, rs2==x29, rd==x30, 
// opcode: bext ; op1:x31; op2:x29; dest:x30; op1val:0xfffffffffffffbff;  op2val:0xbfffffffffffffff
TEST_RR_OP(bext, x30, x31, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xbfffffffffffffff, x1, 16, x2)

inst_3:
// rs1 == rs2 == rd, rs1==x28, rs2==x28, rd==x28, 
// opcode: bext ; op1:x28; op2:x28; dest:x28; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x28, x28, x28, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffbff, x1, 24, x2)

inst_4:
// rs1 == rs2 != rd, rs1==x26, rs2==x26, rd==x27, 
// opcode: bext ; op1:x26; op2:x26; dest:x27; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x27, x26, x26, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffbff, x1, 32, x2)

inst_5:
// rs1==x27, rs2==x25, rd==x26, 
// opcode: bext ; op1:x27; op2:x25; dest:x26; op1val:0xfffffffffffffbff;  op2val:0xf7ffffffffffffff
TEST_RR_OP(bext, x26, x27, x25, 0x0000000000000000, 0xfffffffffffffbff, 0xf7ffffffffffffff, x1, 40, x2)

inst_6:
// rs1==x24, rs2==x27, rd==x25, 
// opcode: bext ; op1:x24; op2:x27; dest:x25; op1val:0xfffffffffffffbff;  op2val:0xfbffffffffffffff
TEST_RR_OP(bext, x25, x24, x27, 0x0000000000000000, 0xfffffffffffffbff, 0xfbffffffffffffff, x1, 48, x2)

inst_7:
// rs1==x25, rs2==x23, rd==x24, 
// opcode: bext ; op1:x25; op2:x23; dest:x24; op1val:0xfffffffffffffbff;  op2val:0xfdffffffffffffff
TEST_RR_OP(bext, x24, x25, x23, 0x0000000000000000, 0xfffffffffffffbff, 0xfdffffffffffffff, x1, 56, x2)

inst_8:
// rs1==x22, rs2==x24, rd==x23, 
// opcode: bext ; op1:x22; op2:x24; dest:x23; op1val:0xfffffffffffffbff;  op2val:0xfeffffffffffffff
TEST_RR_OP(bext, x23, x22, x24, 0x0000000000000000, 0xfffffffffffffbff, 0xfeffffffffffffff, x1, 64, x2)

inst_9:
// rs1==x23, rs2==x21, rd==x22, 
// opcode: bext ; op1:x23; op2:x21; dest:x22; op1val:0xfffffffffffffbff;  op2val:0xff7fffffffffffff
TEST_RR_OP(bext, x22, x23, x21, 0x0000000000000000, 0xfffffffffffffbff, 0xff7fffffffffffff, x1, 72, x2)

inst_10:
// rs1==x20, rs2==x22, rd==x21, 
// opcode: bext ; op1:x20; op2:x22; dest:x21; op1val:0xfffffffffffffbff;  op2val:0xffbfffffffffffff
TEST_RR_OP(bext, x21, x20, x22, 0x0000000000000000, 0xfffffffffffffbff, 0xffbfffffffffffff, x1, 80, x2)

inst_11:
// rs1==x21, rs2==x19, rd==x20, 
// opcode: bext ; op1:x21; op2:x19; dest:x20; op1val:0xfffffffffffffbff;  op2val:0xffdfffffffffffff
TEST_RR_OP(bext, x20, x21, x19, 0x0000000000000000, 0xfffffffffffffbff, 0xffdfffffffffffff, x1, 88, x2)

inst_12:
// rs1==x18, rs2==x20, rd==x19, 
// opcode: bext ; op1:x18; op2:x20; dest:x19; op1val:0xfffffffffffffbff;  op2val:0xffefffffffffffff
TEST_RR_OP(bext, x19, x18, x20, 0x0000000000000000, 0xfffffffffffffbff, 0xffefffffffffffff, x1, 96, x2)

inst_13:
// rs1==x19, rs2==x17, rd==x18, 
// opcode: bext ; op1:x19; op2:x17; dest:x18; op1val:0xfffffffffffffbff;  op2val:0xfff7ffffffffffff
TEST_RR_OP(bext, x18, x19, x17, 0x0000000000000000, 0xfffffffffffffbff, 0xfff7ffffffffffff, x1, 104, x2)

inst_14:
// rs1==x16, rs2==x18, rd==x17, 
// opcode: bext ; op1:x16; op2:x18; dest:x17; op1val:0xfffffffffffffbff;  op2val:0xfffbffffffffffff
TEST_RR_OP(bext, x17, x16, x18, 0x0000000000000000, 0xfffffffffffffbff, 0xfffbffffffffffff, x1, 112, x2)

inst_15:
// rs1==x17, rs2==x15, rd==x16, 
// opcode: bext ; op1:x17; op2:x15; dest:x16; op1val:0xfffffffffffffbff;  op2val:0xfffdffffffffffff
TEST_RR_OP(bext, x16, x17, x15, 0x0000000000000000, 0xfffffffffffffbff, 0xfffdffffffffffff, x1, 120, x2)

inst_16:
// rs1==x14, rs2==x16, rd==x15, 
// opcode: bext ; op1:x14; op2:x16; dest:x15; op1val:0xfffffffffffffbff;  op2val:0xfffeffffffffffff
TEST_RR_OP(bext, x15, x14, x16, 0x0000000000000000, 0xfffffffffffffbff, 0xfffeffffffffffff, x1, 128, x2)

inst_17:
// rs1==x15, rs2==x13, rd==x14, 
// opcode: bext ; op1:x15; op2:x13; dest:x14; op1val:0xfffffffffffffbff;  op2val:0xffff7fffffffffff
TEST_RR_OP(bext, x14, x15, x13, 0x0000000000000000, 0xfffffffffffffbff, 0xffff7fffffffffff, x1, 136, x2)

inst_18:
// rs1==x12, rs2==x14, rd==x13, 
// opcode: bext ; op1:x12; op2:x14; dest:x13; op1val:0xfffffffffffffbff;  op2val:0xffffbfffffffffff
TEST_RR_OP(bext, x13, x12, x14, 0x0000000000000000, 0xfffffffffffffbff, 0xffffbfffffffffff, x1, 144, x2)

inst_19:
// rs1==x13, rs2==x11, rd==x12, 
// opcode: bext ; op1:x13; op2:x11; dest:x12; op1val:0xfffffffffffffbff;  op2val:0xffffdfffffffffff
TEST_RR_OP(bext, x12, x13, x11, 0x0000000000000000, 0xfffffffffffffbff, 0xffffdfffffffffff, x1, 152, x2)

inst_20:
// rs1==x10, rs2==x12, rd==x11, 
// opcode: bext ; op1:x10; op2:x12; dest:x11; op1val:0xfffffffffffffbff;  op2val:0xffffefffffffffff
TEST_RR_OP(bext, x11, x10, x12, 0x0000000000000000, 0xfffffffffffffbff, 0xffffefffffffffff, x1, 160, x2)

inst_21:
// rs1==x11, rs2==x9, rd==x10, 
// opcode: bext ; op1:x11; op2:x9; dest:x10; op1val:0xfffffffffffffbff;  op2val:0xfffff7ffffffffff
TEST_RR_OP(bext, x10, x11, x9, 0x0000000000000000, 0xfffffffffffffbff, 0xfffff7ffffffffff, x1, 168, x2)

inst_22:
// rs1==x8, rs2==x10, rd==x9, 
// opcode: bext ; op1:x8; op2:x10; dest:x9; op1val:0xfffffffffffffbff;  op2val:0xfffffbffffffffff
TEST_RR_OP(bext, x9, x8, x10, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffbffffffffff, x1, 176, x2)

inst_23:
// rs1==x9, rs2==x7, rd==x8, 
// opcode: bext ; op1:x9; op2:x7; dest:x8; op1val:0xfffffffffffffbff;  op2val:0xfffffdffffffffff
TEST_RR_OP(bext, x8, x9, x7, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffdffffffffff, x1, 184, x2)

inst_24:
// rs1==x6, rs2==x8, rd==x7, 
// opcode: bext ; op1:x6; op2:x8; dest:x7; op1val:0xfffffffffffffbff;  op2val:0xfffffeffffffffff
TEST_RR_OP(bext, x7, x6, x8, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffeffffffffff, x1, 192, x2)

inst_25:
// rs1==x7, rs2==x5, rd==x6, 
// opcode: bext ; op1:x7; op2:x5; dest:x6; op1val:0xfffffffffffffbff;  op2val:0xffffff7fffffffff
TEST_RR_OP(bext, x6, x7, x5, 0x0000000000000000, 0xfffffffffffffbff, 0xffffff7fffffffff, x1, 200, x8)
RVTEST_SIGBASE(x7,signature_x7_0)

inst_26:
// rs1==x4, rs2==x6, rd==x5, 
// opcode: bext ; op1:x4; op2:x6; dest:x5; op1val:0xfffffffffffffbff;  op2val:0xffffffbfffffffff
TEST_RR_OP(bext, x5, x4, x6, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffbfffffffff, x7, 0, x8)

inst_27:
// rs1==x5, rs2==x3, rd==x4, 
// opcode: bext ; op1:x5; op2:x3; dest:x4; op1val:0xfffffffffffffbff;  op2val:0xffffffdfffffffff
TEST_RR_OP(bext, x4, x5, x3, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffdfffffffff, x7, 8, x8)

inst_28:
// rs1==x2, rs2==x4, rd==x3, 
// opcode: bext ; op1:x2; op2:x4; dest:x3; op1val:0xfffffffffffffbff;  op2val:0xffffffefffffffff
TEST_RR_OP(bext, x3, x2, x4, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffefffffffff, x7, 16, x8)

inst_29:
// rs1==x3, rs2==x1, rd==x2, 
// opcode: bext ; op1:x3; op2:x1; dest:x2; op1val:0xfffffffffffffbff;  op2val:0xfffffff7ffffffff
TEST_RR_OP(bext, x2, x3, x1, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffff7ffffffff, x7, 24, x8)

inst_30:
// rs1==x0, rs2==x2, rd==x1, 
// opcode: bext ; op1:x0; op2:x2; dest:x1; op1val:0x0;  op2val:0xfffffffbffffffff
TEST_RR_OP(bext, x1, x0, x2, 0x0000000000000000, 0x0, 0xfffffffbffffffff, x7, 32, x8)

inst_31:
// rs1==x1, 
// opcode: bext ; op1:x1; op2:x30; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffdffffffff
TEST_RR_OP(bext, x31, x1, x30, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffdffffffff, x7, 40, x8)

inst_32:
// rs2==x0, 
// opcode: bext ; op1:x30; op2:x0; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x0, 0x0000000000000000, 0xfffffffffffffbff, 0x0, x7, 48, x8)

inst_33:
// rd==x0, 
// opcode: bext ; op1:x31; op2:x30; dest:x0; op1val:0xfffffffffffffbff;  op2val:0xffffffff7fffffff
TEST_RR_OP(bext, x0, x31, x30, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffff7fffffff, x7, 56, x8)

inst_34:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffbfffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffbfffffff, x7, 64, x8)

inst_35:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffdfffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffdfffffff, x7, 72, x8)

inst_36:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffefffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffefffffff, x7, 80, x8)

inst_37:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffff7ffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffff7ffffff, x7, 88, x8)

inst_38:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffbffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffbffffff, x7, 96, x8)

inst_39:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffdffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffdffffff, x7, 104, x8)

inst_40:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffeffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffeffffff, x7, 112, x8)

inst_41:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffff7fffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffff7fffff, x7, 120, x8)

inst_42:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffbfffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffbfffff, x7, 128, x8)

inst_43:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffdfffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffdfffff, x7, 136, x8)

inst_44:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffefffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffefffff, x7, 144, x8)

inst_45:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffff7ffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffff7ffff, x7, 152, x8)

inst_46:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffbffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffbffff, x7, 160, x8)

inst_47:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffdffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffdffff, x7, 168, x8)

inst_48:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffeffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffeffff, x7, 176, x8)

inst_49:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffff7fff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffff7fff, x7, 184, x8)

inst_50:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffbfff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffbfff, x7, 192, x8)

inst_51:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffdfff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffdfff, x7, 200, x8)

inst_52:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffefff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffefff, x7, 208, x8)

inst_53:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffff7ff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffff7ff, x7, 216, x8)

inst_54:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffdff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffdff, x7, 224, x8)

inst_55:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffeff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffeff, x7, 232, x8)

inst_56:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffff7f
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffff7f, x7, 240, x8)

inst_57:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffffbf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffffbf, x7, 248, x8)

inst_58:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffffdf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffffdf, x7, 256, x8)

inst_59:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffffffffffef
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffffffffffef, x7, 264, x8)

inst_60:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffff7
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffff7, x7, 272, x8)

inst_61:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffffb
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffffb, x7, 280, x8)

inst_62:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffffd
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffffd, x7, 288, x8)

inst_63:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffffffffffe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffffffffffe, x7, 296, x8)

inst_64:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x7fffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x7fffffffffffffff, 0xfffffffffffffbff, x7, 304, x8)

inst_65:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xbfffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xbfffffffffffffff, 0xfffffffffffffbff, x7, 312, x8)

inst_66:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xdfffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xdfffffffffffffff, 0xfffffffffffffbff, x7, 320, x8)

inst_67:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xefffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xefffffffffffffff, 0xfffffffffffffbff, x7, 328, x8)

inst_68:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf7ffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf7ffffffffffffff, 0xfffffffffffffbff, x7, 336, x8)

inst_69:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfbffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfbffffffffffffff, 0xfffffffffffffbff, x7, 344, x8)

inst_70:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfdffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfdffffffffffffff, 0xfffffffffffffbff, x7, 352, x8)

inst_71:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfeffffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfeffffffffffffff, 0xfffffffffffffbff, x7, 360, x8)

inst_72:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xff7fffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xff7fffffffffffff, 0xfffffffffffffbff, x7, 368, x8)

inst_73:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffbfffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffbfffffffffffff, 0xfffffffffffffbff, x7, 376, x8)

inst_74:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffdfffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffdfffffffffffff, 0xfffffffffffffbff, x7, 384, x8)

inst_75:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffefffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffefffffffffffff, 0xfffffffffffffbff, x7, 392, x8)

inst_76:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfff7ffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfff7ffffffffffff, 0xfffffffffffffbff, x7, 400, x8)

inst_77:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffbffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffbffffffffffff, 0xfffffffffffffbff, x7, 408, x8)

inst_78:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffdffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffdffffffffffff, 0xfffffffffffffbff, x7, 416, x8)

inst_79:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffeffffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffeffffffffffff, 0xfffffffffffffbff, x7, 424, x8)

inst_80:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffff7fffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffff7fffffffffff, 0xfffffffffffffbff, x7, 432, x8)

inst_81:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffbfffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffbfffffffffff, 0xfffffffffffffbff, x7, 440, x8)

inst_82:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffdfffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffdfffffffffff, 0xfffffffffffffbff, x7, 448, x8)

inst_83:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffefffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffefffffffffff, 0xfffffffffffffbff, x7, 456, x8)

inst_84:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffff7ffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffff7ffffffffff, 0xfffffffffffffbff, x7, 464, x8)

inst_85:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffbffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffbffffffffff, 0xfffffffffffffbff, x7, 472, x8)

inst_86:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffdffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffdffffffffff, 0xfffffffffffffbff, x7, 480, x8)

inst_87:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffeffffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffeffffffffff, 0xfffffffffffffbff, x7, 488, x8)

inst_88:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffff7fffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffff7fffffffff, 0xfffffffffffffbff, x7, 496, x8)

inst_89:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffbfffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffbfffffffff, 0xfffffffffffffbff, x7, 504, x8)

inst_90:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffdfffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffdfffffffff, 0xfffffffffffffbff, x7, 512, x8)

inst_91:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffefffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffefffffffff, 0xfffffffffffffbff, x7, 520, x8)

inst_92:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffff7ffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffff7ffffffff, 0xfffffffffffffbff, x7, 528, x8)

inst_93:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffbffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffbffffffff, 0xfffffffffffffbff, x7, 536, x8)

inst_94:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffdffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffdffffffff, 0xfffffffffffffbff, x7, 544, x8)

inst_95:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffeffffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffeffffffff, 0xfffffffffffffbff, x7, 552, x8)

inst_96:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff7fffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffff7fffffff, 0xfffffffffffffbff, x7, 560, x8)

inst_97:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffbfffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffbfffffff, 0xfffffffffffffbff, x7, 568, x8)

inst_98:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffdfffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffdfffffff, 0xfffffffffffffbff, x7, 576, x8)

inst_99:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffefffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffefffffff, 0xfffffffffffffbff, x7, 584, x8)

inst_100:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffff7ffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffff7ffffff, 0xfffffffffffffbff, x7, 592, x8)

inst_101:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffbffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffbffffff, 0xfffffffffffffbff, x7, 600, x8)

inst_102:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffdffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffdffffff, 0xfffffffffffffbff, x7, 608, x8)

inst_103:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffeffffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffeffffff, 0xfffffffffffffbff, x7, 616, x8)

inst_104:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffff7fffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffff7fffff, 0xfffffffffffffbff, x7, 624, x8)

inst_105:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffbfffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffbfffff, 0xfffffffffffffbff, x7, 632, x8)

inst_106:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffdfffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffdfffff, 0xfffffffffffffbff, x7, 640, x8)

inst_107:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffefffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffefffff, 0xfffffffffffffbff, x7, 648, x8)

inst_108:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffff7ffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffff7ffff, 0xfffffffffffffbff, x7, 656, x8)

inst_109:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffbffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffbffff, 0xfffffffffffffbff, x7, 664, x8)

inst_110:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffdffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffdffff, 0xfffffffffffffbff, x7, 672, x8)

inst_111:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffeffff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffeffff, 0xfffffffffffffbff, x7, 680, x8)

inst_112:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffff7fff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffff7fff, 0xfffffffffffffbff, x7, 688, x8)

inst_113:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffbfff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffbfff, 0xfffffffffffffbff, x7, 696, x8)

inst_114:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffdfff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffdfff, 0xfffffffffffffbff, x7, 704, x8)

inst_115:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffefff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffefff, 0xfffffffffffffbff, x7, 712, x8)

inst_116:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffff7ff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffff7ff, 0xfffffffffffffbff, x7, 720, x8)

inst_117:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffdff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffdff, 0xfffffffffffffbff, x7, 728, x8)

inst_118:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffeff;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffeff, 0xfffffffffffffbff, x7, 736, x8)

inst_119:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffff7f;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffff7f, 0xfffffffffffffbff, x7, 744, x8)

inst_120:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffffbf;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffffbf, 0xfffffffffffffbff, x7, 752, x8)

inst_121:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffffdf;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffffdf, 0xfffffffffffffbff, x7, 760, x8)

inst_122:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffffffffffef;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffffffffffef, 0xfffffffffffffbff, x7, 768, x8)

inst_123:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffff7;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffff7, 0xfffffffffffffbff, x7, 776, x8)

inst_124:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffffb;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffffb, 0xfffffffffffffbff, x7, 784, x8)

inst_125:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffffd;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffffd, 0xfffffffffffffbff, x7, 792, x8)

inst_126:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffffe;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffffe, 0xfffffffffffffbff, x7, 800, x8)

inst_127:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x8000000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x8000000000000000, x7, 808, x8)

inst_128:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x4000000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x4000000000000000, x7, 816, x8)

inst_129:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x2000000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x2000000000000000, x7, 824, x8)

inst_130:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x1000000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x1000000000000000, x7, 832, x8)

inst_131:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x800000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x800000000000000, x7, 840, x8)

inst_132:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x400000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x400000000000000, x7, 848, x8)

inst_133:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x200000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x200000000000000, x7, 856, x8)

inst_134:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x100000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x100000000000000, x7, 864, x8)

inst_135:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x80000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x80000000000000, x7, 872, x8)

inst_136:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x40000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x40000000000000, x7, 880, x8)

inst_137:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x20000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x20000000000000, x7, 888, x8)

inst_138:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x10000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x10000000000000, x7, 896, x8)

inst_139:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x8000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x8000000000000, x7, 904, x8)

inst_140:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x4000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x4000000000000, x7, 912, x8)

inst_141:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x2000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x2000000000000, x7, 920, x8)

inst_142:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x1000000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x1000000000000, x7, 928, x8)

inst_143:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x800000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x800000000000, x7, 936, x8)

inst_144:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x400000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x400000000000, x7, 944, x8)

inst_145:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x200000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x200000000000, x7, 952, x8)

inst_146:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x100000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x100000000000, x7, 960, x8)

inst_147:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x80000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x80000000000, x7, 968, x8)

inst_148:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x40000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x40000000000, x7, 976, x8)

inst_149:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x20000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x20000000000, x7, 984, x8)

inst_150:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x10000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x10000000000, x7, 992, x8)

inst_151:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x8000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x8000000000, x7, 1000, x8)

inst_152:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x4000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x4000000000, x7, 1008, x8)

inst_153:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x2000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x2000000000, x7, 1016, x8)

inst_154:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x1000000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x1000000000, x7, 1024, x8)

inst_155:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x800000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x800000000, x7, 1032, x8)

inst_156:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x400000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x400000000, x7, 1040, x8)

inst_157:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x200000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x200000000, x7, 1048, x8)

inst_158:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x100000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x100000000, x7, 1056, x8)

inst_159:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x80000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x80000000, x7, 1064, x8)

inst_160:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x40000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x40000000, x7, 1072, x8)

inst_161:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x20000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x20000000, x7, 1080, x8)

inst_162:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x10000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x10000000, x7, 1088, x8)

inst_163:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x8000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x8000000, x7, 1096, x8)

inst_164:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x4000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x4000000, x7, 1104, x8)

inst_165:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x2000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x2000000, x7, 1112, x8)

inst_166:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x1000000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x1000000, x7, 1120, x8)

inst_167:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x800000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x800000, x7, 1128, x8)

inst_168:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x400000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x400000, x7, 1136, x8)

inst_169:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x200000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x200000, x7, 1144, x8)

inst_170:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x100000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x100000, x7, 1152, x8)

inst_171:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x80000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x80000, x7, 1160, x8)

inst_172:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x40000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x40000, x7, 1168, x8)

inst_173:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x20000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x20000, x7, 1176, x8)

inst_174:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x10000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x10000, x7, 1184, x8)

inst_175:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x8000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x8000, x7, 1192, x8)

inst_176:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x4000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x4000, x7, 1200, x8)

inst_177:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x2000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x2000, x7, 1208, x8)

inst_178:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x1000
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x1000, x7, 1216, x8)

inst_179:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x800
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x800, x7, 1224, x8)

inst_180:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x400
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x400, x7, 1232, x8)

inst_181:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x200
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x200, x7, 1240, x8)

inst_182:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x100
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x100, x7, 1248, x8)

inst_183:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x80
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x80, x7, 1256, x8)

inst_184:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x40
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x40, x7, 1264, x8)

inst_185:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x20
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x20, x7, 1272, x8)

inst_186:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x10, x7, 1280, x8)

inst_187:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x8, x7, 1288, x8)

inst_188:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x4
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x4, x7, 1296, x8)

inst_189:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x2
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x2, x7, 1304, x8)

inst_190:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x1
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x1, x7, 1312, x8)

inst_191:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8000000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8000000000000000, 0xfffffffffffffbff, x7, 1320, x8)

inst_192:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4000000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4000000000000000, 0xfffffffffffffbff, x7, 1328, x8)

inst_193:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2000000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2000000000000000, 0xfffffffffffffbff, x7, 1336, x8)

inst_194:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1000000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1000000000000000, 0xfffffffffffffbff, x7, 1344, x8)

inst_195:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x800000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x800000000000000, 0xfffffffffffffbff, x7, 1352, x8)

inst_196:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x400000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x400000000000000, 0xfffffffffffffbff, x7, 1360, x8)

inst_197:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x200000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x200000000000000, 0xfffffffffffffbff, x7, 1368, x8)

inst_198:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x100000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x100000000000000, 0xfffffffffffffbff, x7, 1376, x8)

inst_199:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x80000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x80000000000000, 0xfffffffffffffbff, x7, 1384, x8)

inst_200:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40000000000000, 0xfffffffffffffbff, x7, 1392, x8)

inst_201:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x20000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x20000000000000, 0xfffffffffffffbff, x7, 1400, x8)

inst_202:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x10000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x10000000000000, 0xfffffffffffffbff, x7, 1408, x8)

inst_203:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8000000000000, 0xfffffffffffffbff, x7, 1416, x8)

inst_204:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4000000000000, 0xfffffffffffffbff, x7, 1424, x8)

inst_205:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2000000000000, 0xfffffffffffffbff, x7, 1432, x8)

inst_206:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1000000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1000000000000, 0xfffffffffffffbff, x7, 1440, x8)

inst_207:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x800000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x800000000000, 0xfffffffffffffbff, x7, 1448, x8)

inst_208:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x400000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x400000000000, 0xfffffffffffffbff, x7, 1456, x8)

inst_209:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x200000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x200000000000, 0xfffffffffffffbff, x7, 1464, x8)

inst_210:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x100000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x100000000000, 0xfffffffffffffbff, x7, 1472, x8)

inst_211:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x80000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x80000000000, 0xfffffffffffffbff, x7, 1480, x8)

inst_212:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40000000000, 0xfffffffffffffbff, x7, 1488, x8)

inst_213:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x20000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x20000000000, 0xfffffffffffffbff, x7, 1496, x8)

inst_214:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x10000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x10000000000, 0xfffffffffffffbff, x7, 1504, x8)

inst_215:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8000000000, 0xfffffffffffffbff, x7, 1512, x8)

inst_216:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4000000000, 0xfffffffffffffbff, x7, 1520, x8)

inst_217:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2000000000, 0xfffffffffffffbff, x7, 1528, x8)

inst_218:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1000000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1000000000, 0xfffffffffffffbff, x7, 1536, x8)

inst_219:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x800000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x800000000, 0xfffffffffffffbff, x7, 1544, x8)

inst_220:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x400000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x400000000, 0xfffffffffffffbff, x7, 1552, x8)

inst_221:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x200000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x200000000, 0xfffffffffffffbff, x7, 1560, x8)

inst_222:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x100000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x100000000, 0xfffffffffffffbff, x7, 1568, x8)

inst_223:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x80000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x80000000, 0xfffffffffffffbff, x7, 1576, x8)

inst_224:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40000000, 0xfffffffffffffbff, x7, 1584, x8)

inst_225:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x20000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x20000000, 0xfffffffffffffbff, x7, 1592, x8)

inst_226:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x10000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x10000000, 0xfffffffffffffbff, x7, 1600, x8)

inst_227:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8000000, 0xfffffffffffffbff, x7, 1608, x8)

inst_228:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4000000, 0xfffffffffffffbff, x7, 1616, x8)

inst_229:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2000000, 0xfffffffffffffbff, x7, 1624, x8)

inst_230:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1000000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1000000, 0xfffffffffffffbff, x7, 1632, x8)

inst_231:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x800000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x800000, 0xfffffffffffffbff, x7, 1640, x8)

inst_232:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x400000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x400000, 0xfffffffffffffbff, x7, 1648, x8)

inst_233:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x200000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x200000, 0xfffffffffffffbff, x7, 1656, x8)

inst_234:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x100000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x100000, 0xfffffffffffffbff, x7, 1664, x8)

inst_235:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x80000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x80000, 0xfffffffffffffbff, x7, 1672, x8)

inst_236:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40000, 0xfffffffffffffbff, x7, 1680, x8)

inst_237:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x20000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x20000, 0xfffffffffffffbff, x7, 1688, x8)

inst_238:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x10000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x10000, 0xfffffffffffffbff, x7, 1696, x8)

inst_239:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8000, 0xfffffffffffffbff, x7, 1704, x8)

inst_240:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4000, 0xfffffffffffffbff, x7, 1712, x8)

inst_241:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2000, 0xfffffffffffffbff, x7, 1720, x8)

inst_242:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1000;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1000, 0xfffffffffffffbff, x7, 1728, x8)

inst_243:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x800;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x800, 0xfffffffffffffbff, x7, 1736, x8)

inst_244:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x400;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x400, 0xfffffffffffffbff, x7, 1744, x8)

inst_245:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x200;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x200, 0xfffffffffffffbff, x7, 1752, x8)

inst_246:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x100;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x100, 0xfffffffffffffbff, x7, 1760, x8)

inst_247:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x80;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x80, 0xfffffffffffffbff, x7, 1768, x8)

inst_248:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40, 0xfffffffffffffbff, x7, 1776, x8)

inst_249:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x20;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x20, 0xfffffffffffffbff, x7, 1784, x8)

inst_250:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x10;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x10, 0xfffffffffffffbff, x7, 1792, x8)

inst_251:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8, 0xfffffffffffffbff, x7, 1800, x8)

inst_252:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4, 0xfffffffffffffbff, x7, 1808, x8)

inst_253:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2, 0xfffffffffffffbff, x7, 1816, x8)

inst_254:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1, 0xfffffffffffffbff, x7, 1824, x8)

inst_255:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2dedb6a7;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2dedb6a7, 0x0, x7, 1832, x8)

inst_256:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x3c272728;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x3c272728, 0x10, x7, 1840, x8)

inst_257:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4f55c73d;  op2val:0x18
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4f55c73d, 0x18, x7, 1848, x8)

inst_258:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb0ab577a;  op2val:0x14
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb0ab577a, 0x14, x7, 1856, x8)

inst_259:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf0eb21aa;  op2val:0x1a
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf0eb21aa, 0x1a, x7, 1864, x8)

inst_260:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa9e16e27;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa9e16e27, 0x1b, x7, 1872, x8)

inst_261:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x0;  op2val:0xc
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x0, 0xc, x7, 1880, x8)

inst_262:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x80000000;  op2val:0x5
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x80000000, 0x5, x7, 1888, x8)

inst_263:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40000000;  op2val:0x1
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40000000, 0x1, x7, 1896, x8)

inst_264:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x60000000;  op2val:0x18
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x60000000, 0x18, x7, 1904, x8)

inst_265:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb0000000;  op2val:0x1e
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb0000000, 0x1e, x7, 1912, x8)

inst_266:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8000000;  op2val:0x1a
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8000000, 0x1a, x7, 1920, x8)

inst_267:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf4000000;  op2val:0x5
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf4000000, 0x5, x7, 1928, x8)

inst_268:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x82000000;  op2val:0xa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x82000000, 0xa, x7, 1936, x8)

inst_269:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfd000000;  op2val:0x3
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfd000000, 0x3, x7, 1944, x8)

inst_270:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xd8800000;  op2val:0xa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xd8800000, 0xa, x7, 1952, x8)

inst_271:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xc8c00000;  op2val:0x14
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xc8c00000, 0x14, x7, 1960, x8)

inst_272:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa3200000;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa3200000, 0x8, x7, 1968, x8)

inst_273:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xc7900000;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xc7900000, 0x1b, x7, 1976, x8)

inst_274:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x46880000;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x46880000, 0x1c, x7, 1984, x8)

inst_275:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x55440000;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x55440000, 0x1b, x7, 1992, x8)

inst_276:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa56a0000;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa56a0000, 0xe, x7, 2000, x8)

inst_277:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x405d0000;  op2val:0x3
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x405d0000, 0x3, x7, 2008, x8)

inst_278:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xcd2f8000;  op2val:0x5
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xcd2f8000, 0x5, x7, 2016, x8)

inst_279:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa6c04000;  op2val:0x19
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa6c04000, 0x19, x7, 2024, x8)

inst_280:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x33bc2000;  op2val:0x15
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x33bc2000, 0x15, x7, 2032, x8)

inst_281:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf1c6b000;  op2val:0xc
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf1c6b000, 0xc, x7, 2040, x8)
RVTEST_SIGBASE(x7,signature_x7_1)

inst_282:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xaa3d6800;  op2val:0xd
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xaa3d6800, 0xd, x7, 0, x8)
RVTEST_SIGBASE(x7,signature_x7_2)

inst_283:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x7aa5e400;  op2val:0xa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x7aa5e400, 0xa, x7, 0, x8)

inst_284:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xc1b7ae00;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xc1b7ae00, 0x1c, x7, 8, x8)

inst_285:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4c56bb00;  op2val:0x9
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4c56bb00, 0x9, x7, 16, x8)

inst_286:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x72c58380;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x72c58380, 0x0, x7, 24, x8)

inst_287:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x32ab8740;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x32ab8740, 0xe, x7, 32, x8)

inst_288:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x96cdf1a0;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x96cdf1a0, 0x1d, x7, 40, x8)

inst_289:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb87a9e30;  op2val:0x11
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb87a9e30, 0x11, x7, 48, x8)

inst_290:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x163dff98;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x163dff98, 0x17, x7, 56, x8)

inst_291:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x9205d39c;  op2val:0x18
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x9205d39c, 0x18, x7, 64, x8)

inst_292:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x50a03c5a;  op2val:0x16
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x50a03c5a, 0x16, x7, 72, x8)

inst_293:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x797d76df;  op2val:0x11
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x797d76df, 0x11, x7, 80, x8)

inst_294:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x24496fe3;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x24496fe3, 0x8, x7, 88, x8)

inst_295:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xde14bff2;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xde14bff2, 0x1d, x7, 96, x8)

inst_296:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb808a677;  op2val:0x3
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb808a677, 0x3, x7, 104, x8)

inst_297:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x76b1fd3d;  op2val:0x7
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x76b1fd3d, 0x7, x7, 112, x8)

inst_298:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x5dcf019d;  op2val:0xf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x5dcf019d, 0xf, x7, 120, x8)

inst_299:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x47b7097b;  op2val:0x1f
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x47b7097b, 0x1f, x7, 128, x8)

inst_300:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x759f1b44;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x759f1b44, 0x10, x7, 136, x8)

inst_301:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x40d90a1d;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x40d90a1d, 0x17, x7, 144, x8)

inst_302:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2dedf123;  op2val:0x16
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2dedf123, 0x16, x7, 152, x8)

inst_303:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4b1634e7;  op2val:0xc
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4b1634e7, 0xc, x7, 160, x8)

inst_304:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8935b82f;  op2val:0xb
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8935b82f, 0xb, x7, 168, x8)

inst_305:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x70bcb8df;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x70bcb8df, 0x1c, x7, 176, x8)

inst_306:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x8de1c73f;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x8de1c73f, 0x8, x7, 184, x8)

inst_307:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb0e04e7f;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb0e04e7f, 0x1c, x7, 192, x8)

inst_308:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x589218ff;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x589218ff, 0x10, x7, 200, x8)

inst_309:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa7be99ff;  op2val:0x7
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa7be99ff, 0x7, x7, 208, x8)

inst_310:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa37e33ff;  op2val:0x14
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa37e33ff, 0x14, x7, 216, x8)

inst_311:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xe37d37ff;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xe37d37ff, 0x1b, x7, 224, x8)

inst_312:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xabb4cfff;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xabb4cfff, 0x17, x7, 232, x8)

inst_313:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x7c9ddfff;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x7c9ddfff, 0x1b, x7, 240, x8)

inst_314:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x5b11bfff;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x5b11bfff, 0xe, x7, 248, x8)

inst_315:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xcb347fff;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xcb347fff, 0x10, x7, 256, x8)

inst_316:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf306ffff;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf306ffff, 0x8, x7, 264, x8)

inst_317:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xbea5ffff;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xbea5ffff, 0x1b, x7, 272, x8)

inst_318:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xd38bffff;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xd38bffff, 0x1c, x7, 280, x8)

inst_319:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x15b7ffff;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x15b7ffff, 0x10, x7, 288, x8)

inst_320:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xd58fffff;  op2val:0x9
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xd58fffff, 0x9, x7, 296, x8)

inst_321:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfe1fffff;  op2val:0x11
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfe1fffff, 0x11, x7, 304, x8)

inst_322:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x203fffff;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x203fffff, 0x0, x7, 312, x8)

inst_323:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x77fffff;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x77fffff, 0x1b, x7, 320, x8)

inst_324:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xbeffffff;  op2val:0x12
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xbeffffff, 0x12, x7, 328, x8)

inst_325:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x89ffffff;  op2val:0xd
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x89ffffff, 0xd, x7, 336, x8)

inst_326:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x23ffffff;  op2val:0x4
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x23ffffff, 0x4, x7, 344, x8)

inst_327:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa7ffffff;  op2val:0xb
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa7ffffff, 0xb, x7, 352, x8)

inst_328:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xcfffffff;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xcfffffff, 0xe, x7, 360, x8)

inst_329:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x9fffffff;  op2val:0x9
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x9fffffff, 0x9, x7, 368, x8)

inst_330:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xbfffffff;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xbfffffff, 0xe, x7, 376, x8)

inst_331:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x7fffffff;  op2val:0xb
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x7fffffff, 0xb, x7, 384, x8)

inst_332:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x12
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffff, 0x12, x7, 392, x8)

inst_333:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x164f1513;  op2val:0x1b
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x164f1513, 0x1b, x7, 400, x8)

inst_334:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xacc6d8f2;  op2val:0x9
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xacc6d8f2, 0x9, x7, 408, x8)

inst_335:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xa123f501;  op2val:0x6
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xa123f501, 0x6, x7, 416, x8)

inst_336:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb57a6a1d;  op2val:0x2
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb57a6a1d, 0x2, x7, 424, x8)

inst_337:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xe90794df;  op2val:0x1
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xe90794df, 0x1, x7, 432, x8)

inst_338:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xaf5570ee;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xaf5570ee, 0x0, x7, 440, x8)

inst_339:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf542441e;  op2val:0x1
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf542441e, 0x1, x7, 448, x8)

inst_340:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x62f28d1b;  op2val:0x4
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x62f28d1b, 0x4, x7, 456, x8)

inst_341:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x38b9b45d;  op2val:0x12
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x38b9b45d, 0x12, x7, 464, x8)

inst_342:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x16809a12;  op2val:0x6
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x16809a12, 0x6, x7, 472, x8)

inst_343:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x82a1750;  op2val:0x6
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x82a1750, 0x6, x7, 480, x8)

inst_344:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x79dd25b;  op2val:0x4
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x79dd25b, 0x4, x7, 488, x8)

inst_345:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x34c687b;  op2val:0x12
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x34c687b, 0x12, x7, 496, x8)

inst_346:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1b601fd;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1b601fd, 0xe, x7, 504, x8)

inst_347:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb302fd;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb302fd, 0x10, x7, 512, x8)

inst_348:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x62a6b3;  op2val:0x5
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x62a6b3, 0x5, x7, 520, x8)

inst_349:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x339238;  op2val:0x11
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x339238, 0x11, x7, 528, x8)

inst_350:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x164af0;  op2val:0x5
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x164af0, 0x5, x7, 536, x8)

inst_351:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x9222a;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x9222a, 0x0, x7, 544, x8)

inst_352:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x6284e;  op2val:0x12
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x6284e, 0x12, x7, 552, x8)

inst_353:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x35161;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x35161, 0xe, x7, 560, x8)

inst_354:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x11e24;  op2val:0xc
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x11e24, 0xc, x7, 568, x8)

inst_355:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf614;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf614, 0x1c, x7, 576, x8)

inst_356:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x5cc1;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x5cc1, 0x1d, x7, 584, x8)

inst_357:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x3226;  op2val:0x1
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x3226, 0x1, x7, 592, x8)

inst_358:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1d0c;  op2val:0xf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1d0c, 0xf, x7, 600, x8)

inst_359:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xdd4;  op2val:0x2
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xdd4, 0x2, x7, 608, x8)

inst_360:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x5d1;  op2val:0x4
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x5d1, 0x4, x7, 616, x8)

inst_361:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x2a7;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x2a7, 0x0, x7, 624, x8)

inst_362:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x197;  op2val:0xa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x197, 0xa, x7, 632, x8)

inst_363:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xb9;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xb9, 0x1c, x7, 640, x8)

inst_364:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x4c;  op2val:0x19
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x4c, 0x19, x7, 648, x8)

inst_365:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x26;  op2val:0x2
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x26, 0x2, x7, 656, x8)

inst_366:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x12;  op2val:0x9
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x12, 0x9, x7, 664, x8)

inst_367:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xc;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xc, 0x1c, x7, 672, x8)

inst_368:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x6;  op2val:0xb
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x6, 0xb, x7, 680, x8)

inst_369:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x3;  op2val:0x1e
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x3, 0x1e, x7, 688, x8)

inst_370:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x1;  op2val:0xc
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x1, 0xc, x7, 696, x8)

inst_371:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x0;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x0, 0x1d, x7, 704, x8)

inst_372:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x59432a19;  op2val:0xf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x59432a19, 0xf, x7, 712, x8)

inst_373:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xceb506f6;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xceb506f6, 0x17, x7, 720, x8)

inst_374:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xc5ec6148;  op2val:0x18
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xc5ec6148, 0x18, x7, 728, x8)

inst_375:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x99ef1857;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x99ef1857, 0x1d, x7, 736, x8)

inst_376:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x14b91c79;  op2val:0x1e
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x14b91c79, 0x1e, x7, 744, x8)

inst_377:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x973e89c;  op2val:0x1f
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x973e89c, 0x1f, x7, 752, x8)

inst_378:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x7843bdb9;  op2val:0x1a
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x7843bdb9, 0x1a, x7, 760, x8)

inst_379:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0x9798c9d0;  op2val:0xe
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0x9798c9d0, 0xe, x7, 768, x8)

inst_380:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xd814d576;  op2val:0xa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xd814d576, 0xa, x7, 776, x8)

inst_381:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xe0a37559;  op2val:0x14
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xe0a37559, 0x14, x7, 784, x8)

inst_382:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf79fb998;  op2val:0x1e
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf79fb998, 0x1e, x7, 792, x8)

inst_383:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xf87a2561;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xf87a2561, 0x1c, x7, 800, x8)

inst_384:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfda56d7f;  op2val:0xf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfda56d7f, 0xf, x7, 808, x8)

inst_385:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfe4deab5;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfe4deab5, 0x17, x7, 816, x8)

inst_386:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xff6875bb;  op2val:0x13
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xff6875bb, 0x13, x7, 824, x8)

inst_387:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xff93d0e4;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xff93d0e4, 0x8, x7, 832, x8)

inst_388:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffd4aa23;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffd4aa23, 0x0, x7, 840, x8)

inst_389:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffe2fc91;  op2val:0x18
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffe2fc91, 0x18, x7, 848, x8)

inst_390:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfff1d2a0;  op2val:0x1c
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfff1d2a0, 0x1c, x7, 856, x8)

inst_391:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfff904d1;  op2val:0xf
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfff904d1, 0xf, x7, 864, x8)

inst_392:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffcdb0b;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffcdb0b, 0x1d, x7, 872, x8)

inst_393:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffec2b4;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffec2b4, 0x17, x7, 880, x8)

inst_394:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffff1e5f;  op2val:0x13
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffff1e5f, 0x13, x7, 888, x8)

inst_395:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffa2ee;  op2val:0xb
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffa2ee, 0xb, x7, 896, x8)

inst_396:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffd410;  op2val:0x10
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffd410, 0x10, x7, 904, x8)

inst_397:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffee0a;  op2val:0x1a
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffee0a, 0x1a, x7, 912, x8)

inst_398:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffff32a;  op2val:0x16
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffff32a, 0x16, x7, 920, x8)

inst_399:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffb84;  op2val:0x8
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffb84, 0x8, x7, 928, x8)

inst_400:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffc1d;  op2val:0x1a
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffc1d, 0x1a, x7, 936, x8)

inst_401:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffe31;  op2val:0x17
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffe31, 0x17, x7, 944, x8)

inst_402:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffff44;  op2val:0x4
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffff44, 0x4, x7, 952, x8)

inst_403:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffba;  op2val:0x1f
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffba, 0x1f, x7, 960, x8)

inst_404:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffc6;  op2val:0xa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffc6, 0xa, x7, 968, x8)

inst_405:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffe8;  op2val:0x11
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffe8, 0x11, x7, 976, x8)

inst_406:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffff2;  op2val:0x1f
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffff2, 0x1f, x7, 984, x8)

inst_407:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffff9;  op2val:0x1d
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffff9, 0x1d, x7, 992, x8)

inst_408:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffd;  op2val:0x0
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffd, 0x0, x7, 1000, x8)

inst_409:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffe;  op2val:0x1e
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffe, 0x1e, x7, 1008, x8)

inst_410:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x2
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xffffffff, 0x2, x7, 1016, x8)

inst_411:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xaaaaaaaaaaaaaaaa
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xaaaaaaaaaaaaaaaa, x7, 1024, x8)

inst_412:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0x5555555555555555
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0x5555555555555555, x7, 1032, x8)

inst_413:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xaaaaaaaaaaaaaaaa;  op2val:0xfffffffffffffbff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xaaaaaaaaaaaaaaaa, 0xfffffffffffffbff, x7, 1040, x8)

inst_414:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xdfffffffffffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xdfffffffffffffff, x7, 1048, x8)

inst_415:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xefffffffffffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xefffffffffffffff, x7, 1056, x8)

inst_416:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffbffffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffbffffffff, x7, 1064, x8)

inst_417:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xfffffffeffffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffeffffffff, x7, 1072, x8)

inst_418:
// 
// opcode: bext ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffffffffbff;  op2val:0xffffffff7fffffff
TEST_RR_OP(bext, x31, x30, x29, 0x0000000000000000, 0xfffffffffffffbff, 0xffffffff7fffffff, x7, 1080, x8)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 26*(XLEN/32),4,0xdeadbeef


signature_x7_0:
    .fill 256*(XLEN/32),4,0xdeadbeef


signature_x7_1:
    .fill 1*(XLEN/32),4,0xdeadbeef


signature_x7_2:
    .fill 136*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
