
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 05:22:24 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x5,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd != rs2, rs1==x22, rs2==x29, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x3b2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x22; op2:x29; dest:x22; op1val:0x1f; op2val:0x4fb2;
   valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x22, x22, x29, dyn, 0, 0, x5, 0*FLEN/8, x15, x1, x13)

inst_1:
// rs1 == rs2 != rd, rs1==x16, rs2==x16, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x060 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x16; op2:x16; dest:x10; op1val:0x46; op2val:0x46;
   valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x10, x16, x16, dyn, 0, 0, x5, 2*FLEN/8, x15, x1, x13)

inst_2:
// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0;
   valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x0, x0, x0, dyn, 0, 0, x5, 4*FLEN/8, x15, x1, x13)

inst_3:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x26, rs2==x8, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x26; op2:x8; dest:x11; op1val:0x3d; op2val:0x47a0;
   valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x11, x26, x8, dyn, 0, 0, x5, 6*FLEN/8, x15, x1, x13)

inst_4:
// rs2 == rd != rs1, rs1==x20, rs2==x23, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x20; op2:x23; dest:x23; op1val:0x4b; op2val:0x44b0;
   valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x23, x20, x23, dyn, 0, 0, x5, 8*FLEN/8, x15, x1, x13)

inst_5:
// rs1==x25, rs2==x7, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x25; op2:x7; dest:x12; op1val:0x4e; op2val:0x40e0;
   valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x12, x25, x7, dyn, 0, 0, x5, 10*FLEN/8, x15, x1, x13)

inst_6:
// rs1==x10, rs2==x14, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x10; op2:x14; dest:x28; op1val:0x3d; op2val:0x3ba0;
   valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x28, x10, x14, dyn, 0, 0, x5, 12*FLEN/8, x15, x1, x13)

inst_7:
// rs1==x28, rs2==x10, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x28; op2:x10; dest:x25; op1val:0x47; op2val:0x3870;
   valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x25, x28, x10, dyn, 0, 0, x5, 14*FLEN/8, x15, x1, x13)

inst_8:
// rs1==x3, rs2==x17, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x240 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x3; op2:x17; dest:x24; op1val:0x19; op2val:0x2e40;
   valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x24, x3, x17, dyn, 0, 0, x5, 16*FLEN/8, x15, x1, x13)

inst_9:
// rs1==x30, rs2==x26, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x26; dest:x17; op1val:0x3d; op2val:0x2fa0;
   valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x17, x30, x26, dyn, 0, 0, x5, 18*FLEN/8, x15, x1, x13)

inst_10:
// rs1==x17, rs2==x28, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x068 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x17; op2:x28; dest:x6; op1val:0x47; op2val:0xd468;
   valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x6, x17, x28, dyn, 0, 0, x5, 20*FLEN/8, x15, x1, x13)

inst_11:
// rs1==x14, rs2==x25, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x260 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x14; op2:x25; dest:x2; op1val:0x33; op2val:0xce60;
   valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x2, x14, x25, dyn, 0, 0, x5, 22*FLEN/8, x15, x1, x13)

inst_12:
// rs1==x27, rs2==x3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x100 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x27; op2:x3; dest:x4; op1val:0x14; op2val:0xc500;
   valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x4, x27, x3, dyn, 0, 0, x5, 24*FLEN/8, x15, x1, x13)

inst_13:
// rs1==x9, rs2==x27, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x120 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x9; op2:x27; dest:x19; op1val:0x52; op2val:0xc920;
   valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x19, x9, x27, dyn, 0, 0, x5, 26*FLEN/8, x15, x1, x13)
RVTEST_VALBASEUPD(x14,test_dataset_1)

inst_14:
// rs1==x2, rs2==x4, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x2; op2:x4; dest:x20; op1val:0x43; op2val:0xc430;
   valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x20, x2, x4, dyn, 0, 0, x14, 0*FLEN/8, x17, x1, x13)

inst_15:
// rs1==x5, rs2==x6, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x5; op2:x6; dest:x29; op1val:0x5f; op2val:0xc1f0;
   valaddr_reg:x14; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x13
*/
TEST_FPRR_OP(fdiv.h, x29, x5, x6, dyn, 0, 0, x14, 2*FLEN/8, x17, x1, x13)

inst_16:
// rs1==x18, rs2==x9, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x160 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x18; op2:x9; dest:x31; op1val:0x56; op2val:0xbd60;
   valaddr_reg:x14; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x31, x18, x9, dyn, 0, 0, x14, 4*FLEN/8, x17, x1, x16)
RVTEST_SIGBASE(x10,signature_x10_0)

inst_17:
// rs1==x31, rs2==x2, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x140 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x31; op2:x2; dest:x27; op1val:0x15; op2val:0xb140;
   valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x27, x31, x2, dyn, 0, 0, x14, 6*FLEN/8, x17, x10, x16)

inst_18:
// rs1==x12, rs2==x13, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x12; op2:x13; dest:x1; op1val:0x4c; op2val:0xb4c0;
   valaddr_reg:x14; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x1, x12, x13, dyn, 0, 0, x14, 8*FLEN/8, x17, x10, x16)

inst_19:
// rs1==x7, rs2==x22, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x7; op2:x22; dest:x15; op1val:0x27; op2val:0xace0;
   valaddr_reg:x14; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x15, x7, x22, dyn, 0, 0, x14, 10*FLEN/8, x17, x10, x16)

inst_20:
// rs1==x29, rs2==x1, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x021 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x29; op2:x1; dest:x8; op1val:0x3c23; op2val:0x3c21;
   valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x8, x29, x1, dyn, 0, 0, x14, 12*FLEN/8, x17, x10, x16)

inst_21:
// rs1==x19, rs2==x31, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x04a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x19; op2:x31; dest:x30; op1val:0x3c4d; op2val:0x3c4a;
   valaddr_reg:x14; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x30, x19, x31, dyn, 0, 0, x14, 14*FLEN/8, x17, x10, x16)

inst_22:
// rs1==x21, rs2==x19, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x032 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x21; op2:x19; dest:x13; op1val:0x3c32; op2val:0x3c2d;
   valaddr_reg:x14; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x13, x21, x19, dyn, 0, 0, x14, 16*FLEN/8, x17, x10, x16)

inst_23:
// rs1==x15, rs2==x12, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x037 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x15; op2:x12; dest:x7; op1val:0x3c37; op2val:0x3c2e;
   valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x7, x15, x12, dyn, 0, 0, x14, 18*FLEN/8, x17, x10, x16)

inst_24:
// rs1==x4, rs2==x11, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x4; op2:x11; dest:x3; op1val:0x3c5e; op2val:0x3c4c;
   valaddr_reg:x14; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x3, x4, x11, dyn, 0, 0, x14, 20*FLEN/8, x17, x10, x16)

inst_25:
// rs1==x11, rs2==x5, rd==x21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x018 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x11; op2:x5; dest:x21; op1val:0x3c39; op2val:0x3c18;
   valaddr_reg:x14; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x21, x11, x5, dyn, 0, 0, x14, 22*FLEN/8, x17, x10, x16)

inst_26:
// rs1==x23, rs2==x24, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x23; op2:x24; dest:x9; op1val:0x3c2f; op2val:0x3be0;
   valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x9, x23, x24, dyn, 0, 0, x14, 24*FLEN/8, x17, x10, x16)
RVTEST_VALBASEUPD(x3,test_dataset_2)

inst_27:
// rs1==x1, rs2==x21, rd==x18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x005 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x325 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x1; op2:x21; dest:x18; op1val:0x3c05; op2val:0x3b25;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x18, x1, x21, dyn, 0, 0, x3, 0*FLEN/8, x4, x10, x16)

inst_28:
// rs1==x24, rs2==x15, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2cc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x24; op2:x15; dest:x14; op1val:0x3c40; op2val:0x3acc;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x14, x24, x15, dyn, 0, 0, x3, 2*FLEN/8, x4, x10, x16)

inst_29:
// rs1==x6, rs2==x30, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x022 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x182 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x6; op2:x30; dest:x26; op1val:0x3c22; op2val:0x3982;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x16
*/
TEST_FPRR_OP(fdiv.h, x26, x6, x30, dyn, 0, 0, x3, 4*FLEN/8, x4, x10, x16)

inst_30:
// rs1==x13, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x0f and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x036 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x13; op2:x20; dest:x16; op1val:0x3c38; op2val:0xbc36;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x16, x13, x20, dyn, 0, 0, x3, 6*FLEN/8, x4, x10, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_31:
// rs1==x8, rs2==x18, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x024 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x8; op2:x18; dest:x5; op1val:0x3c27; op2val:0xbc24;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x5, x8, x18, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c41; op2val:0xbc3c;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x041 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c4a; op2val:0xbc41;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x045 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c45; op2val:0xbc34;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x014 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c35; op2val:0xbc14;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x01e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c1e; op2val:0xbbc0;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c58; op2val:0xbbb8;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c24; op2val:0xbaa0;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x056 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3c56; op2val:0xb9c8;
   valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x137 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x15; op2val:0x4d37;
   valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x300 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2a; op2val:0x4b00;
   valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x366 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4a; op2val:0x4b66;
   valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x238 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0x3e38;
   valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x54; op2val:0x44f0;
   valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0f8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x52; op2val:0x40f8;
   valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x23; op2val:0x384e;
   valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x10; op2val:0x2ff0;
   valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0c and fm2 == 0x3b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e; op2val:0x33b8;
   valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3bc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3e; op2val:0x2fbc;
   valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x196 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2d; op2val:0xd196;
   valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x06a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0xcc6a;
   valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0cc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x3; op2val:0xb8cc;
   valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x21c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x37; op2val:0xc61c;
   valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x36; op2val:0xc25a;
   valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xb1d1;
   valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0dc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0xbcdc;
   valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1f4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0xa9f4;
   valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ba and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5c; op2val:0xb5ba;
   valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x2b; op2val:0xad5d;
   valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x082 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x24; op2val:0x2882;
   valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x09 and fm2 == 0x3c5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x1f; op2val:0x27c5;
   valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x106 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x28; op2val:0x2906;
   valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 0 and fe2 == 0x08 and fm2 == 0x10b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xa; op2val:0x210b;
   valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0e4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4d; op2val:0x2ce4;
   valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x12a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5; op2val:0x1d2a;
   valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x312 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x35; op2val:0x2b12;
   valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1a6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x4f; op2val:0x2da6;
   valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x2ac and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x14; op2val:0x26ac;
   valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x203 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x6; op2val:0x2203;
   valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x122 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x29; op2val:0xa922;
   valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x083 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x12; op2val:0xa483;
   valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x227 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x31; op2val:0xaa27;
   valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x039 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x43; op2val:0xac39;
   valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x053 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x146 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x53; op2val:0xad46;
   valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x58; op2val:0xadae;
   valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x08 and fm2 == 0x379 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0xe; op2val:0xa379;
   valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0a5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x41; op2val:0xaca5;
   valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ac and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x38; op2val:0xacac;
   valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1d2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x5d; op2val:0xb1d2;
   valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x41f; op2val:0x3c1d;
   valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x035 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x438; op2val:0x3c35;
   valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x043 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x443; op2val:0x3c3e;
   valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x03e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x447; op2val:0x3c3e;
   valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x402; op2val:0x3be4;
   valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x029 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44b; op2val:0x3c29;
   valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x403; op2val:0x3b8d;
   valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44f; op2val:0x3ba8;
   valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x051 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2e8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x451; op2val:0x3ae8;
   valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x160 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x408; op2val:0x3960;
   valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x04f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x451; op2val:0xbc4f;
   valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x039 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x43c; op2val:0xbc39;
   valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x052 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0xbc52;
   valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x045 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44e; op2val:0xbc45;
   valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x424; op2val:0xbc13;
   valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x43f; op2val:0xbc1e;
   valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x44c; op2val:0xbc0b;
   valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x457; op2val:0xbbb7;
   valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x430; op2val:0xbab3;
   valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1c1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x451; op2val:0xb9c1;
   valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x027 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x028 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7827; op2val:0x3828;
   valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x384e;
   valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x019 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x3819;
   valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x01c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7818; op2val:0x381c;
   valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x06b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7862; op2val:0x386b;
   valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x05f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x784d; op2val:0x385f;
   valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x027 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x049 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7827; op2val:0x3849;
   valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x053 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x3853;
   valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x097 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x3897;
   valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7858; op2val:0x39cb;
   valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 164*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7811; op2val:0xb812;
   valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 166*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7841; op2val:0xb842;
   valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x056 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7854; op2val:0xb856;
   valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x781f; op2val:0xb823;
   valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 172*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x020 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7818; op2val:0xb820;
   valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x049 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7838; op2val:0xb849;
   valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 176*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x785a; op2val:0xb87e;
   valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 178*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0xb853;
   valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0xb8c2;
   valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 182*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ca and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7857; op2val:0xb9ca;
   valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 184*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x060 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x46; op2val:0x5060;
   valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x30; op2val:0x4a00;
   valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31,32,FLEN)
NAN_BOXED(20402,32,FLEN)
NAN_BOXED(70,32,FLEN)
NAN_BOXED(70,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(61,32,FLEN)
NAN_BOXED(18336,32,FLEN)
NAN_BOXED(75,32,FLEN)
NAN_BOXED(17584,32,FLEN)
NAN_BOXED(78,32,FLEN)
NAN_BOXED(16608,32,FLEN)
NAN_BOXED(61,32,FLEN)
NAN_BOXED(15264,32,FLEN)
NAN_BOXED(71,32,FLEN)
NAN_BOXED(14448,32,FLEN)
NAN_BOXED(25,32,FLEN)
NAN_BOXED(11840,32,FLEN)
NAN_BOXED(61,32,FLEN)
NAN_BOXED(12192,32,FLEN)
NAN_BOXED(71,32,FLEN)
NAN_BOXED(54376,16,FLEN)
NAN_BOXED(51,32,FLEN)
NAN_BOXED(52832,16,FLEN)
NAN_BOXED(20,32,FLEN)
NAN_BOXED(50432,16,FLEN)
NAN_BOXED(82,32,FLEN)
NAN_BOXED(51488,16,FLEN)
test_dataset_1:
NAN_BOXED(67,32,FLEN)
NAN_BOXED(50224,16,FLEN)
NAN_BOXED(95,32,FLEN)
NAN_BOXED(49648,16,FLEN)
NAN_BOXED(86,32,FLEN)
NAN_BOXED(48480,16,FLEN)
NAN_BOXED(21,32,FLEN)
NAN_BOXED(45376,16,FLEN)
NAN_BOXED(76,32,FLEN)
NAN_BOXED(46272,16,FLEN)
NAN_BOXED(39,32,FLEN)
NAN_BOXED(44256,16,FLEN)
NAN_BOXED(15395,32,FLEN)
NAN_BOXED(15393,32,FLEN)
NAN_BOXED(15437,32,FLEN)
NAN_BOXED(15434,32,FLEN)
NAN_BOXED(15410,32,FLEN)
NAN_BOXED(15405,32,FLEN)
NAN_BOXED(15415,32,FLEN)
NAN_BOXED(15406,32,FLEN)
NAN_BOXED(15454,32,FLEN)
NAN_BOXED(15436,32,FLEN)
NAN_BOXED(15417,32,FLEN)
NAN_BOXED(15384,32,FLEN)
NAN_BOXED(15407,32,FLEN)
NAN_BOXED(15328,32,FLEN)
test_dataset_2:
NAN_BOXED(15365,16,FLEN)
NAN_BOXED(15141,16,FLEN)
NAN_BOXED(15424,16,FLEN)
NAN_BOXED(15052,16,FLEN)
NAN_BOXED(15394,16,FLEN)
NAN_BOXED(14722,16,FLEN)
NAN_BOXED(15416,16,FLEN)
NAN_BOXED(48182,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(48164,16,FLEN)
NAN_BOXED(15425,16,FLEN)
NAN_BOXED(48188,16,FLEN)
NAN_BOXED(15434,16,FLEN)
NAN_BOXED(48193,16,FLEN)
NAN_BOXED(15429,16,FLEN)
NAN_BOXED(48180,16,FLEN)
NAN_BOXED(15413,16,FLEN)
NAN_BOXED(48148,16,FLEN)
NAN_BOXED(15390,16,FLEN)
NAN_BOXED(48064,16,FLEN)
NAN_BOXED(15448,16,FLEN)
NAN_BOXED(48056,16,FLEN)
NAN_BOXED(15396,16,FLEN)
NAN_BOXED(47776,16,FLEN)
NAN_BOXED(15446,16,FLEN)
NAN_BOXED(47560,16,FLEN)
NAN_BOXED(21,16,FLEN)
NAN_BOXED(19767,16,FLEN)
NAN_BOXED(42,16,FLEN)
NAN_BOXED(19200,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(19302,16,FLEN)
NAN_BOXED(14,16,FLEN)
NAN_BOXED(15928,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(17648,16,FLEN)
NAN_BOXED(82,16,FLEN)
NAN_BOXED(16632,16,FLEN)
NAN_BOXED(35,16,FLEN)
NAN_BOXED(14414,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(12272,16,FLEN)
NAN_BOXED(62,16,FLEN)
NAN_BOXED(13240,16,FLEN)
NAN_BOXED(62,16,FLEN)
NAN_BOXED(12220,16,FLEN)
NAN_BOXED(45,16,FLEN)
NAN_BOXED(53654,16,FLEN)
NAN_BOXED(53,16,FLEN)
NAN_BOXED(52330,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(47308,16,FLEN)
NAN_BOXED(55,16,FLEN)
NAN_BOXED(50716,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(49754,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(45521,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(48348,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(43508,16,FLEN)
NAN_BOXED(92,16,FLEN)
NAN_BOXED(46522,16,FLEN)
NAN_BOXED(43,16,FLEN)
NAN_BOXED(44381,16,FLEN)
NAN_BOXED(36,16,FLEN)
NAN_BOXED(10370,16,FLEN)
NAN_BOXED(31,16,FLEN)
NAN_BOXED(10181,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(10502,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(8459,16,FLEN)
NAN_BOXED(77,16,FLEN)
NAN_BOXED(11492,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(7466,16,FLEN)
NAN_BOXED(53,16,FLEN)
NAN_BOXED(11026,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(11686,16,FLEN)
NAN_BOXED(20,16,FLEN)
NAN_BOXED(9900,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(8707,16,FLEN)
NAN_BOXED(41,16,FLEN)
NAN_BOXED(43298,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(42115,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(43559,16,FLEN)
NAN_BOXED(67,16,FLEN)
NAN_BOXED(44089,16,FLEN)
NAN_BOXED(83,16,FLEN)
NAN_BOXED(44358,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(44462,16,FLEN)
NAN_BOXED(14,16,FLEN)
NAN_BOXED(41849,16,FLEN)
NAN_BOXED(65,16,FLEN)
NAN_BOXED(44197,16,FLEN)
NAN_BOXED(56,16,FLEN)
NAN_BOXED(44204,16,FLEN)
NAN_BOXED(93,16,FLEN)
NAN_BOXED(45522,16,FLEN)
NAN_BOXED(1055,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(1080,16,FLEN)
NAN_BOXED(15413,16,FLEN)
NAN_BOXED(1091,16,FLEN)
NAN_BOXED(15422,16,FLEN)
NAN_BOXED(1095,16,FLEN)
NAN_BOXED(15422,16,FLEN)
NAN_BOXED(1026,16,FLEN)
NAN_BOXED(15332,16,FLEN)
NAN_BOXED(1099,16,FLEN)
NAN_BOXED(15401,16,FLEN)
NAN_BOXED(1027,16,FLEN)
NAN_BOXED(15245,16,FLEN)
NAN_BOXED(1103,16,FLEN)
NAN_BOXED(15272,16,FLEN)
NAN_BOXED(1105,16,FLEN)
NAN_BOXED(15080,16,FLEN)
NAN_BOXED(1032,16,FLEN)
NAN_BOXED(14688,16,FLEN)
NAN_BOXED(1105,16,FLEN)
NAN_BOXED(48207,16,FLEN)
NAN_BOXED(1084,16,FLEN)
NAN_BOXED(48185,16,FLEN)
NAN_BOXED(1111,16,FLEN)
NAN_BOXED(48210,16,FLEN)
NAN_BOXED(1102,16,FLEN)
NAN_BOXED(48197,16,FLEN)
NAN_BOXED(1060,16,FLEN)
NAN_BOXED(48147,16,FLEN)
NAN_BOXED(1087,16,FLEN)
NAN_BOXED(48158,16,FLEN)
NAN_BOXED(1100,16,FLEN)
NAN_BOXED(48139,16,FLEN)
NAN_BOXED(1111,16,FLEN)
NAN_BOXED(48055,16,FLEN)
NAN_BOXED(1072,16,FLEN)
NAN_BOXED(47795,16,FLEN)
NAN_BOXED(1105,16,FLEN)
NAN_BOXED(47553,16,FLEN)
NAN_BOXED(30759,16,FLEN)
NAN_BOXED(14376,16,FLEN)
NAN_BOXED(30797,16,FLEN)
NAN_BOXED(14414,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(14361,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(14364,16,FLEN)
NAN_BOXED(30818,16,FLEN)
NAN_BOXED(14443,16,FLEN)
NAN_BOXED(30797,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(30759,16,FLEN)
NAN_BOXED(14409,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(14419,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(14487,16,FLEN)
NAN_BOXED(30808,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(30737,16,FLEN)
NAN_BOXED(47122,16,FLEN)
NAN_BOXED(30785,16,FLEN)
NAN_BOXED(47170,16,FLEN)
NAN_BOXED(30804,16,FLEN)
NAN_BOXED(47190,16,FLEN)
NAN_BOXED(30751,16,FLEN)
NAN_BOXED(47139,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(47136,16,FLEN)
NAN_BOXED(30776,16,FLEN)
NAN_BOXED(47177,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(47230,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(47187,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(47298,16,FLEN)
NAN_BOXED(30807,16,FLEN)
NAN_BOXED(47562,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(20576,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(18944,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 34*((SIGALIGN)/4),4,0xdeadbeef


signature_x10_0:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 182*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
