
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon May  8 04:56:42 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsh.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsh instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fsh-align covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfh.*);def TEST_CASE_1=True;",fsh-align)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1==x31, rs2==f31,ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode: fsh; op1:x31; op2:f31; op2val:0xabcdef12; immval:-0x4; align:0; flagreg:x4;
// valreg: x3; valoffset: 0*FLEN/4
TEST_STORE_F(x1,x2,159,x31,f31,-0x4,0*SIGALIGN,fsh,0,x4,x3, 0*FLEN/4)

inst_1:// rs1==x30, rs2==f30,ea_align == 0 and (imm_val % 4) == 1, 
// opcode: fsh; op1:x30; op2:f30; op2val:0xabcdef12; immval:-0x3; align:0; flagreg:x4;
// valreg: x3; valoffset: 1*FLEN/4
TEST_STORE_F(x1,x2,159,x30,f30,-0x3,2*SIGALIGN,fsh,0,x4,x3, 1*FLEN/4)

inst_2:// rs1==x29, rs2==f29,ea_align == 0 and (imm_val % 4) == 2, 
// opcode: fsh; op1:x29; op2:f29; op2val:0xabcdef12; immval:-0x6; align:0; flagreg:x4;
// valreg: x3; valoffset: 2*FLEN/4
TEST_STORE_F(x1,x2,159,x29,f29,-0x6,4*SIGALIGN,fsh,0,x4,x3, 2*FLEN/4)

inst_3:// rs1==x28, rs2==f28,ea_align == 0 and (imm_val % 4) == 3, imm_val > 0
// opcode: fsh; op1:x28; op2:f28; op2val:0xabcdef12; immval:0x7ff; align:0; flagreg:x4;
// valreg: x3; valoffset: 3*FLEN/4
TEST_STORE_F(x1,x2,159,x28,f28,0x7ff,6*SIGALIGN,fsh,0,x4,x3, 3*FLEN/4)

inst_4:// rs1==x27, rs2==f27,imm_val == 0, 
// opcode: fsh; op1:x27; op2:f27; op2val:0xabcdef12; immval:0x0; align:0; flagreg:x4;
// valreg: x3; valoffset: 4*FLEN/4
TEST_STORE_F(x1,x2,159,x27,f27,0x0,8*SIGALIGN,fsh,0,x4,x3, 4*FLEN/4)

inst_5:// rs1==x26, rs2==f26,
// opcode: fsh; op1:x26; op2:f26; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 5*FLEN/4
TEST_STORE_F(x1,x2,0,x26,f26,-0x800,10*SIGALIGN,fsh,0,x4,x3, 5*FLEN/4)

inst_6:// rs1==x25, rs2==f25,
// opcode: fsh; op1:x25; op2:f25; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 6*FLEN/4
TEST_STORE_F(x1,x2,0,x25,f25,-0x800,12*SIGALIGN,fsh,0,x4,x3, 6*FLEN/4)

inst_7:// rs1==x24, rs2==f24,
// opcode: fsh; op1:x24; op2:f24; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 7*FLEN/4
TEST_STORE_F(x1,x2,0,x24,f24,-0x800,14*SIGALIGN,fsh,0,x4,x3, 7*FLEN/4)

inst_8:// rs1==x23, rs2==f23,
// opcode: fsh; op1:x23; op2:f23; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 8*FLEN/4
TEST_STORE_F(x1,x2,0,x23,f23,-0x800,16*SIGALIGN,fsh,0,x4,x3, 8*FLEN/4)

inst_9:// rs1==x22, rs2==f22,
// opcode: fsh; op1:x22; op2:f22; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 9*FLEN/4
TEST_STORE_F(x1,x2,0,x22,f22,-0x800,18*SIGALIGN,fsh,0,x4,x3, 9*FLEN/4)

inst_10:// rs1==x21, rs2==f21,
// opcode: fsh; op1:x21; op2:f21; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 10*FLEN/4
TEST_STORE_F(x1,x2,0,x21,f21,-0x800,20*SIGALIGN,fsh,0,x4,x3, 10*FLEN/4)

inst_11:// rs1==x20, rs2==f20,
// opcode: fsh; op1:x20; op2:f20; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 11*FLEN/4
TEST_STORE_F(x1,x2,0,x20,f20,-0x800,22*SIGALIGN,fsh,0,x4,x3, 11*FLEN/4)

inst_12:// rs1==x19, rs2==f19,
// opcode: fsh; op1:x19; op2:f19; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 12*FLEN/4
TEST_STORE_F(x1,x2,0,x19,f19,-0x800,24*SIGALIGN,fsh,0,x4,x3, 12*FLEN/4)

inst_13:// rs1==x18, rs2==f18,
// opcode: fsh; op1:x18; op2:f18; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 13*FLEN/4
TEST_STORE_F(x1,x2,0,x18,f18,-0x800,26*SIGALIGN,fsh,0,x4,x3, 13*FLEN/4)

inst_14:// rs1==x17, rs2==f17,
// opcode: fsh; op1:x17; op2:f17; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 14*FLEN/4
TEST_STORE_F(x1,x2,0,x17,f17,-0x800,28*SIGALIGN,fsh,0,x4,x3, 14*FLEN/4)

inst_15:// rs1==x16, rs2==f16,
// opcode: fsh; op1:x16; op2:f16; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 15*FLEN/4
TEST_STORE_F(x1,x2,0,x16,f16,-0x800,30*SIGALIGN,fsh,0,x4,x3, 15*FLEN/4)

inst_16:// rs1==x15, rs2==f15,
// opcode: fsh; op1:x15; op2:f15; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 16*FLEN/4
TEST_STORE_F(x1,x2,0,x15,f15,-0x800,32*SIGALIGN,fsh,0,x4,x3, 16*FLEN/4)

inst_17:// rs1==x14, rs2==f14,
// opcode: fsh; op1:x14; op2:f14; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 17*FLEN/4
TEST_STORE_F(x1,x2,0,x14,f14,-0x800,34*SIGALIGN,fsh,0,x4,x3, 17*FLEN/4)

inst_18:// rs1==x13, rs2==f13,
// opcode: fsh; op1:x13; op2:f13; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 18*FLEN/4
TEST_STORE_F(x1,x2,0,x13,f13,-0x800,36*SIGALIGN,fsh,0,x4,x3, 18*FLEN/4)

inst_19:// rs1==x12, rs2==f12,
// opcode: fsh; op1:x12; op2:f12; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 19*FLEN/4
TEST_STORE_F(x1,x2,0,x12,f12,-0x800,38*SIGALIGN,fsh,0,x4,x3, 19*FLEN/4)

inst_20:// rs1==x11, rs2==f11,
// opcode: fsh; op1:x11; op2:f11; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 20*FLEN/4
TEST_STORE_F(x1,x2,0,x11,f11,-0x800,40*SIGALIGN,fsh,0,x4,x3, 20*FLEN/4)

inst_21:// rs1==x10, rs2==f10,
// opcode: fsh; op1:x10; op2:f10; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 21*FLEN/4
TEST_STORE_F(x1,x2,0,x10,f10,-0x800,42*SIGALIGN,fsh,0,x4,x3, 21*FLEN/4)

inst_22:// rs1==x9, rs2==f9,
// opcode: fsh; op1:x9; op2:f9; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 22*FLEN/4
TEST_STORE_F(x1,x2,0,x9,f9,-0x800,44*SIGALIGN,fsh,0,x4,x3, 22*FLEN/4)

inst_23:// rs1==x8, rs2==f8,
// opcode: fsh; op1:x8; op2:f8; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x4;
// valreg: x3; valoffset: 23*FLEN/4
TEST_STORE_F(x1,x2,0,x8,f8,-0x800,46*SIGALIGN,fsh,0,x4,x3, 23*FLEN/4)
RVTEST_VALBASEUPD(x8,test_dataset_1)

inst_24:// rs1==x7, rs2==f7,
// opcode: fsh; op1:x7; op2:f7; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 0*FLEN/4
TEST_STORE_F(x1,x2,0,x7,f7,-0x800,48*SIGALIGN,fsh,0,x9,x8, 0*FLEN/4)

inst_25:// rs1==x6, rs2==f6,
// opcode: fsh; op1:x6; op2:f6; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 1*FLEN/4
TEST_STORE_F(x1,x2,0,x6,f6,-0x800,50*SIGALIGN,fsh,0,x9,x8, 1*FLEN/4)

inst_26:// rs1==x5, rs2==f5,
// opcode: fsh; op1:x5; op2:f5; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 2*FLEN/4
TEST_STORE_F(x1,x6,0,x5,f5,-0x800,52*SIGALIGN,fsh,0,x9,x8, 2*FLEN/4)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_27:// rs1==x4, rs2==f4,
// opcode: fsh; op1:x4; op2:f4; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 3*FLEN/4
TEST_STORE_F(x5,x6,0,x4,f4,-0x800,0*SIGALIGN,fsh,0,x9,x8, 3*FLEN/4)

inst_28:// rs1==x3, rs2==f3,
// opcode: fsh; op1:x3; op2:f3; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 4*FLEN/4
TEST_STORE_F(x5,x6,0,x3,f3,-0x800,2*SIGALIGN,fsh,0,x9,x8, 4*FLEN/4)

inst_29:// rs1==x2, rs2==f2,
// opcode: fsh; op1:x2; op2:f2; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 5*FLEN/4
TEST_STORE_F(x5,x6,0,x2,f2,-0x800,4*SIGALIGN,fsh,0,x9,x8, 5*FLEN/4)

inst_30:// rs1==x1, rs2==f1,
// opcode: fsh; op1:x1; op2:f1; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 6*FLEN/4
TEST_STORE_F(x5,x6,0,x1,f1,-0x800,6*SIGALIGN,fsh,0,x9,x8, 6*FLEN/4)

inst_31:// rs2==f0,
// opcode: fsh; op1:x31; op2:f0; op2val:0xabcdef12; immval:-0x800; align:0; flagreg:x9;
// valreg: x8; valoffset: 7*FLEN/4
TEST_STORE_F(x5,x6,0,x31,f0,-0x800,8*SIGALIGN,fsh,0,x9,x8, 7*FLEN/4)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2882400018,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 54*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
