
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Thu Jul  6 07:22:07 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zdinx/fcvt.l.d.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.l.d instruction of the RISC-V RV64_Zfinx_Zdinx extension for the fcvt.l.d_b23 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zdinx.*);def TEST_CASE_1=True;",fcvt.l.d_b23)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x5,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1==x28, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x28; dest:x30; op1val:0x43dffffffffffffc; valaddr_reg:x5;
val_offset:0*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x30, x28, dyn, 0, 0, x5, 0*FLEN/8, x7, x1, x3,LREG)

inst_1:// rs1==x30, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x28; op1val:0x43dffffffffffffc; valaddr_reg:x5;
val_offset:1*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x28, x30, dyn, 32, 0, x5, 1*FLEN/8, x7, x1, x3,LREG)

inst_2:// rs1==x24, rd==x26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x24; dest:x26; op1val:0x43dffffffffffffc; valaddr_reg:x5;
val_offset:2*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x26, x24, dyn, 64, 0, x5, 2*FLEN/8, x7, x1, x3,LREG)

inst_3:// rs1==x26, rd==x24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x26; dest:x24; op1val:0x43dffffffffffffc; valaddr_reg:x5;
val_offset:3*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x24, x26, dyn, 96, 0, x5, 3*FLEN/8, x7, x1, x3,LREG)

inst_4:// rs1==x20, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x20; dest:x22; op1val:0x43dffffffffffffc; valaddr_reg:x5;
val_offset:4*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x22, x20, dyn, 128, 0, x5, 4*FLEN/8, x7, x1, x3,LREG)

inst_5:// rs1==x22, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x22; dest:x20; op1val:0x43dffffffffffffd; valaddr_reg:x5;
val_offset:5*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x20, x22, dyn, 0, 0, x5, 5*FLEN/8, x7, x1, x3,LREG)

inst_6:// rs1==x16, rd==x18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x16; dest:x18; op1val:0x43dffffffffffffd; valaddr_reg:x5;
val_offset:6*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x18, x16, dyn, 32, 0, x5, 6*FLEN/8, x7, x1, x3,LREG)

inst_7:// rs1==x18, rd==x16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x18; dest:x16; op1val:0x43dffffffffffffd; valaddr_reg:x5;
val_offset:7*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x16, x18, dyn, 64, 0, x5, 7*FLEN/8, x7, x1, x3,LREG)

inst_8:// rs1==x12, rd==x14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x12; dest:x14; op1val:0x43dffffffffffffd; valaddr_reg:x5;
val_offset:8*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x14, x12, dyn, 96, 0, x5, 8*FLEN/8, x7, x1, x3,LREG)

inst_9:// rs1==x14, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x14; dest:x12; op1val:0x43dffffffffffffd; valaddr_reg:x5;
val_offset:9*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x12, x14, dyn, 128, 0, x5, 9*FLEN/8, x7, x1, x3,LREG)

inst_10:// rs1==x8, rd==x10,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x8; dest:x10; op1val:0x43dffffffffffffe; valaddr_reg:x5;
val_offset:10*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x10, x8, dyn, 0, 0, x5, 10*FLEN/8, x7, x1, x3,LREG)

inst_11:// rs1==x10, rd==x8,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x10; dest:x8; op1val:0x43dffffffffffffe; valaddr_reg:x5;
val_offset:11*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x8, x10, dyn, 32, 0, x5, 11*FLEN/8, x7, x1, x3,LREG)

inst_12:// rs1==x4, rd==x6,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x4; dest:x6; op1val:0x43dffffffffffffe; valaddr_reg:x5;
val_offset:12*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x6, x4, dyn, 64, 0, x5, 12*FLEN/8, x7, x1, x3,LREG)

inst_13:// rs1==x6, rd==x4,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x6; dest:x4; op1val:0x43dffffffffffffe; valaddr_reg:x5;
val_offset:13*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x4, x6, dyn, 96, 0, x5, 13*FLEN/8, x7, x1, x3,LREG)

inst_14:// rs1==x2,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x2; dest:x31; op1val:0x43dffffffffffffe; valaddr_reg:x5;
val_offset:14*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x2, dyn, 128, 0, x5, 14*FLEN/8, x7, x1, x3,LREG)

inst_15:// rd==x2,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x31; dest:x2; op1val:0x43dfffffffffffff; valaddr_reg:x5;
val_offset:15*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x2, x31, dyn, 0, 0, x5, 15*FLEN/8, x7, x1, x3,LREG)

inst_16:// fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43dfffffffffffff; valaddr_reg:x5;
val_offset:16*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 32, 0, x5, 16*FLEN/8, x7, x1, x3,LREG)

inst_17:// fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43dfffffffffffff; valaddr_reg:x5;
val_offset:17*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 64, 0, x5, 17*FLEN/8, x7, x1, x3,LREG)

inst_18:// fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43dfffffffffffff; valaddr_reg:x5;
val_offset:18*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 96, 0, x5, 18*FLEN/8, x7, x1, x3,LREG)

inst_19:// fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43dfffffffffffff; valaddr_reg:x5;
val_offset:19*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 128, 0, x5, 19*FLEN/8, x7, x1, x3,LREG)

inst_20:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x5;
val_offset:20*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 0, 0, x5, 20*FLEN/8, x7, x1, x3,LREG)

inst_21:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x5;
val_offset:21*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 32, 0, x5, 21*FLEN/8, x7, x1, x3,LREG)

inst_22:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x5;
val_offset:22*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 64, 0, x5, 22*FLEN/8, x7, x1, x3,LREG)

inst_23:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x5;
val_offset:23*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 96, 0, x5, 23*FLEN/8, x7, x1, x3,LREG)

inst_24:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x5;
val_offset:24*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 128, 0, x5, 24*FLEN/8, x7, x1, x3,LREG)

inst_25:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000001; valaddr_reg:x5;
val_offset:25*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 0, 0, x5, 25*FLEN/8, x7, x1, x3,LREG)

inst_26:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000001; valaddr_reg:x5;
val_offset:26*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 32, 0, x5, 26*FLEN/8, x7, x1, x3,LREG)

inst_27:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000001; valaddr_reg:x5;
val_offset:27*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 64, 0, x5, 27*FLEN/8, x7, x1, x3,LREG)

inst_28:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000001; valaddr_reg:x5;
val_offset:28*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 96, 0, x5, 28*FLEN/8, x7, x1, x3,LREG)

inst_29:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000001; valaddr_reg:x5;
val_offset:29*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 128, 0, x5, 29*FLEN/8, x7, x1, x3,LREG)

inst_30:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x5;
val_offset:30*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 0, 0, x5, 30*FLEN/8, x7, x1, x3,LREG)

inst_31:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x5;
val_offset:31*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 32, 0, x5, 31*FLEN/8, x7, x1, x3,LREG)

inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x5;
val_offset:32*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 64, 0, x5, 32*FLEN/8, x7, x1, x3,LREG)

inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x5;
val_offset:33*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 96, 0, x5, 33*FLEN/8, x7, x1, x3,LREG)

inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x5;
val_offset:34*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 128, 0, x5, 34*FLEN/8, x7, x1, x3,LREG)

inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x5;
val_offset:35*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 0, 0, x5, 35*FLEN/8, x7, x1, x3,LREG)

inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x5;
val_offset:36*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 32, 0, x5, 36*FLEN/8, x7, x1, x3,LREG)

inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x5;
val_offset:37*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 64, 0, x5, 37*FLEN/8, x7, x1, x3,LREG)

inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x5;
val_offset:38*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 96, 0, x5, 38*FLEN/8, x7, x1, x3,LREG)

inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x5;
val_offset:39*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 128, 0, x5, 39*FLEN/8, x7, x1, x3,LREG)

inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x5;
val_offset:40*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 0, 0, x5, 40*FLEN/8, x7, x1, x3,LREG)

inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x20 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x5;
val_offset:41*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 32, 0, x5, 41*FLEN/8, x7, x1, x3,LREG)

inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x40 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x5;
val_offset:42*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 64, 0, x5, 42*FLEN/8, x7, x1, x3,LREG)

inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x60 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x5;
val_offset:43*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 96, 0, x5, 43*FLEN/8, x7, x1, x3,LREG)

inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x80 and rm_val == 7   
/* opcode: fcvt.l.d ; op1:x30; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x5;
val_offset:44*FLEN/8; rmval:dyn; correctval:0; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.l.d, x31, x30, dyn, 128, 0, x5, 44*FLEN/8, x7, x1, x3,LREG)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 90*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
