
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:03:19 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fcvt.s.wu.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.wu instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fcvt.s.wu_b26 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fcvt.s.wu_b26)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1==x16, rd==f9,rs1_val == 0 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x16; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f9, x16, dyn, 0, 0, x3, 0*4, x10, x1, x4,LREGWU)

inst_1:// rs1==x7, rd==f10,rs1_val == 1 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x7; dest:f10; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f10, x7, dyn, 0, 0, x3, 1*4, x10, x1, x4,LREGWU)

inst_2:// rs1==x5, rd==f21,rs1_val == 1027494066 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x5; dest:f21; op1val:0x3d3e50b2; valaddr_reg:x3;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f21, x5, dyn, 0, 0, x3, 2*4, x10, x1, x4,LREGWU)

inst_3:// rs1==x18, rd==f23,rs1_val == 107790943 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x18; dest:f23; op1val:0x66cc25f; valaddr_reg:x3;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f23, x18, dyn, 0, 0, x3, 3*4, x10, x1, x4,LREGWU)

inst_4:// rs1==x28, rd==f18,rs1_val == 1094 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x28; dest:f18; op1val:0x446; valaddr_reg:x3;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f18, x28, dyn, 0, 0, x3, 4*4, x10, x1, x4,LREGWU)

inst_5:// rs1==x8, rd==f16,rs1_val == 123 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x8; dest:f16; op1val:0x7b; valaddr_reg:x3;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f16, x8, dyn, 0, 0, x3, 5*4, x10, x1, x4,LREGWU)

inst_6:// rs1==x30, rd==f29,rs1_val == 12789625 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x30; dest:f29; op1val:0xc32779; valaddr_reg:x3;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f29, x30, dyn, 0, 0, x3, 6*4, x10, x1, x4,LREGWU)

inst_7:// rs1==x27, rd==f26,rs1_val == 15 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x27; dest:f26; op1val:0xf; valaddr_reg:x3;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f26, x27, dyn, 0, 0, x3, 7*4, x10, x1, x4,LREGWU)

inst_8:// rs1==x9, rd==f14,rs1_val == 1587807073 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x9; dest:f14; op1val:0x5ea40361; valaddr_reg:x3;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f14, x9, dyn, 0, 0, x3, 8*4, x10, x1, x4,LREGWU)

inst_9:// rs1==x20, rd==f11,rs1_val == 16 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x20; dest:f11; op1val:0x10; valaddr_reg:x3;
val_offset:9*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f11, x20, dyn, 0, 0, x3, 9*4, x10, x1, x4,LREGWU)

inst_10:// rs1==x17, rd==f6,rs1_val == 1848861 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x17; dest:f6; op1val:0x1c361d; valaddr_reg:x3;
val_offset:10*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f6, x17, dyn, 0, 0, x3, 10*4, x10, x1, x4,LREGWU)

inst_11:// rs1==x29, rd==f3,rs1_val == 2 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x29; dest:f3; op1val:0x2; valaddr_reg:x3;
val_offset:11*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f3, x29, dyn, 0, 0, x3, 11*4, x10, x1, x4,LREGWU)

inst_12:// rs1==x26, rd==f19,rs1_val == 231549045 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x26; dest:f19; op1val:0xdcd2875; valaddr_reg:x3;
val_offset:12*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f19, x26, dyn, 0, 0, x3, 12*4, x10, x1, x4,LREGWU)

inst_13:// rs1==x6, rd==f17,rs1_val == 241276 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x6; dest:f17; op1val:0x3ae7c; valaddr_reg:x3;
val_offset:13*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f17, x6, dyn, 0, 0, x3, 13*4, x10, x1, x4,LREGWU)

inst_14:// rs1==x25, rd==f24,rs1_val == 24575 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x25; dest:f24; op1val:0x5fff; valaddr_reg:x3;
val_offset:14*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f24, x25, dyn, 0, 0, x3, 14*4, x10, x1, x4,LREGWU)

inst_15:// rs1==x21, rd==f4,rs1_val == 253 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x21; dest:f4; op1val:0xfd; valaddr_reg:x3;
val_offset:15*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f4, x21, dyn, 0, 0, x3, 15*4, x10, x1, x4,LREGWU)

inst_16:// rs1==x24, rd==f8,rs1_val == 32105925 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x24; dest:f8; op1val:0x1e9e5c5; valaddr_reg:x3;
val_offset:16*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f8, x24, dyn, 0, 0, x3, 16*4, x10, x1, x4,LREGWU)

inst_17:// rs1==x13, rd==f1,rs1_val == 334857 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x13; dest:f1; op1val:0x51c09; valaddr_reg:x3;
val_offset:17*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f1, x13, dyn, 0, 0, x3, 17*4, x10, x1, x4,LREGWU)

inst_18:// rs1==x0, rd==f5,rs1_val == 339827553 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x0; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:18*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f5, x0, dyn, 0, 0, x3, 18*4, x10, x1, x4,LREGWU)

inst_19:// rs1==x12, rd==f12,rs1_val == 3864061 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x12; dest:f12; op1val:0x3af5fd; valaddr_reg:x3;
val_offset:19*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f12, x12, dyn, 0, 0, x3, 19*4, x10, x1, x4,LREGWU)

inst_20:// rs1==x22, rd==f31,rs1_val == 398 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x22; dest:f31; op1val:0x18e; valaddr_reg:x3;
val_offset:20*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f31, x22, dyn, 0, 0, x3, 20*4, x10, x1, x4,LREGWU)

inst_21:// rs1==x2, rd==f25,rs1_val == 4055 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x2; dest:f25; op1val:0xfd7; valaddr_reg:x3;
val_offset:21*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f25, x2, dyn, 0, 0, x3, 21*4, x10, x1, x4,LREGWU)

inst_22:// rs1==x19, rd==f28,rs1_val == 45 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x19; dest:f28; op1val:0x2d; valaddr_reg:x3;
val_offset:22*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f28, x19, dyn, 0, 0, x3, 22*4, x10, x1, x4,LREGWU)

inst_23:// rs1==x31, rd==f27,rs1_val == 45276376 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x31; dest:f27; op1val:0x2b2dcd8; valaddr_reg:x3;
val_offset:23*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f27, x31, dyn, 0, 0, x3, 23*4, x10, x1, x4,LREGWU)

inst_24:// rs1==x14, rd==f2,rs1_val == 56436 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x14; dest:f2; op1val:0xdc74; valaddr_reg:x3;
val_offset:24*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f2, x14, dyn, 0, 0, x3, 24*4, x10, x1, x4,LREGWU)
RVTEST_VALBASEUPD(x5,test_dataset_1)

inst_25:// rs1==x15, rd==f15,rs1_val == 6573466 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x15; dest:f15; op1val:0x644d9a; valaddr_reg:x5;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f15, x15, dyn, 0, 0, x5, 0*4, x6, x1, x4,LREGWU)

inst_26:// rs1==x3, rd==f20,rs1_val == 676 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x3; dest:f20; op1val:0x2a4; valaddr_reg:x5;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x4;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f20, x3, dyn, 0, 0, x5, 1*4, x6, x1, x4,LREGWU)

inst_27:// rs1==x23, rd==f13,rs1_val == 6781 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x23; dest:f13; op1val:0x1a7d; valaddr_reg:x5;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f13, x23, dyn, 0, 0, x5, 2*4, x6, x1, x3,LREGWU)
RVTEST_SIGBASE(x2,signature_x2_0)

inst_28:// rs1==x1, rd==f7,rs1_val == 7 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x1; dest:f7; op1val:0x7; valaddr_reg:x5;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f7, x1, dyn, 0, 0, x5, 3*4, x6, x2, x3,LREGWU)

inst_29:// rs1==x11, rd==f22,rs1_val == 71376 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x11; dest:f22; op1val:0x116d0; valaddr_reg:x5;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f22, x11, dyn, 0, 0, x5, 4*4, x6, x2, x3,LREGWU)

inst_30:// rs1==x4, rd==f0,rs1_val == 896618 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x4; dest:f0; op1val:0xdae6a; valaddr_reg:x5;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f0, x4, dyn, 0, 0, x5, 5*4, x6, x2, x3,LREGWU)

inst_31:// rs1==x10, rd==f30,rs1_val == 9438 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x10; dest:f30; op1val:0x24de; valaddr_reg:x5;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f30, x10, dyn, 0, 0, x5, 6*4, x6, x2, x3,LREGWU)

inst_32:// rs1_val == 339827553 and  fcsr == 0 and rm_val == 7  
/* opcode: fcvt.s.wu ; op1:x31; dest:f31; op1val:0x14415b61; valaddr_reg:x5;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.s.wu, f31, x31, dyn, 0, 0, x5, 7*4, x6, x2, x3,LREGWU)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 1027494066;
.word 107790943;
.word 1094;
.word 123;
.word 12789625;
.word 15;
.word 1587807073;
.word 16;
.word 1848861;
.word 2;
.word 231549045;
.word 241276;
.word 24575;
.word 253;
.word 32105925;
.word 334857;
.word 0;
.word 3864061;
.word 398;
.word 4055;
.word 45;
.word 45276376;
.word 56436;
test_dataset_1:
.word 6573466;
.word 676;
.word 6781;
.word 7;
.word 71376;
.word 896618;
.word 9438;
.word 339827553;
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 56*((SIGALIGN)/4),4,0xdeadbeef


signature_x2_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
