
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x11,test_dataset_0)
RVTEST_SIGBASE(x8,signature_x8_1)

inst_0:// rs1==f7, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f7; dest:x29; op1val:0x0; valaddr_reg:x11;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x29, f7, dyn, 0, 0, x11, 0*FLEN/8, x17, x8, x9,FLREG)

inst_1:// rs1==f15, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f15; dest:x28; op1val:0x1; valaddr_reg:x11;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x28, f15, dyn, 0, 0, x11, 1*FLEN/8, x17, x8, x9,FLREG)

inst_2:// rs1==f31, rd==x1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f31; dest:x1; op1val:0x2; valaddr_reg:x11;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f31, dyn, 0, 0, x11, 2*FLEN/8, x17, x8, x9,FLREG)

inst_3:// rs1==f1, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f1; dest:x14; op1val:0xfffffffffffff; valaddr_reg:x11;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x14, f1, dyn, 0, 0, x11, 3*FLEN/8, x17, x8, x9,FLREG)

inst_4:// rs1==f2, rd==x22,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f2; dest:x22; op1val:0x10000000000000; valaddr_reg:x11;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x22, f2, dyn, 0, 0, x11, 4*FLEN/8, x17, x8, x9,FLREG)

inst_5:// rs1==f0, rd==x4,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f0; dest:x4; op1val:0x10000000000002; valaddr_reg:x11;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x4, f0, dyn, 0, 0, x11, 5*FLEN/8, x17, x8, x9,FLREG)

inst_6:// rs1==f4, rd==x0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f4; dest:x0; op1val:0x3ff0000000000000; valaddr_reg:x11;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x0, f4, dyn, 0, 0, x11, 6*FLEN/8, x17, x8, x9,FLREG)

inst_7:// rs1==f17, rd==x10,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f17; dest:x10; op1val:0x7fefffffffffffff; valaddr_reg:x11;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x10, f17, dyn, 0, 0, x11, 7*FLEN/8, x17, x8, x9,FLREG)

inst_8:// rs1==f16, rd==x24,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f16; dest:x24; op1val:0x7ff0000000000000; valaddr_reg:x11;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x24, f16, dyn, 0, 0, x11, 8*FLEN/8, x17, x8, x9,FLREG)

inst_9:// rs1==f12, rd==x20,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f12; dest:x20; op1val:0x7ff0000000000001; valaddr_reg:x11;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f12, dyn, 0, 0, x11, 9*FLEN/8, x17, x8, x9,FLREG)

inst_10:// rs1==f6, rd==x26,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f6; dest:x26; op1val:0x7ff8000000000000; valaddr_reg:x11;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x26, f6, dyn, 0, 0, x11, 10*FLEN/8, x17, x8, x9,FLREG)

inst_11:// rs1==f28, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f28; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x11;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x13, f28, dyn, 0, 0, x11, 11*FLEN/8, x17, x8, x9,FLREG)

inst_12:// rs1==f21, rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f21; dest:x2; op1val:0x8000000000000000; valaddr_reg:x11;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x2, f21, dyn, 0, 0, x11, 12*FLEN/8, x17, x8, x9,FLREG)

inst_13:// rs1==f3, rd==x15,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f3; dest:x15; op1val:0x8000000000000001; valaddr_reg:x11;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f3, dyn, 0, 0, x11, 13*FLEN/8, x17, x8, x9,FLREG)

inst_14:// rs1==f22, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f22; dest:x16; op1val:0x8000000000000002; valaddr_reg:x11;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x16, f22, dyn, 0, 0, x11, 14*FLEN/8, x17, x8, x9,FLREG)

inst_15:// rs1==f9, rd==x18,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f9; dest:x18; op1val:0x800fffffffffffff; valaddr_reg:x11;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x18, f9, dyn, 0, 0, x11, 15*FLEN/8, x17, x8, x9,FLREG)

inst_16:// rs1==f20, rd==x6,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f20; dest:x6; op1val:0x8010000000000000; valaddr_reg:x11;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x6, f20, dyn, 0, 0, x11, 16*FLEN/8, x17, x8, x9,FLREG)

inst_17:// rs1==f27, rd==x31,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f27; dest:x31; op1val:0x8010000000000002; valaddr_reg:x11;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f27, dyn, 0, 0, x11, 17*FLEN/8, x17, x8, x9,FLREG)

inst_18:// rs1==f11, rd==x3,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f11; dest:x3; op1val:0xbf80000000000000; valaddr_reg:x11;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x3, f11, dyn, 0, 0, x11, 18*FLEN/8, x17, x8, x9,FLREG)

inst_19:// rs1==f19, rd==x12,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f19; dest:x12; op1val:0xffefffffffffffff; valaddr_reg:x11;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x12, f19, dyn, 0, 0, x11, 19*FLEN/8, x17, x8, x9,FLREG)

inst_20:// rs1==f8, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f8; dest:x30; op1val:0xfff0000000000000; valaddr_reg:x11;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x30, f8, dyn, 0, 0, x11, 20*FLEN/8, x17, x8, x9,FLREG)

inst_21:// rs1==f23, rd==x19,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f23; dest:x19; op1val:0xfff0000000000001; valaddr_reg:x11;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x19, f23, dyn, 0, 0, x11, 21*FLEN/8, x17, x8, x9,FLREG)

inst_22:// rs1==f5, rd==x7,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f5; dest:x7; op1val:0xfff8000000000000; valaddr_reg:x11;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x7, f5, dyn, 0, 0, x11, 22*FLEN/8, x17, x8, x9,FLREG)

inst_23:// rs1==f24, rd==x25,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f24; dest:x25; op1val:0xfff8000000000001; valaddr_reg:x11;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x25, f24, dyn, 0, 0, x11, 23*FLEN/8, x17, x8, x9,FLREG)

inst_24:// rs1==f13, rd==x5,
/* opcode: fcvt.w.d ; op1:f13; dest:x5; op1val:0x0; valaddr_reg:x11;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x5, f13, dyn, 0, 0, x11, 24*FLEN/8, x17, x8, x9,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)

inst_25:// rs1==f10, rd==x17,
/* opcode: fcvt.w.d ; op1:f10; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x17, f10, dyn, 0, 0, x3, 0*FLEN/8, x4, x8, x9,FLREG)

inst_26:// rs1==f29, rd==x23,
/* opcode: fcvt.w.d ; op1:f29; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x23, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x8, x9,FLREG)

inst_27:// rs1==f18, rd==x9,
/* opcode: fcvt.w.d ; op1:f18; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f18, dyn, 0, 0, x3, 2*FLEN/8, x4, x8, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:// rs1==f30, rd==x8,
/* opcode: fcvt.w.d ; op1:f30; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x8, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)

inst_29:// rs1==f14, rd==x27,
/* opcode: fcvt.w.d ; op1:f14; dest:x27; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x27, f14, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)

inst_30:// rs1==f26, rd==x21,
/* opcode: fcvt.w.d ; op1:f26; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x21, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)

inst_31:// rs1==f25, rd==x11,
/* opcode: fcvt.w.d ; op1:f25; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x11, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)

inst_32:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.dword 0x0
.dword 0x1
.dword 0x2
.dword 0xfffffffffffff
.dword 0x10000000000000
.dword 0x10000000000002
.dword 0x3ff0000000000000
.dword 0x7fefffffffffffff
.dword 0x7ff0000000000000
.dword 0x7ff0000000000001
.dword 0x7ff8000000000000
.dword 0x7ff8000000000001
.dword 0x8000000000000000
.dword 0x8000000000000001
.dword 0x8000000000000002
.dword 0x800fffffffffffff
.dword 0x8010000000000000
.dword 0x8010000000000002
.dword 0xbf80000000000000
.dword 0xffefffffffffffff
.dword 0xfff0000000000000
.dword 0xfff0000000000001
.dword 0xfff8000000000000
.dword 0xfff8000000000001
.dword 0x0
test_dataset_1:
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0x3ff0000000000000
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x8_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x8_1:
    .fill 56*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
