
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 06:03:37 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x6,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x31, rs2==x2, rs3==x31, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x052 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x31; op2:x2; op3:x31; dest:x28; op1val:0x4a; op2val:0x3052;
op3val:0x4a; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x28, x31, x2, x31, dyn, 0, 0, x6, 0*FLEN/8, x9, x1, x5)

inst_1:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x29, rs2==x25, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x29; op2:x25; op3:x25; dest:x26; op1val:0x3f; op2val:0x3e18;
op3val:0x3e18; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x26, x29, x25, x25, dyn, 0, 0, x6, 3*FLEN/8, x9, x1, x5)

inst_2:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x21, rs2==x3, rs3==x30, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x022 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x21; op2:x3; op3:x30; dest:x11; op1val:0x22; op2val:0x2787;
op3val:0x5; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x11, x21, x3, x30, dyn, 0, 0, x6, 6*FLEN/8, x9, x1, x5)

inst_3:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x4, rs2==x30, rs3==x29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x013 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x4; op2:x30; op3:x29; dest:x30; op1val:0x1; op2val:0x4976;
op3val:0x13; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x30, x4, x30, x29, dyn, 0, 0, x6, 9*FLEN/8, x9, x1, x5)

inst_4:
// rs1 == rd == rs3 != rs2, rs1==x22, rs2==x15, rs3==x22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x22; op2:x15; op3:x22; dest:x22; op1val:0x55; op2val:0x39a5;
op3val:0x55; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x22, x22, x15, x22, dyn, 0, 0, x6, 12*FLEN/8, x9, x1, x5)

inst_5:
// rs1 == rs2 == rs3 != rd, rs1==x26, rs2==x26, rs3==x26, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x26; op2:x26; op3:x26; dest:x29; op1val:0x3d; op2val:0x3d;
op3val:0x3d; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x29, x26, x26, x26, dyn, 0, 0, x6, 15*FLEN/8, x9, x1, x5)

inst_6:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x11, rs2==x11, rs3==x27, rd==x2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x163 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x11; op2:x11; op3:x27; dest:x2; op1val:0x5f; op2val:0x5f;
op3val:0x30; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x2, x11, x11, x27, dyn, 0, 0, x6, 18*FLEN/8, x9, x1, x5)

inst_7:
// rd == rs2 == rs3 != rs1, rs1==x17, rs2==x10, rs3==x10, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x17; op2:x10; op3:x10; dest:x10; op1val:0x29; op2val:0xb9a8;
op3val:0xb9a8; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x10, x17, x10, x10, dyn, 0, 0, x6, 21*FLEN/8, x9, x1, x5)

inst_8:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x18, rs2==x19, rs3==x13, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x09a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x18; op2:x19; op3:x13; dest:x18; op1val:0x3; op2val:0xd49a;
op3val:0x23; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x18, x18, x19, x13, dyn, 0, 0, x6, 24*FLEN/8, x9, x1, x5)

inst_9:
// rs1 == rs2 == rs3 == rd, rs1==x8, rs2==x8, rs3==x8, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x8; op2:x8; op3:x8; dest:x8; op1val:0x3f; op2val:0x3f;
op3val:0x3f; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x8, x8, x8, x8, dyn, 0, 0, x6, 27*FLEN/8, x9, x1, x5)

inst_10:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x3, rs2==x18, rs3==x24, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x098 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x3; op2:x18; op3:x24; dest:x24; op1val:0x5e; op2val:0x3898;
op3val:0x35; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x24, x3, x18, x24, dyn, 0, 0, x6, 30*FLEN/8, x9, x1, x5)

inst_11:
// rs1 == rs2 == rd != rs3, rs1==x7, rs2==x7, rs3==x16, rd==x7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x7; op2:x7; op3:x16; dest:x7; op1val:0x45; op2val:0x45;
op3val:0x46; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x7, x7, x7, x16, dyn, 0, 0, x6, 33*FLEN/8, x9, x1, x5)

inst_12:
// rs1==x24, rs2==x22, rs3==x1, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x22e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x24; op2:x22; op3:x1; dest:x19; op1val:0x58; op2val:0x322e;
op3val:0xd; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x19, x24, x22, x1, dyn, 0, 0, x6, 36*FLEN/8, x9, x1, x5)

inst_13:
// rs1==x27, rs2==x31, rs3==x15, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x27a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x049 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x27; op2:x31; op3:x15; dest:x23; op1val:0x19; op2val:0x427a;
op3val:0x49; valaddr_reg:x6; val_offset:39*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x23, x27, x31, x15, dyn, 0, 0, x6, 39*FLEN/8, x9, x1, x5)
RVTEST_VALBASEUPD(x8,test_dataset_1)

inst_14:
// rs1==x25, rs2==x13, rs3==x2, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x047 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x25; op2:x13; op3:x2; dest:x21; op1val:0x47; op2val:0x3df8;
op3val:0x5a; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x21, x25, x13, x2, dyn, 0, 0, x8, 0*FLEN/8, x11, x1, x5)

inst_15:
// rs1==x30, rs2==x21, rs3==x11, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x19d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x022 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x21; op3:x11; dest:x31; op1val:0x5e; op2val:0x399d;
op3val:0x22; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x21, x11, dyn, 0, 0, x8, 3*FLEN/8, x11, x1, x5)

inst_16:
// rs1==x2, rs2==x4, rs3==x0, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x2; op2:x4; op3:x0; dest:x16; op1val:0x55; op2val:0x3eba;
op3val:0x0; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x16, x2, x4, x0, dyn, 0, 0, x8, 6*FLEN/8, x11, x1, x5)

inst_17:
// rs1==x12, rs2==x9, rs3==x21, rd==x0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x12; op2:x9; op3:x21; dest:x0; op1val:0x58; op2val:0x3e5d;
op3val:0xc; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x0, x12, x9, x21, dyn, 0, 0, x8, 9*FLEN/8, x11, x1, x7)
RVTEST_SIGBASE(x2,signature_x2_0)

inst_18:
// rs1==x6, rs2==x12, rs3==x5, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x6; op2:x12; op3:x5; dest:x27; op1val:0x37; op2val:0x456f;
op3val:0x2b; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x27, x6, x12, x5, dyn, 0, 0, x8, 12*FLEN/8, x11, x2, x7)

inst_19:
// rs1==x15, rs2==x28, rs3==x6, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x14 and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x15; op2:x28; op3:x6; dest:x20; op1val:0xc; op2val:0x51d2;
op3val:0x2f; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x20, x15, x28, x6, dyn, 0, 0, x8, 15*FLEN/8, x11, x2, x7)

inst_20:
// rs1==x16, rs2==x24, rs3==x12, rd==x15,fs1 == 0 and fe1 == 0x0f and fm1 == 0x035 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x021 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x16; op2:x24; op3:x12; dest:x15; op1val:0x3c35; op2val:0x279b;
op3val:0x3c21; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x15, x16, x24, x12, dyn, 0, 0, x8, 18*FLEN/8, x11, x2, x7)

inst_21:
// rs1==x20, rs2==x29, rs3==x4, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x039 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x135 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x20; op2:x29; op3:x4; dest:x9; op1val:0x3c39; op2val:0x2d35;
op3val:0x3c5a; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x9, x20, x29, x4, dyn, 0, 0, x8, 21*FLEN/8, x11, x2, x7)

inst_22:
// rs1==x23, rs2==x16, rs3==x14, rd==x25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x0f and fm3 == 0x061 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x23; op2:x16; op3:x14; dest:x25; op1val:0x3c0d; op2val:0x2dbd;
op3val:0x3c61; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x25, x23, x16, x14, dyn, 0, 0, x8, 24*FLEN/8, x11, x2, x7)

inst_23:
// rs1==x9, rs2==x23, rs3==x18, rd==x3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01a and fs2 == 0 and fe2 == 0x0b and fm2 == 0x0ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x9; op2:x23; op3:x18; dest:x3; op1val:0x3c1a; op2val:0x2cff;
op3val:0x3c5a; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x3, x9, x23, x18, dyn, 0, 0, x8, 27*FLEN/8, x11, x2, x7)

inst_24:
// rs1==x5, rs2==x27, rs3==x7, rd==x12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x052 and fs2 == 0 and fe2 == 0x09 and fm2 == 0x117 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x026 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x5; op2:x27; op3:x7; dest:x12; op1val:0x3c52; op2val:0x2517;
op3val:0x3c26; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x12, x5, x27, x7, dyn, 0, 0, x8, 30*FLEN/8, x11, x2, x7)

inst_25:
// rs1==x10, rs2==x6, rs3==x9, rd==x13,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00d and fs2 == 1 and fe2 == 0x09 and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x006 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x10; op2:x6; op3:x9; dest:x13; op1val:0x3c0d; op2val:0xa66b;
op3val:0x3c06; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x13, x10, x6, x9, dyn, 0, 0, x8, 33*FLEN/8, x11, x2, x7)

inst_26:
// rs1==x14, rs2==x17, rs3==x28, rd==x4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x14; op2:x17; op3:x28; dest:x4; op1val:0x3c4c; op2val:0xa86b;
op3val:0x3c1a; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x4, x14, x17, x28, dyn, 0, 0, x8, 36*FLEN/8, x11, x2, x7)
RVTEST_VALBASEUPD(x3,test_dataset_2)

inst_27:
// rs1==x19, rs2==x14, rs3==x3, rd==x17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x19; op2:x14; op3:x3; dest:x17; op1val:0x3c54; op2val:0xacad;
op3val:0x3c2f; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x17, x19, x14, x3, dyn, 0, 0, x3, 0*FLEN/8, x4, x2, x7)

inst_28:
// rs1==x28, rs2==x20, rs3==x23, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2cc and fs3 == 0 and fe3 == 0x0f and fm3 == 0x019 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x28; op2:x20; op3:x23; dest:x14; op1val:0x3c3f; op2val:0xb2cc;
op3val:0x3c19; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x14, x28, x20, x23, dyn, 0, 0, x3, 3*FLEN/8, x4, x2, x7)

inst_29:
// rs1==x0, rs2==x1, rs3==x17, rd==x5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x0; op2:x1; op3:x17; dest:x5; op1val:0x0; op2val:0xb66d;
op3val:0x3c4a; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x5, x0, x1, x17, dyn, 0, 0, x3, 6*FLEN/8, x4, x2, x7)

inst_30:
// rs1==x1, rs2==x0, rs3==x19, rd==x6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x1; op2:x0; op3:x19; dest:x6; op1val:0x3c53; op2val:0x0;
op3val:0x3c5a; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x6, x1, x0, x19, dyn, 0, 0, x3, 9*FLEN/8, x4, x2, x7)

inst_31:
// rs1==x13, rs2==x5, rs3==x20, rd==x1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38b and fs3 == 0 and fe3 == 0x0f and fm3 == 0x004 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x13; op2:x5; op3:x20; dest:x1; op1val:0x3c41; op2val:0x3f8b;
op3val:0x3c04; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x1, x13, x5, x20, dyn, 0, 0, x3, 12*FLEN/8, x4, x2, x7)

inst_32:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x052 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c52; op2val:0x3f97;
op3val:0x3c2f; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 15*FLEN/8, x4, x2, x7)

inst_33:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x020 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x00a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c20; op2val:0x400a;
op3val:0x3c4e; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 18*FLEN/8, x4, x2, x7)

inst_34:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x038 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x027 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c38; op2val:0x3fc9;
op3val:0x3c27; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 21*FLEN/8, x4, x2, x7)

inst_35:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x02e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x007 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c2e; op2val:0x4007;
op3val:0x3c4c; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 24*FLEN/8, x4, x2, x7)

inst_36:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x010 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c10; op2val:0x4015;
op3val:0x3c0c; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 27*FLEN/8, x4, x2, x7)

inst_37:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x041 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x027 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x057 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c41; op2val:0x4027;
op3val:0x3c57; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 30*FLEN/8, x4, x2, x7)

inst_38:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c44; op2val:0x4044;
op3val:0x3c1a; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 33*FLEN/8, x4, x2, x7)

inst_39:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x113 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c0f; op2val:0x4113;
op3val:0x3c4e; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 36*FLEN/8, x4, x2, x7)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x3666;
op3val:0x23; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 39*FLEN/8, x4, x2, x7)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x080 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x28; op2val:0x4080;
op3val:0x5d; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 42*FLEN/8, x4, x2, x7)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2c4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x031 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1a; op2val:0x3ec4;
op3val:0x31; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 45*FLEN/8, x4, x2, x7)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x129 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3e; op2val:0x3529;
op3val:0x1d; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 48*FLEN/8, x4, x2, x7)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x12; op2val:0x42aa;
op3val:0x4d; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 51*FLEN/8, x4, x2, x7)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x038 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1b; op2val:0x4038;
op3val:0x5a; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 54*FLEN/8, x4, x2, x7)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x385 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43; op2val:0xbb85;
op3val:0x2; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 57*FLEN/8, x4, x2, x7)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x047 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x016 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x19; op2val:0xc447;
op3val:0x16; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 60*FLEN/8, x4, x2, x7)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x340 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x053 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0xd340;
op3val:0x53; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 63*FLEN/8, x4, x2, x7)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x120 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x048 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b; op2val:0xc920;
op3val:0x48; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 66*FLEN/8, x4, x2, x7)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x389 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x050 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x56; op2val:0x3b89;
op3val:0x50; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 69*FLEN/8, x4, x2, x7)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x04c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x028 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50; op2val:0x384c;
op3val:0x28; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 72*FLEN/8, x4, x2, x7)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x080 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x031 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30; op2val:0x3c80;
op3val:0x31; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 75*FLEN/8, x4, x2, x7)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x032 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44; op2val:0x3af0;
op3val:0x32; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 78*FLEN/8, x4, x2, x7)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x026 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x328 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x26; op2val:0x3b28;
op3val:0x11; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 81*FLEN/8, x4, x2, x7)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x069 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x57; op2val:0x3c69;
op3val:0x3f; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 84*FLEN/8, x4, x2, x7)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x25b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x018 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7; op2val:0x4a5b;
op3val:0x18; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 87*FLEN/8, x4, x2, x7)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x37d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37; op2val:0x437d;
op3val:0x4d; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 90*FLEN/8, x4, x2, x7)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x060 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x033 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60; op2val:0x426a;
op3val:0x33; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 93*FLEN/8, x4, x2, x7)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d and fs2 == 0 and fe2 == 0x14 and fm2 == 0x17b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x039 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xd; op2val:0x517b;
op3val:0x39; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 96*FLEN/8, x4, x2, x7)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20; op2val:0xcfe4;
op3val:0xc; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 99*FLEN/8, x4, x2, x7)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04e and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x056 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e; op2val:0xc9fe;
op3val:0x56; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 102*FLEN/8, x4, x2, x7)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x024 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a; op2val:0xcc24;
op3val:0x3a; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 105*FLEN/8, x4, x2, x7)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x120 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31; op2val:0xcd20;
op3val:0xa; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 108*FLEN/8, x4, x2, x7)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x037 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43; op2val:0xcb1a;
op3val:0x37; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 111*FLEN/8, x4, x2, x7)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x027 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3d; op2val:0xcbcd;
op3val:0x27; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 114*FLEN/8, x4, x2, x7)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5b; op2val:0xc8fa;
op3val:0x35; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 117*FLEN/8, x4, x2, x7)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x019 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0xb; op2val:0xd4f1;
op3val:0x19; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 120*FLEN/8, x4, x2, x7)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x060 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x312 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x058 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60; op2val:0xc712;
op3val:0x58; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 123*FLEN/8, x4, x2, x7)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x23; op2val:0xca78;
op3val:0x3a; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 126*FLEN/8, x4, x2, x7)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0x4c6c;
op3val:0x5d; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 129*FLEN/8, x4, x2, x7)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x190 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x003 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x17; op2val:0x5190;
op3val:0x3; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 132*FLEN/8, x4, x2, x7)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x045 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3; op2val:0x5daa;
op3val:0x45; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 135*FLEN/8, x4, x2, x7)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x010 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x018 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x10; op2val:0x5418;
op3val:0x21; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 138*FLEN/8, x4, x2, x7)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c; op2val:0x4aef;
op3val:0x2f; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 141*FLEN/8, x4, x2, x7)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x11e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x19; op2val:0x511e;
op3val:0x21; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 144*FLEN/8, x4, x2, x7)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x41; op2val:0x4bd2;
op3val:0x3a; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 147*FLEN/8, x4, x2, x7)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b and fs2 == 0 and fe2 == 0x13 and fm2 == 0x197 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x043 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b; op2val:0x4d97;
op3val:0x43; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 150*FLEN/8, x4, x2, x7)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x236 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x035 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x21; op2val:0x4e36;
op3val:0x35; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 153*FLEN/8, x4, x2, x7)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x176 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36; op2val:0x4976;
op3val:0x4f; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 156*FLEN/8, x4, x2, x7)

inst_80:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0a and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43f; op2val:0x2800;
op3val:0x423; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 159*FLEN/8, x4, x2, x7)

inst_81:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04e and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2da and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x44e; op2val:0x2ada;
op3val:0x43d; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 162*FLEN/8, x4, x2, x7)

inst_82:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x455; op2val:0x2ab1;
op3val:0x43e; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 165*FLEN/8, x4, x2, x7)

inst_83:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x08 and fm2 == 0x12e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x013 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43f; op2val:0x212e;
op3val:0x413; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 168*FLEN/8, x4, x2, x7)

inst_84:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05d and fs2 == 0 and fe2 == 0x09 and fm2 == 0x390 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x031 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45d; op2val:0x2790;
op3val:0x431; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 171*FLEN/8, x4, x2, x7)

inst_85:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x040 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x387 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x028 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x440; op2val:0x1f87;
op3val:0x428; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 174*FLEN/8, x4, x2, x7)

inst_86:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x368 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x452; op2val:0x9b68;
op3val:0x43c; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 177*FLEN/8, x4, x2, x7)

inst_87:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x42a; op2val:0xacdc;
op3val:0x42f; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 180*FLEN/8, x4, x2, x7)

inst_88:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x015 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x455; op2val:0xb2c7;
op3val:0x415; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 183*FLEN/8, x4, x2, x7)

inst_89:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2b5 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x031 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x450; op2val:0xb6b5;
op3val:0x431; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 186*FLEN/8, x4, x2, x7)

inst_90:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x459; op2val:0x3fa4;
op3val:0x44e; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 189*FLEN/8, x4, x2, x7)

inst_91:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e5 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x029 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x423; op2val:0x3fe5;
op3val:0x429; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 192*FLEN/8, x4, x2, x7)

inst_92:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x399 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x033 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x453; op2val:0x3f99;
op3val:0x433; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 195*FLEN/8, x4, x2, x7)

inst_93:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e9 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x05e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x43f; op2val:0x3fe9;
op3val:0x45e; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 198*FLEN/8, x4, x2, x7)

inst_94:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x015 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x026 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x415; op2val:0x4005;
op3val:0x426; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 201*FLEN/8, x4, x2, x7)

inst_95:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x398 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x448; op2val:0x3f98;
op3val:0x401; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 204*FLEN/8, x4, x2, x7)

inst_96:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x050 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3dc and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x450; op2val:0x3fdc;
op3val:0x43a; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 207*FLEN/8, x4, x2, x7)

inst_97:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x043 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x018 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x408; op2val:0x4043;
op3val:0x418; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 210*FLEN/8, x4, x2, x7)

inst_98:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x004 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x04f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x404; op2val:0x40a2;
op3val:0x44f; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 213*FLEN/8, x4, x2, x7)

inst_99:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x449; op2val:0x40b1;
op3val:0x40f; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 216*FLEN/8, x4, x2, x7)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7858; op2val:0xbab0;
op3val:0x785c; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 219*FLEN/8, x4, x2, x7)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x030 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x344 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7830; op2val:0xbb44;
op3val:0x782f; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 222*FLEN/8, x4, x2, x7)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7840; op2val:0xbaef;
op3val:0x784c; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 225*FLEN/8, x4, x2, x7)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x019 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7808; op2val:0xbbac;
op3val:0x7819; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 228*FLEN/8, x4, x2, x7)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x372 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0xbb72;
op3val:0x7823; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 231*FLEN/8, x4, x2, x7)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x002 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbb2c;
op3val:0x7802; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 234*FLEN/8, x4, x2, x7)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x29b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0xba9b;
op3val:0x7844; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 237*FLEN/8, x4, x2, x7)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783f; op2val:0xba83;
op3val:0x780a; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 240*FLEN/8, x4, x2, x7)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783d; op2val:0xb96f;
op3val:0x781e; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 243*FLEN/8, x4, x2, x7)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780d; op2val:0xb724;
op3val:0x7830; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 246*FLEN/8, x4, x2, x7)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1c4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782f; op2val:0x41c4;
op3val:0x7813; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 249*FLEN/8, x4, x2, x7)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x058 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x051 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7858; op2val:0x41aa;
op3val:0x7851; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 252*FLEN/8, x4, x2, x7)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x020 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7820; op2val:0x41f4;
op3val:0x784e; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 255*FLEN/8, x4, x2, x7)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1c9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x013 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7829; op2val:0x41c9;
op3val:0x7813; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 258*FLEN/8, x4, x2, x7)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x051 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7805; op2val:0x4218;
op3val:0x7851; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 261*FLEN/8, x4, x2, x7)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x056 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7856; op2val:0x417f;
op3val:0x780d; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 264*FLEN/8, x4, x2, x7)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 0 and fe2 == 0x10 and fm2 == 0x169 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0x4169;
op3val:0x780e; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 267*FLEN/8, x4, x2, x7)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x006 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x053 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7806; op2val:0x41e0;
op3val:0x7853; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 270*FLEN/8, x4, x2, x7)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x783e; op2val:0x414b;
op3val:0x783c; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 273*FLEN/8, x4, x2, x7)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x099 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x009 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785d; op2val:0x4099;
op3val:0x7809; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 276*FLEN/8, x4, x2, x7)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x0c and fm2 == 0x052 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a; op2val:0x3052;
op3val:0xb; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 279*FLEN/8, x4, x2, x7)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0x3e18;
op3val:0x62; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 282*FLEN/8, x4, x2, x7)

inst_122:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x39a5;
op3val:0x4c; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 285*FLEN/8, x4, x2, x7)

inst_123:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x053 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x062 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3d; op2val:0x3c53;
op3val:0x62; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 288*FLEN/8, x4, x2, x7)

inst_124:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x163 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5f; op2val:0xb163;
op3val:0x30; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 291*FLEN/8, x4, x2, x7)

inst_125:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x29; op2val:0xb9a8;
op3val:0x63; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 294*FLEN/8, x4, x2, x7)

inst_126:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3f; op2val:0xc7b6;
op3val:0x1a; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 297*FLEN/8, x4, x2, x7)

inst_127:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x045 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x02c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x45; op2val:0x3c2c;
op3val:0x46; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 300*FLEN/8, x4, x2, x7)

inst_128:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x55; op2val:0x3eba;
op3val:0x4f; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 303*FLEN/8, x4, x2, x7)

inst_129:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x25d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x58; op2val:0x3e5d;
op3val:0xc; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 306*FLEN/8, x4, x2, x7)

inst_130:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c42; op2val:0xb66d;
op3val:0x3c4a; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 309*FLEN/8, x4, x2, x7)

inst_131:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x053 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0x0000  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3c53; op2val:0x3fba;
op3val:0x3c5a; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x7; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x3, 312*FLEN/8, x4, x2, x7)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(74,32,FLEN)
NAN_BOXED(12370,32,FLEN)
NAN_BOXED(74,32,FLEN)
NAN_BOXED(63,32,FLEN)
NAN_BOXED(15896,32,FLEN)
NAN_BOXED(15896,32,FLEN)
NAN_BOXED(34,32,FLEN)
NAN_BOXED(10119,32,FLEN)
NAN_BOXED(5,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(18806,32,FLEN)
NAN_BOXED(19,32,FLEN)
NAN_BOXED(85,32,FLEN)
NAN_BOXED(14757,32,FLEN)
NAN_BOXED(85,32,FLEN)
NAN_BOXED(61,32,FLEN)
NAN_BOXED(61,32,FLEN)
NAN_BOXED(61,32,FLEN)
NAN_BOXED(95,32,FLEN)
NAN_BOXED(95,16,FLEN)
NAN_BOXED(48,32,FLEN)
NAN_BOXED(41,32,FLEN)
NAN_BOXED(47528,16,FLEN)
NAN_BOXED(47528,32,FLEN)
NAN_BOXED(3,32,FLEN)
NAN_BOXED(54426,16,FLEN)
NAN_BOXED(35,32,FLEN)
NAN_BOXED(63,32,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(63,32,FLEN)
NAN_BOXED(94,32,FLEN)
NAN_BOXED(14488,32,FLEN)
NAN_BOXED(53,32,FLEN)
NAN_BOXED(69,32,FLEN)
NAN_BOXED(69,32,FLEN)
NAN_BOXED(70,32,FLEN)
NAN_BOXED(88,32,FLEN)
NAN_BOXED(12846,32,FLEN)
NAN_BOXED(13,32,FLEN)
NAN_BOXED(25,32,FLEN)
NAN_BOXED(17018,32,FLEN)
NAN_BOXED(73,32,FLEN)
test_dataset_1:
NAN_BOXED(71,32,FLEN)
NAN_BOXED(15864,32,FLEN)
NAN_BOXED(90,32,FLEN)
NAN_BOXED(94,32,FLEN)
NAN_BOXED(14749,32,FLEN)
NAN_BOXED(34,32,FLEN)
NAN_BOXED(85,32,FLEN)
NAN_BOXED(16058,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(88,32,FLEN)
NAN_BOXED(15965,32,FLEN)
NAN_BOXED(12,32,FLEN)
NAN_BOXED(55,32,FLEN)
NAN_BOXED(17775,32,FLEN)
NAN_BOXED(43,32,FLEN)
NAN_BOXED(12,32,FLEN)
NAN_BOXED(20946,32,FLEN)
NAN_BOXED(47,32,FLEN)
NAN_BOXED(15413,32,FLEN)
NAN_BOXED(10139,32,FLEN)
NAN_BOXED(15393,32,FLEN)
NAN_BOXED(15417,32,FLEN)
NAN_BOXED(11573,32,FLEN)
NAN_BOXED(15450,32,FLEN)
NAN_BOXED(15373,32,FLEN)
NAN_BOXED(11709,32,FLEN)
NAN_BOXED(15457,32,FLEN)
NAN_BOXED(15386,32,FLEN)
NAN_BOXED(11519,32,FLEN)
NAN_BOXED(15450,32,FLEN)
NAN_BOXED(15442,32,FLEN)
NAN_BOXED(9495,32,FLEN)
NAN_BOXED(15398,32,FLEN)
NAN_BOXED(15373,32,FLEN)
NAN_BOXED(42603,16,FLEN)
NAN_BOXED(15366,32,FLEN)
NAN_BOXED(15436,32,FLEN)
NAN_BOXED(43115,16,FLEN)
NAN_BOXED(15386,32,FLEN)
test_dataset_2:
NAN_BOXED(15444,16,FLEN)
NAN_BOXED(44205,16,FLEN)
NAN_BOXED(15407,16,FLEN)
NAN_BOXED(15423,16,FLEN)
NAN_BOXED(45772,16,FLEN)
NAN_BOXED(15385,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(46701,16,FLEN)
NAN_BOXED(15434,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(15450,16,FLEN)
NAN_BOXED(15425,16,FLEN)
NAN_BOXED(16267,16,FLEN)
NAN_BOXED(15364,16,FLEN)
NAN_BOXED(15442,16,FLEN)
NAN_BOXED(16279,16,FLEN)
NAN_BOXED(15407,16,FLEN)
NAN_BOXED(15392,16,FLEN)
NAN_BOXED(16394,16,FLEN)
NAN_BOXED(15438,16,FLEN)
NAN_BOXED(15416,16,FLEN)
NAN_BOXED(16329,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(15406,16,FLEN)
NAN_BOXED(16391,16,FLEN)
NAN_BOXED(15436,16,FLEN)
NAN_BOXED(15376,16,FLEN)
NAN_BOXED(16405,16,FLEN)
NAN_BOXED(15372,16,FLEN)
NAN_BOXED(15425,16,FLEN)
NAN_BOXED(16423,16,FLEN)
NAN_BOXED(15447,16,FLEN)
NAN_BOXED(15428,16,FLEN)
NAN_BOXED(16452,16,FLEN)
NAN_BOXED(15386,16,FLEN)
NAN_BOXED(15375,16,FLEN)
NAN_BOXED(16659,16,FLEN)
NAN_BOXED(15438,16,FLEN)
NAN_BOXED(85,16,FLEN)
NAN_BOXED(13926,16,FLEN)
NAN_BOXED(35,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(16512,16,FLEN)
NAN_BOXED(93,16,FLEN)
NAN_BOXED(26,16,FLEN)
NAN_BOXED(16068,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(62,16,FLEN)
NAN_BOXED(13609,16,FLEN)
NAN_BOXED(29,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(17066,16,FLEN)
NAN_BOXED(77,16,FLEN)
NAN_BOXED(27,16,FLEN)
NAN_BOXED(16440,16,FLEN)
NAN_BOXED(90,16,FLEN)
NAN_BOXED(67,16,FLEN)
NAN_BOXED(48005,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(25,16,FLEN)
NAN_BOXED(50247,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(54080,16,FLEN)
NAN_BOXED(83,16,FLEN)
NAN_BOXED(43,16,FLEN)
NAN_BOXED(51488,16,FLEN)
NAN_BOXED(72,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(15241,16,FLEN)
NAN_BOXED(80,16,FLEN)
NAN_BOXED(80,16,FLEN)
NAN_BOXED(14412,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(15488,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(68,16,FLEN)
NAN_BOXED(15088,16,FLEN)
NAN_BOXED(50,16,FLEN)
NAN_BOXED(38,16,FLEN)
NAN_BOXED(15144,16,FLEN)
NAN_BOXED(17,16,FLEN)
NAN_BOXED(87,16,FLEN)
NAN_BOXED(15465,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(19035,16,FLEN)
NAN_BOXED(24,16,FLEN)
NAN_BOXED(55,16,FLEN)
NAN_BOXED(17277,16,FLEN)
NAN_BOXED(77,16,FLEN)
NAN_BOXED(96,16,FLEN)
NAN_BOXED(17002,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(13,16,FLEN)
NAN_BOXED(20859,16,FLEN)
NAN_BOXED(57,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(53220,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(78,16,FLEN)
NAN_BOXED(51710,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(52260,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(52512,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(67,16,FLEN)
NAN_BOXED(51994,16,FLEN)
NAN_BOXED(55,16,FLEN)
NAN_BOXED(61,16,FLEN)
NAN_BOXED(52173,16,FLEN)
NAN_BOXED(39,16,FLEN)
NAN_BOXED(91,16,FLEN)
NAN_BOXED(51450,16,FLEN)
NAN_BOXED(53,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(54513,16,FLEN)
NAN_BOXED(25,16,FLEN)
NAN_BOXED(96,16,FLEN)
NAN_BOXED(50962,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(35,16,FLEN)
NAN_BOXED(51832,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(19564,16,FLEN)
NAN_BOXED(93,16,FLEN)
NAN_BOXED(23,16,FLEN)
NAN_BOXED(20880,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(23978,16,FLEN)
NAN_BOXED(69,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(21528,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(76,16,FLEN)
NAN_BOXED(19183,16,FLEN)
NAN_BOXED(47,16,FLEN)
NAN_BOXED(25,16,FLEN)
NAN_BOXED(20766,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(65,16,FLEN)
NAN_BOXED(19410,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(43,16,FLEN)
NAN_BOXED(19863,16,FLEN)
NAN_BOXED(67,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(20022,16,FLEN)
NAN_BOXED(53,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(18806,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(1087,16,FLEN)
NAN_BOXED(10240,16,FLEN)
NAN_BOXED(1059,16,FLEN)
NAN_BOXED(1102,16,FLEN)
NAN_BOXED(10970,16,FLEN)
NAN_BOXED(1085,16,FLEN)
NAN_BOXED(1109,16,FLEN)
NAN_BOXED(10929,16,FLEN)
NAN_BOXED(1086,16,FLEN)
NAN_BOXED(1087,16,FLEN)
NAN_BOXED(8494,16,FLEN)
NAN_BOXED(1043,16,FLEN)
NAN_BOXED(1117,16,FLEN)
NAN_BOXED(10128,16,FLEN)
NAN_BOXED(1073,16,FLEN)
NAN_BOXED(1088,16,FLEN)
NAN_BOXED(8071,16,FLEN)
NAN_BOXED(1064,16,FLEN)
NAN_BOXED(1106,16,FLEN)
NAN_BOXED(39784,16,FLEN)
NAN_BOXED(1084,16,FLEN)
NAN_BOXED(1066,16,FLEN)
NAN_BOXED(44252,16,FLEN)
NAN_BOXED(1071,16,FLEN)
NAN_BOXED(1109,16,FLEN)
NAN_BOXED(45767,16,FLEN)
NAN_BOXED(1045,16,FLEN)
NAN_BOXED(1104,16,FLEN)
NAN_BOXED(46773,16,FLEN)
NAN_BOXED(1073,16,FLEN)
NAN_BOXED(1113,16,FLEN)
NAN_BOXED(16292,16,FLEN)
NAN_BOXED(1102,16,FLEN)
NAN_BOXED(1059,16,FLEN)
NAN_BOXED(16357,16,FLEN)
NAN_BOXED(1065,16,FLEN)
NAN_BOXED(1107,16,FLEN)
NAN_BOXED(16281,16,FLEN)
NAN_BOXED(1075,16,FLEN)
NAN_BOXED(1087,16,FLEN)
NAN_BOXED(16361,16,FLEN)
NAN_BOXED(1118,16,FLEN)
NAN_BOXED(1045,16,FLEN)
NAN_BOXED(16389,16,FLEN)
NAN_BOXED(1062,16,FLEN)
NAN_BOXED(1096,16,FLEN)
NAN_BOXED(16280,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1104,16,FLEN)
NAN_BOXED(16348,16,FLEN)
NAN_BOXED(1082,16,FLEN)
NAN_BOXED(1032,16,FLEN)
NAN_BOXED(16451,16,FLEN)
NAN_BOXED(1048,16,FLEN)
NAN_BOXED(1028,16,FLEN)
NAN_BOXED(16546,16,FLEN)
NAN_BOXED(1103,16,FLEN)
NAN_BOXED(1097,16,FLEN)
NAN_BOXED(16561,16,FLEN)
NAN_BOXED(1039,16,FLEN)
NAN_BOXED(30808,16,FLEN)
NAN_BOXED(47792,16,FLEN)
NAN_BOXED(30812,16,FLEN)
NAN_BOXED(30768,16,FLEN)
NAN_BOXED(47940,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(47855,16,FLEN)
NAN_BOXED(30796,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(48044,16,FLEN)
NAN_BOXED(30745,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(47986,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(47916,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30775,16,FLEN)
NAN_BOXED(47771,16,FLEN)
NAN_BOXED(30788,16,FLEN)
NAN_BOXED(30783,16,FLEN)
NAN_BOXED(47747,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30781,16,FLEN)
NAN_BOXED(47471,16,FLEN)
NAN_BOXED(30750,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(46884,16,FLEN)
NAN_BOXED(30768,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(16836,16,FLEN)
NAN_BOXED(30739,16,FLEN)
NAN_BOXED(30808,16,FLEN)
NAN_BOXED(16810,16,FLEN)
NAN_BOXED(30801,16,FLEN)
NAN_BOXED(30752,16,FLEN)
NAN_BOXED(16884,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30761,16,FLEN)
NAN_BOXED(16841,16,FLEN)
NAN_BOXED(30739,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(16920,16,FLEN)
NAN_BOXED(30801,16,FLEN)
NAN_BOXED(30806,16,FLEN)
NAN_BOXED(16767,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(30812,16,FLEN)
NAN_BOXED(16745,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(30726,16,FLEN)
NAN_BOXED(16864,16,FLEN)
NAN_BOXED(30803,16,FLEN)
NAN_BOXED(30782,16,FLEN)
NAN_BOXED(16715,16,FLEN)
NAN_BOXED(30780,16,FLEN)
NAN_BOXED(30813,16,FLEN)
NAN_BOXED(16537,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(12370,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(15896,16,FLEN)
NAN_BOXED(98,16,FLEN)
NAN_BOXED(85,16,FLEN)
NAN_BOXED(14757,16,FLEN)
NAN_BOXED(76,16,FLEN)
NAN_BOXED(61,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(98,16,FLEN)
NAN_BOXED(95,16,FLEN)
NAN_BOXED(45411,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(41,16,FLEN)
NAN_BOXED(47528,16,FLEN)
NAN_BOXED(99,16,FLEN)
NAN_BOXED(63,16,FLEN)
NAN_BOXED(51126,16,FLEN)
NAN_BOXED(26,16,FLEN)
NAN_BOXED(69,16,FLEN)
NAN_BOXED(15404,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(85,16,FLEN)
NAN_BOXED(16058,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(15965,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(15426,16,FLEN)
NAN_BOXED(46701,16,FLEN)
NAN_BOXED(15434,16,FLEN)
NAN_BOXED(15443,16,FLEN)
NAN_BOXED(16314,16,FLEN)
NAN_BOXED(15450,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 36*((SIGALIGN)/4),4,0xdeadbeef


signature_x2_0:
    .fill 228*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
