[core]
	repositoryformatversion = 0
	filemode = true
	bare = false
	logallrefupdates = true
[submodule]
	active = .
[remote "origin"]
	url = https://github.com/Wren6991/Hazard3
	fetch = +refs/heads/stable:refs/remotes/origin/stable
[branch "stable"]
	remote = origin
	merge = refs/heads/stable
[submodule "example_soc/libfpga"]
	url = https://github.com/Wren6991/libfpga.git
[submodule "scripts"]
	url = https://github.com/Wren6991/fpgascripts
[submodule "test/formal/riscv-formal"]
	url = https://github.com/Wren6991/riscv-formal.git
[submodule "test/sim/embench/embench-iot"]
	url = https://github.com/Wren6991/embench-iot.git
[submodule "test/sim/riscv-compliance/riscv-arch-test"]
	url = https://github.com/wren6991/riscv-arch-test.git
[submodule "test/sim/riscv-tests/riscv-tests"]
	url = https://github.com/Wren6991/riscv-tests.git