//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1 reg
// RDY_set_addr_map               O     1 const
// RDY_server_request_put         O     1 reg
// server_response_get            O    66 reg
// RDY_server_response_get        O     1 reg
// get_timer_interrupt_req_get    O     1 reg
// RDY_get_timer_interrupt_req_get  O     1 reg
// get_sw_interrupt_req_get       O     1 reg
// RDY_get_sw_interrupt_req_get   O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// set_addr_map_addr_base         I    64 reg
// set_addr_map_addr_lim          I    64 reg
// server_request_put             I   137 reg
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_set_addr_map                I     1
// EN_server_request_put          I     1
// EN_server_response_get         I     1
// EN_get_timer_interrupt_req_get  I     1
// EN_get_sw_interrupt_req_get    I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkNear_Mem_IO(CLK,
		     RST_N,

		     EN_server_reset_request_put,
		     RDY_server_reset_request_put,

		     EN_server_reset_response_get,
		     RDY_server_reset_response_get,

		     set_addr_map_addr_base,
		     set_addr_map_addr_lim,
		     EN_set_addr_map,
		     RDY_set_addr_map,

		     server_request_put,
		     EN_server_request_put,
		     RDY_server_request_put,

		     EN_server_response_get,
		     server_response_get,
		     RDY_server_response_get,

		     EN_get_timer_interrupt_req_get,
		     get_timer_interrupt_req_get,
		     RDY_get_timer_interrupt_req_get,

		     EN_get_sw_interrupt_req_get,
		     get_sw_interrupt_req_get,
		     RDY_get_sw_interrupt_req_get);
  input  CLK;
  input  RST_N;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // action method set_addr_map
  input  [63 : 0] set_addr_map_addr_base;
  input  [63 : 0] set_addr_map_addr_lim;
  input  EN_set_addr_map;
  output RDY_set_addr_map;

  // action method server_request_put
  input  [136 : 0] server_request_put;
  input  EN_server_request_put;
  output RDY_server_request_put;

  // actionvalue method server_response_get
  input  EN_server_response_get;
  output [65 : 0] server_response_get;
  output RDY_server_response_get;

  // actionvalue method get_timer_interrupt_req_get
  input  EN_get_timer_interrupt_req_get;
  output get_timer_interrupt_req_get;
  output RDY_get_timer_interrupt_req_get;

  // actionvalue method get_sw_interrupt_req_get
  input  EN_get_sw_interrupt_req_get;
  output get_sw_interrupt_req_get;
  output RDY_get_sw_interrupt_req_get;

  // signals for module outputs
  wire [65 : 0] server_response_get;
  wire RDY_get_sw_interrupt_req_get,
       RDY_get_timer_interrupt_req_get,
       RDY_server_request_put,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       RDY_server_response_get,
       RDY_set_addr_map,
       get_sw_interrupt_req_get,
       get_timer_interrupt_req_get;

  // inlined wires
  wire [63 : 0] crg_time$port0__write_1,
		crg_time$port1__write_1,
		crg_time$port2__read,
		crg_timecmp$port1__write_1,
		crg_timecmp$port2__read;
  wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register crg_time
  reg [63 : 0] crg_time;
  wire [63 : 0] crg_time$D_IN;
  wire crg_time$EN;

  // register crg_timecmp
  reg [63 : 0] crg_timecmp;
  wire [63 : 0] crg_timecmp$D_IN;
  wire crg_timecmp$EN;

  // register rg_addr_base
  reg [63 : 0] rg_addr_base;
  wire [63 : 0] rg_addr_base$D_IN;
  wire rg_addr_base$EN;

  // register rg_addr_lim
  reg [63 : 0] rg_addr_lim;
  wire [63 : 0] rg_addr_lim$D_IN;
  wire rg_addr_lim$EN;

  // register rg_msip
  reg rg_msip;
  wire rg_msip$D_IN, rg_msip$EN;

  // register rg_mtip
  reg rg_mtip;
  wire rg_mtip$D_IN, rg_mtip$EN;

  // register rg_state
  reg rg_state;
  wire rg_state$D_IN, rg_state$EN;

  // ports of submodule f_reqs
  wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT;
  wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule f_rsps
  wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT;
  wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N;

  // ports of submodule f_sw_interrupt_req
  wire f_sw_interrupt_req$CLR,
       f_sw_interrupt_req$DEQ,
       f_sw_interrupt_req$D_IN,
       f_sw_interrupt_req$D_OUT,
       f_sw_interrupt_req$EMPTY_N,
       f_sw_interrupt_req$ENQ,
       f_sw_interrupt_req$FULL_N;

  // ports of submodule f_timer_interrupt_req
  wire f_timer_interrupt_req$CLR,
       f_timer_interrupt_req$DEQ,
       f_timer_interrupt_req$D_IN,
       f_timer_interrupt_req$D_OUT,
       f_timer_interrupt_req$EMPTY_N,
       f_timer_interrupt_req$ENQ,
       f_timer_interrupt_req$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_compare,
       CAN_FIRE_RL_rl_process_rd_req,
       CAN_FIRE_RL_rl_process_wr_req,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_rl_soft_reset,
       CAN_FIRE_RL_rl_tick_timer,
       CAN_FIRE_get_sw_interrupt_req_get,
       CAN_FIRE_get_timer_interrupt_req_get,
       CAN_FIRE_server_request_put,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_server_response_get,
       CAN_FIRE_set_addr_map,
       WILL_FIRE_RL_rl_compare,
       WILL_FIRE_RL_rl_process_rd_req,
       WILL_FIRE_RL_rl_process_wr_req,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_rl_soft_reset,
       WILL_FIRE_RL_rl_tick_timer,
       WILL_FIRE_get_sw_interrupt_req_get,
       WILL_FIRE_get_timer_interrupt_req_get,
       WILL_FIRE_server_request_put,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_server_response_get,
       WILL_FIRE_set_addr_map;

  // inputs to muxes for submodule ports
  wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2;
  wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1,
		MUX_crg_timecmp$port1__write_1__VAL_1;
  wire MUX_crg_time$port1__write_1__SEL_1,
       MUX_crg_timecmp$port1__write_1__SEL_1,
       MUX_rg_msip$write_1__SEL_1,
       MUX_rg_mtip$write_1__SEL_1,
       MUX_rg_mtip$write_1__VAL_1,
       MUX_rg_state$write_1__SEL_1;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h8676;
  reg [31 : 0] v__h8808;
  reg [31 : 0] v__h1471;
  reg [31 : 0] v__h1868;
  reg [31 : 0] v__h2065;
  reg [31 : 0] v__h1714;
  reg [31 : 0] v__h2442;
  reg [31 : 0] v__h7890;
  reg [31 : 0] v__h8258;
  reg [31 : 0] v__h8368;
  reg [31 : 0] v__h8475;
  reg [31 : 0] v__h1465;
  reg [31 : 0] v__h1708;
  reg [31 : 0] v__h1862;
  reg [31 : 0] v__h2059;
  reg [31 : 0] v__h2436;
  reg [31 : 0] v__h7884;
  reg [31 : 0] v__h8252;
  reg [31 : 0] v__h8362;
  reg [31 : 0] v__h8469;
  reg [31 : 0] v__h8670;
  reg [31 : 0] v__h8802;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] rsp_rdata__h2209;
  wire [63 : 0] byte_addr__h1981,
		mask__h2865,
		mask__h5362,
		new_data__h5360,
		new_time__h4107,
		new_time__h6632,
		new_timecmp__h2834,
		new_timecmp__h5331,
		old_time__h6631,
		rdata__h1996,
		rdata__h2020,
		rdata__h2026,
		x__h2876,
		x__h4149,
		x__h5373,
		x__h6674,
		y__h2877,
		y__h2878,
		y__h5374,
		y__h5375;
  wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132,
	       SEXT_f_reqs_first__8_BIT_1_28___d129,
	       SEXT_f_reqs_first__8_BIT_2_24___d125,
	       SEXT_f_reqs_first__8_BIT_3_21___d122,
	       SEXT_f_reqs_first__8_BIT_4_17___d118,
	       SEXT_f_reqs_first__8_BIT_5_14___d115,
	       SEXT_f_reqs_first__8_BIT_6_10___d111,
	       SEXT_f_reqs_first__8_BIT_7_07___d108;
  wire NOT_cfg_verbosity_read_ULE_1_0___d31,
       rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // action method set_addr_map
  assign RDY_set_addr_map = 1'd1 ;
  assign CAN_FIRE_set_addr_map = 1'd1 ;
  assign WILL_FIRE_set_addr_map = EN_set_addr_map ;

  // action method server_request_put
  assign RDY_server_request_put = f_reqs$FULL_N ;
  assign CAN_FIRE_server_request_put = f_reqs$FULL_N ;
  assign WILL_FIRE_server_request_put = EN_server_request_put ;

  // actionvalue method server_response_get
  assign server_response_get = f_rsps$D_OUT ;
  assign RDY_server_response_get = f_rsps$EMPTY_N ;
  assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ;
  assign WILL_FIRE_server_response_get = EN_server_response_get ;

  // actionvalue method get_timer_interrupt_req_get
  assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ;
  assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ;
  assign CAN_FIRE_get_timer_interrupt_req_get =
	     f_timer_interrupt_req$EMPTY_N ;
  assign WILL_FIRE_get_timer_interrupt_req_get =
	     EN_get_timer_interrupt_req_get ;

  // actionvalue method get_sw_interrupt_req_get
  assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ;
  assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ;
  assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ;
  assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ;

  // submodule f_reqs
  FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(f_reqs$D_IN),
						   .ENQ(f_reqs$ENQ),
						   .DEQ(f_reqs$DEQ),
						   .CLR(f_reqs$CLR),
						   .D_OUT(f_reqs$D_OUT),
						   .FULL_N(f_reqs$FULL_N),
						   .EMPTY_N(f_reqs$EMPTY_N));

  // submodule f_reset_reqs
  FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N),
					 .CLK(CLK),
					 .ENQ(f_reset_reqs$ENQ),
					 .DEQ(f_reset_reqs$DEQ),
					 .CLR(f_reset_reqs$CLR),
					 .FULL_N(f_reset_reqs$FULL_N),
					 .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
					 .CLK(CLK),
					 .ENQ(f_reset_rsps$ENQ),
					 .DEQ(f_reset_rsps$DEQ),
					 .CLR(f_reset_rsps$CLR),
					 .FULL_N(f_reset_rsps$FULL_N),
					 .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule f_rsps
  FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(f_rsps$D_IN),
						  .ENQ(f_rsps$ENQ),
						  .DEQ(f_rsps$DEQ),
						  .CLR(f_rsps$CLR),
						  .D_OUT(f_rsps$D_OUT),
						  .FULL_N(f_rsps$FULL_N),
						  .EMPTY_N(f_rsps$EMPTY_N));

  // submodule f_sw_interrupt_req
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N),
							     .CLK(CLK),
							     .D_IN(f_sw_interrupt_req$D_IN),
							     .ENQ(f_sw_interrupt_req$ENQ),
							     .DEQ(f_sw_interrupt_req$DEQ),
							     .CLR(f_sw_interrupt_req$CLR),
							     .D_OUT(f_sw_interrupt_req$D_OUT),
							     .FULL_N(f_sw_interrupt_req$FULL_N),
							     .EMPTY_N(f_sw_interrupt_req$EMPTY_N));

  // submodule f_timer_interrupt_req
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N),
								.CLK(CLK),
								.D_IN(f_timer_interrupt_req$D_IN),
								.ENQ(f_timer_interrupt_req$ENQ),
								.DEQ(f_timer_interrupt_req$DEQ),
								.CLR(f_timer_interrupt_req$CLR),
								.D_OUT(f_timer_interrupt_req$D_OUT),
								.FULL_N(f_timer_interrupt_req$FULL_N),
								.EMPTY_N(f_timer_interrupt_req$EMPTY_N));

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset =
	     f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // rule RL_rl_soft_reset
  assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ;

  // rule RL_rl_process_rd_req
  assign CAN_FIRE_RL_rl_process_rd_req =
	     f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state &&
	     !f_reset_reqs$EMPTY_N &&
	     f_reqs$D_OUT[136] ;
  assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ;

  // rule RL_rl_compare
  assign CAN_FIRE_RL_rl_compare = MUX_rg_mtip$write_1__SEL_1 ;
  assign WILL_FIRE_RL_rl_compare = MUX_rg_mtip$write_1__SEL_1 ;

  // rule RL_rl_tick_timer
  assign CAN_FIRE_RL_rl_tick_timer =
	     rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF &&
	     !f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ;

  // rule RL_rl_process_wr_req
  assign CAN_FIRE_RL_rl_process_wr_req =
	     f_reqs$EMPTY_N && f_rsps$FULL_N &&
	     (byte_addr__h1981 != 64'h0 ||
	      rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ||
	      f_sw_interrupt_req$FULL_N) &&
	     rg_state &&
	     !f_reset_reqs$EMPTY_N &&
	     !f_reqs$D_OUT[136] ;
  assign WILL_FIRE_RL_rl_process_wr_req =
	     CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ;

  // inputs to muxes for submodule ports
  assign MUX_crg_time$port1__write_1__SEL_1 =
	     WILL_FIRE_RL_rl_process_wr_req &&
	     (byte_addr__h1981 == 64'h000000000000BFF8 ||
	      byte_addr__h1981 == 64'h000000000000BFFC) ;
  assign MUX_crg_timecmp$port1__write_1__SEL_1 =
	     WILL_FIRE_RL_rl_process_wr_req &&
	     (byte_addr__h1981 == 64'h0000000000004000 ||
	      byte_addr__h1981 == 64'h0000000000004004) ;
  assign MUX_rg_msip$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 &&
	     !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ;
  assign MUX_rg_mtip$write_1__SEL_1 =
	     f_timer_interrupt_req$FULL_N && rg_state &&
	     rg_mtip != MUX_rg_mtip$write_1__VAL_1 &&
	     !f_reset_reqs$EMPTY_N ;
  assign MUX_rg_state$write_1__SEL_1 =
	     f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ;
  assign MUX_crg_time$port1__write_1__VAL_1 =
	     (byte_addr__h1981 == 64'h000000000000BFF8) ?
	       new_time__h4107 :
	       new_time__h6632 ;
  assign MUX_crg_timecmp$port1__write_1__VAL_1 =
	     (byte_addr__h1981 == 64'h0000000000004000) ?
	       new_timecmp__h2834 :
	       new_timecmp__h5331 ;
  assign MUX_f_rsps$enq_1__VAL_1 =
	     { 1'd1,
	       byte_addr__h1981 == 64'h0 ||
	       byte_addr__h1981 == 64'h0000000000004000 ||
	       byte_addr__h1981 == 64'h000000000000BFF8 ||
	       byte_addr__h1981 == 64'h0000000000000004 ||
	       byte_addr__h1981 == 64'h0000000000004004 ||
	       byte_addr__h1981 == 64'h000000000000BFFC,
	       rsp_rdata__h2209 } ;
  assign MUX_f_rsps$enq_1__VAL_2 =
	     { 1'd0,
	       byte_addr__h1981 == 64'h0 ||
	       byte_addr__h1981 == 64'h0000000000004000 ||
	       byte_addr__h1981 == 64'h000000000000BFF8 ||
	       byte_addr__h1981 == 64'h0000000000000004 ||
	       byte_addr__h1981 == 64'h0000000000004004 ||
	       byte_addr__h1981 == 64'h000000000000BFFC,
	       64'hAAAAAAAAAAAAAAAA } ;
  assign MUX_rg_mtip$write_1__VAL_1 = crg_time >= crg_timecmp ;

  // inlined wires
  assign crg_time$port0__write_1 = crg_time + 64'd1 ;
  assign crg_time$EN_port1__write =
	     WILL_FIRE_RL_rl_process_wr_req &&
	     (byte_addr__h1981 == 64'h000000000000BFF8 ||
	      byte_addr__h1981 == 64'h000000000000BFFC) ||
	     WILL_FIRE_RL_rl_reset ;
  assign crg_time$port1__write_1 =
	     MUX_crg_time$port1__write_1__SEL_1 ?
	       MUX_crg_time$port1__write_1__VAL_1 :
	       64'd1 ;
  assign crg_time$port2__read =
	     crg_time$EN_port1__write ?
	       crg_time$port1__write_1 :
	       old_time__h6631 ;
  assign crg_timecmp$EN_port1__write =
	     WILL_FIRE_RL_rl_process_wr_req &&
	     (byte_addr__h1981 == 64'h0000000000004000 ||
	      byte_addr__h1981 == 64'h0000000000004004) ||
	     WILL_FIRE_RL_rl_reset ;
  assign crg_timecmp$port1__write_1 =
	     MUX_crg_timecmp$port1__write_1__SEL_1 ?
	       MUX_crg_timecmp$port1__write_1__VAL_1 :
	       64'd0 ;
  assign crg_timecmp$port2__read =
	     crg_timecmp$EN_port1__write ?
	       crg_timecmp$port1__write_1 :
	       crg_timecmp ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = 4'h0 ;
  assign cfg_verbosity$EN = 1'b0 ;

  // register crg_time
  assign crg_time$D_IN = crg_time$port2__read ;
  assign crg_time$EN = 1'b1 ;

  // register crg_timecmp
  assign crg_timecmp$D_IN = crg_timecmp$port2__read ;
  assign crg_timecmp$EN = 1'b1 ;

  // register rg_addr_base
  assign rg_addr_base$D_IN = set_addr_map_addr_base ;
  assign rg_addr_base$EN = EN_set_addr_map ;

  // register rg_addr_lim
  assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
  assign rg_addr_lim$EN = EN_set_addr_map ;

  // register rg_msip
  assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ;
  assign rg_msip$EN =
	     WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 &&
	     !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ||
	     WILL_FIRE_RL_rl_reset ;

  // register rg_mtip
  assign rg_mtip$D_IN =
	     !WILL_FIRE_RL_rl_compare || MUX_rg_mtip$write_1__VAL_1 ;
  assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ;

  // register rg_state
  assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ;
  assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ;

  // submodule f_reqs
  assign f_reqs$D_IN = server_request_put ;
  assign f_reqs$ENQ = EN_server_request_put ;
  assign f_reqs$DEQ =
	     WILL_FIRE_RL_rl_process_wr_req ||
	     WILL_FIRE_RL_rl_process_rd_req ;
  assign f_reqs$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule f_reset_reqs
  assign f_reset_reqs$ENQ = EN_server_reset_request_put ;
  assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ;
  assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule f_rsps
  assign f_rsps$D_IN =
	     WILL_FIRE_RL_rl_process_rd_req ?
	       MUX_f_rsps$enq_1__VAL_1 :
	       MUX_f_rsps$enq_1__VAL_2 ;
  assign f_rsps$ENQ =
	     WILL_FIRE_RL_rl_process_rd_req ||
	     WILL_FIRE_RL_rl_process_wr_req ;
  assign f_rsps$DEQ = EN_server_response_get ;
  assign f_rsps$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule f_sw_interrupt_req
  assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ;
  assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ;
  assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ;
  assign f_sw_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ;

  // submodule f_timer_interrupt_req
  assign f_timer_interrupt_req$D_IN = MUX_rg_mtip$write_1__VAL_1 ;
  assign f_timer_interrupt_req$ENQ = MUX_rg_mtip$write_1__SEL_1 ;
  assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ;
  assign f_timer_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ;

  // remaining internal signals
  assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ;
  assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ;
  assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ;
  assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ;
  assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ;
  assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ;
  assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ;
  assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ;
  assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ;
  assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ;
  assign mask__h2865 =
	     { SEXT_f_reqs_first__8_BIT_7_07___d108,
	       SEXT_f_reqs_first__8_BIT_6_10___d111,
	       SEXT_f_reqs_first__8_BIT_5_14___d115,
	       SEXT_f_reqs_first__8_BIT_4_17___d118,
	       SEXT_f_reqs_first__8_BIT_3_21___d122,
	       SEXT_f_reqs_first__8_BIT_2_24___d125,
	       SEXT_f_reqs_first__8_BIT_1_28___d129,
	       SEXT_f_reqs_first__8_BIT_0_31___d132 } ;
  assign mask__h5362 =
	     { SEXT_f_reqs_first__8_BIT_3_21___d122,
	       SEXT_f_reqs_first__8_BIT_2_24___d125,
	       SEXT_f_reqs_first__8_BIT_1_28___d129,
	       SEXT_f_reqs_first__8_BIT_0_31___d132,
	       32'd0 } ;
  assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ;
  assign new_time__h4107 = x__h4149 | y__h2877 ;
  assign new_time__h6632 = x__h6674 | y__h5374 ;
  assign new_timecmp__h2834 = x__h2876 | y__h2877 ;
  assign new_timecmp__h5331 = x__h5373 | y__h5374 ;
  assign old_time__h6631 =
	     CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ;
  assign rdata__h1996 = { 63'd0, rg_msip } ;
  assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ;
  assign rdata__h2026 = { 32'd0, crg_time[63:32] } ;
  assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 =
	     rg_msip == f_reqs$D_OUT[8] ;
  assign x__h2876 = crg_timecmp & y__h2878 ;
  assign x__h4149 = old_time__h6631 & y__h2878 ;
  assign x__h5373 = crg_timecmp & y__h5375 ;
  assign x__h6674 = old_time__h6631 & y__h5375 ;
  assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ;
  assign y__h2878 =
	     { ~SEXT_f_reqs_first__8_BIT_7_07___d108,
	       ~SEXT_f_reqs_first__8_BIT_6_10___d111,
	       ~SEXT_f_reqs_first__8_BIT_5_14___d115,
	       ~SEXT_f_reqs_first__8_BIT_4_17___d118,
	       ~SEXT_f_reqs_first__8_BIT_3_21___d122,
	       ~SEXT_f_reqs_first__8_BIT_2_24___d125,
	       ~SEXT_f_reqs_first__8_BIT_1_28___d129,
	       ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ;
  assign y__h5374 = new_data__h5360 & mask__h5362 ;
  assign y__h5375 =
	     { ~SEXT_f_reqs_first__8_BIT_3_21___d122,
	       ~SEXT_f_reqs_first__8_BIT_2_24___d125,
	       ~SEXT_f_reqs_first__8_BIT_1_28___d129,
	       ~SEXT_f_reqs_first__8_BIT_0_31___d132,
	       32'hFFFFFFFF } ;
  always@(byte_addr__h1981 or
	  rdata__h1996 or
	  crg_timecmp or rdata__h2020 or crg_time or rdata__h2026)
  begin
    case (byte_addr__h1981)
      64'h0: rsp_rdata__h2209 = rdata__h1996;
      64'h0000000000000004: rsp_rdata__h2209 = 64'd0;
      64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp;
      64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020;
      64'h000000000000BFF8: rsp_rdata__h2209 = crg_time;
      64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026;
      default: rsp_rdata__h2209 = 64'd0;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1;
	crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1;
	crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0;
	rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1;
	rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN;
	if (crg_timecmp$EN)
	  crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN;
	if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
      end
    if (rg_addr_base$EN)
      rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
    if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
    if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    crg_time = 64'hAAAAAAAAAAAAAAAA;
    crg_timecmp = 64'hAAAAAAAAAAAAAAAA;
    rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
    rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
    rg_msip = 1'h0;
    rg_mtip = 1'h0;
    rg_state = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_get_timer_interrupt_req_get &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	begin
	  v__h8676 = $stime;
	  #0;
	end
    v__h8670 = v__h8676 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_get_timer_interrupt_req_get &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x",
		 v__h8670,
		 f_timer_interrupt_req$D_OUT);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31)
	begin
	  v__h8808 = $stime;
	  #0;
	end
    v__h8802 = v__h8808 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x",
		 v__h8802,
		 f_sw_interrupt_req$D_OUT);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0)
	begin
	  v__h1471 = $stime;
	  #0;
	end
    v__h1465 = v__h1471 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0)
	$display("%0d: Near_Mem_IO.rl_reset", v__h1465);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	begin
	  v__h1868 = $stime;
	  #0;
	end
    v__h1862 = v__h1868 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d",
		 v__h1862,
		 rg_mtip);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("Near_Mem_IO_Req { ", "read_not_write: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", f_reqs$D_OUT[135:72]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", f_reqs$D_OUT[71:8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", f_reqs$D_OUT[7:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	begin
	  v__h2065 = $stime;
	  #0;
	end
    v__h2059 = v__h2065 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr",
		 v__h2059);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("            ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("Near_Mem_IO_Req { ", "read_not_write: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("'h%h", f_reqs$D_OUT[135:72]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("'h%h", f_reqs$D_OUT[71:8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("'h%h", f_reqs$D_OUT[7:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("    <= ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("Near_Mem_IO_Rsp { ", "read_not_write: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "ok: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31 &&
	  byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31 &&
	  (byte_addr__h1981 == 64'h0 ||
	   byte_addr__h1981 == 64'h0000000000004000 ||
	   byte_addr__h1981 == 64'h000000000000BFF8 ||
	   byte_addr__h1981 == 64'h0000000000000004 ||
	   byte_addr__h1981 == 64'h0000000000004004 ||
	   byte_addr__h1981 == 64'h000000000000BFFC))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", rsp_rdata__h2209, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_rd_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31)
	begin
	  v__h1714 = $stime;
	  #0;
	end
    v__h1708 = v__h1714 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d",
		 v__h1708,
		 MUX_rg_mtip$write_1__VAL_1,
		 crg_time,
		 crg_timecmp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	begin
	  v__h2442 = $stime;
	  #0;
	end
    v__h2436 = v__h2442 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d",
		 v__h2436,
		 rg_mtip);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("Near_Mem_IO_Req { ", "read_not_write: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", f_reqs$D_OUT[135:72]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", f_reqs$D_OUT[71:8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", f_reqs$D_OUT[7:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 &&
	  !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("    new MSIP = %0d", f_reqs$D_OUT[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004000 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("    Writing MTIMECMP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004000 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        old MTIMECMP         = 0x%0h", crg_timecmp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004000 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        new MTIMECMP         = 0x%0h", new_timecmp__h2834);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004000 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        cur MTIME            = 0x%0h", old_time__h6631);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004000 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        new MTIMECMP - MTIME = 0x%0h",
		 new_timecmp__h2834 - old_time__h6631);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h000000000000BFF8 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("    Writing MTIME");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h000000000000BFF8 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        old MTIME = 0x%0h", old_time__h6631);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h000000000000BFF8 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        new MTIME = 0x%0h", new_time__h4107);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004004 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("    Writing MTIMECMP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004004 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        old MTIMECMP         = 0x%0h", crg_timecmp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004004 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        new MTIMECMP         = 0x%0h", new_timecmp__h5331);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004004 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        cur MTIME            = 0x%0h", old_time__h6631);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h0000000000004004 &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        new MTIMECMP - MTIME = 0x%0h",
		 new_timecmp__h5331 - old_time__h6631);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h000000000000BFFC &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("    Writing MTIME");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h000000000000BFFC &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        old MTIME = 0x%0h", old_time__h6631);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  byte_addr__h1981 == 64'h000000000000BFFC &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$display("        new MTIME = 0x%0h", new_time__h6632);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	begin
	  v__h7890 = $stime;
	  #0;
	end
    v__h7884 = v__h7890 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr",
		 v__h7884);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("            ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("Near_Mem_IO_Req { ", "read_not_write: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("'h%h", f_reqs$D_OUT[135:72]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write(", ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("'h%h", f_reqs$D_OUT[71:8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("'h%h", f_reqs$D_OUT[7:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("    <= ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("Near_Mem_IO_Rsp { ", "read_not_write: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "ok: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31 &&
	  byte_addr__h1981 != 64'h0 &&
	  byte_addr__h1981 != 64'h0000000000004000 &&
	  byte_addr__h1981 != 64'h000000000000BFF8 &&
	  byte_addr__h1981 != 64'h0000000000000004 &&
	  byte_addr__h1981 != 64'h0000000000004004 &&
	  byte_addr__h1981 != 64'h000000000000BFFC)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31 &&
	  (byte_addr__h1981 == 64'h0 ||
	   byte_addr__h1981 == 64'h0000000000004000 ||
	   byte_addr__h1981 == 64'h000000000000BFF8 ||
	   byte_addr__h1981 == 64'h0000000000000004 ||
	   byte_addr__h1981 == 64'h0000000000004004 ||
	   byte_addr__h1981 == 64'h000000000000BFFC))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_process_wr_req &&
	  NOT_cfg_verbosity_read_ULE_1_0___d31)
	$write("\n");
    if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
      begin
        v__h8258 = $stime;
	#0;
      end
    v__h8252 = v__h8258 / 32'd10;
    if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
      $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
	       v__h8252,
	       set_addr_map_addr_base);
    if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
      begin
        v__h8368 = $stime;
	#0;
      end
    v__h8362 = v__h8368 / 32'd10;
    if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
      $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
	       v__h8362,
	       set_addr_map_addr_lim);
    if (EN_set_addr_map)
      begin
        v__h8475 = $stime;
	#0;
      end
    v__h8469 = v__h8475 / 32'd10;
    if (EN_set_addr_map)
      $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h",
	       v__h8469,
	       set_addr_map_addr_base,
	       set_addr_map_addr_lim);
  end
  // synopsys translate_on
endmodule  // mkNear_Mem_IO

