Skip to content

Workspace

/ RISC-V /
.git
.Xil
core
documentation
lib
peripherals
processor
test
build_digilent_arty_a7_100t.tclSep 18, 2026, 4:15:11 AM3.31 KiB
clockInfo.txtSep 18, 2026, 4:16:53 AM375 B
digilent_arty_a7_100t.bitSep 18, 2026, 4:18:11 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 18, 2026, 4:17:06 AM22.02 KiB
digilent_arty_a7_control_sets.rptSep 18, 2026, 4:17:05 AM25.43 KiB
digilent_arty_a7_drc.rptSep 18, 2026, 4:17:48 AM2.34 KiB
digilent_arty_a7_io.rptSep 18, 2026, 4:17:05 AM96.81 KiB
digilent_arty_a7_power.rptSep 18, 2026, 4:17:51 AM8.69 KiB
digilent_arty_a7_route_status.rptSep 18, 2026, 4:17:47 AM651 B
digilent_arty_a7_timing.rptSep 18, 2026, 4:17:49 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 18, 2026, 4:17:05 AM7.55 KiB
digilent_arty_a7_utilization_place.rptSep 18, 2026, 4:17:05 AM10.65 KiB
LICENSESep 18, 2026, 4:15:04 AM1.07 KiB
processor_ci_defines.vhSep 18, 2026, 4:15:11 AM300 B
README.mdSep 18, 2026, 4:15:04 AM812 B
simplified_pipeline.pngSep 18, 2026, 4:15:04 AM177.18 KiB