Skip to content

Workspace

/ RISC-V /
.git
.Xil
core
documentation
lib
peripherals
processor
test
build_digilent_arty_a7_100t.tclAug 30, 2026, 4:15:11 AM3.31 KiB
clockInfo.txtAug 30, 2026, 4:16:54 AM375 B
digilent_arty_a7_100t.bitAug 30, 2026, 4:18:13 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 30, 2026, 4:17:08 AM22.02 KiB
digilent_arty_a7_control_sets.rptAug 30, 2026, 4:17:07 AM25.43 KiB
digilent_arty_a7_drc.rptAug 30, 2026, 4:17:50 AM2.34 KiB
digilent_arty_a7_io.rptAug 30, 2026, 4:17:07 AM96.81 KiB
digilent_arty_a7_power.rptAug 30, 2026, 4:17:53 AM8.69 KiB
digilent_arty_a7_route_status.rptAug 30, 2026, 4:17:49 AM651 B
digilent_arty_a7_timing.rptAug 30, 2026, 4:17:51 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 30, 2026, 4:17:06 AM7.55 KiB
digilent_arty_a7_utilization_place.rptAug 30, 2026, 4:17:07 AM10.65 KiB
LICENSEAug 30, 2026, 4:15:04 AM1.07 KiB
processor_ci_defines.vhAug 30, 2026, 4:15:11 AM300 B
README.mdAug 30, 2026, 4:15:04 AM812 B
simplified_pipeline.pngAug 30, 2026, 4:15:04 AM177.18 KiB