Skip to content
[Jenkins]Jenkins
log in

Workspace

/ RPU /
.git
.Xil
tests
vhdl
build_digilent_arty_a7_100t.tclJul 23, 2026, 2:11:07 AM3.02 KiB
clockInfo.txtJul 23, 2026, 2:12:35 AM375 B
digilent_arty_a7_100t.bitJul 23, 2026, 2:13:44 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 23, 2026, 2:12:46 AM21.28 KiB
digilent_arty_a7_control_sets.rptJul 23, 2026, 2:12:45 AM19.69 KiB
digilent_arty_a7_drc.rptJul 23, 2026, 2:13:23 AM19.75 KiB
digilent_arty_a7_io.rptJul 23, 2026, 2:12:45 AM96.81 KiB
digilent_arty_a7_power.rptJul 23, 2026, 2:13:25 AM8.85 KiB
digilent_arty_a7_route_status.rptJul 23, 2026, 2:13:21 AM651 B
digilent_arty_a7_timing.rptJul 23, 2026, 2:13:23 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 23, 2026, 2:12:45 AM5.05 KiB
digilent_arty_a7_utilization_place.rptJul 23, 2026, 2:12:45 AM10.87 KiB
LICENSEJul 23, 2026, 2:08:44 AM11.09 KiB
processor_ci_defines.vhJul 23, 2026, 2:11:07 AM300 B
README.mdJul 23, 2026, 2:08:44 AM1.24 KiB
rpu_core_diagram.pngJul 23, 2026, 2:08:44 AM87.03 KiB