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build_digilent_arty_a7_100t.tclAug 24, 2026, 2:11:23 AM3.02 KiB
clockInfo.txtAug 24, 2026, 2:12:51 AM375 B
digilent_arty_a7_100t.bitAug 24, 2026, 2:13:59 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 24, 2026, 2:13:02 AM21.28 KiB
digilent_arty_a7_control_sets.rptAug 24, 2026, 2:13:01 AM19.69 KiB
digilent_arty_a7_drc.rptAug 24, 2026, 2:13:38 AM19.75 KiB
digilent_arty_a7_io.rptAug 24, 2026, 2:13:01 AM96.81 KiB
digilent_arty_a7_power.rptAug 24, 2026, 2:13:40 AM8.85 KiB
digilent_arty_a7_route_status.rptAug 24, 2026, 2:13:37 AM651 B
digilent_arty_a7_timing.rptAug 24, 2026, 2:13:38 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 24, 2026, 2:13:01 AM5.05 KiB
digilent_arty_a7_utilization_place.rptAug 24, 2026, 2:13:01 AM10.87 KiB
LICENSEAug 24, 2026, 2:09:00 AM11.09 KiB
processor_ci_defines.vhAug 24, 2026, 2:11:23 AM300 B
README.mdAug 24, 2026, 2:09:00 AM1.24 KiB
rpu_core_diagram.pngAug 24, 2026, 2:09:00 AM87.03 KiB