| .git |
| .Xil |
| tests |
| vhdl |
| build_digilent_arty_a7_100t.tcl | Jul 17, 2026, 2:11:34 AM | 3.02 KiB | |
| clockInfo.txt | Jul 17, 2026, 2:13:03 AM | 375 B | |
| digilent_arty_a7_100t.bit | Jul 17, 2026, 2:14:13 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Jul 17, 2026, 2:13:13 AM | 21.28 KiB | |
| digilent_arty_a7_control_sets.rpt | Jul 17, 2026, 2:13:12 AM | 19.69 KiB | |
| digilent_arty_a7_drc.rpt | Jul 17, 2026, 2:13:51 AM | 19.75 KiB | |
| digilent_arty_a7_io.rpt | Jul 17, 2026, 2:13:12 AM | 96.81 KiB | |
| digilent_arty_a7_power.rpt | Jul 17, 2026, 2:13:53 AM | 8.85 KiB | |
| digilent_arty_a7_route_status.rpt | Jul 17, 2026, 2:13:50 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Jul 17, 2026, 2:13:52 AM | 22.74 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Jul 17, 2026, 2:13:12 AM | 5.05 KiB | |
| digilent_arty_a7_utilization_place.rpt | Jul 17, 2026, 2:13:12 AM | 10.87 KiB | |
| LICENSE | Jul 17, 2026, 2:09:17 AM | 11.09 KiB | |
| processor_ci_defines.vh | Jul 17, 2026, 2:11:34 AM | 300 B | |
| README.md | Jul 17, 2026, 2:09:17 AM | 1.24 KiB | |
| rpu_core_diagram.png | Jul 17, 2026, 2:09:17 AM | 87.03 KiB | |
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