DE2-115 FPGA Board Configuration



Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
CLOCK_50 Y2 input 3.3-V LVTTL
CLOCK2_50 AG14 input 3.3-V LVTTL
CLOCK3_50 AG15 input 3.3-V LVTTL



Sma
Name Location Direction Standard
SMA_CLKIN AH14 input 3.3-V LVTTL
SMA_CLKOUT AE23 output 3.3-V LVTTL



LED
Name Location Direction Standard
LEDR[0] G19 output 2.5 V
LEDR[1] F19 output 2.5 V
LEDR[2] E19 output 2.5 V
LEDR[3] F21 output 2.5 V
LEDR[4] F18 output 2.5 V
LEDR[5] E18 output 2.5 V
LEDR[6] J19 output 2.5 V
LEDR[7] H19 output 2.5 V
LEDR[8] J17 output 2.5 V
LEDR[9] G17 output 2.5 V
LEDR[10] J15 output 2.5 V
LEDR[11] H16 output 2.5 V
LEDR[12] J16 output 2.5 V
LEDR[13] H17 output 2.5 V
LEDR[14] F15 output 2.5 V
LEDR[15] G15 output 2.5 V
LEDR[16] G16 output 2.5 V
LEDR[17] H15 output 2.5 V
LEDG[0] E21 output 2.5 V
LEDG[1] E22 output 2.5 V
LEDG[2] E25 output 2.5 V
LEDG[3] E24 output 2.5 V
LEDG[4] H21 output 2.5 V
LEDG[5] G20 output 2.5 V
LEDG[6] G22 output 2.5 V
LEDG[7] G21 output 2.5 V
LEDG[8] F17 output 2.5 V



KEY
Name Location Direction Standard
KEY[0] M23 input 3.3-V LVTTL
KEY[1] M21 input 3.3-V LVTTL
KEY[2] N21 input 3.3-V LVTTL
KEY[3] R24 input 3.3-V LVTTL



EX_IO
Name Location Direction Standard
EX_IO[0] J10 inout 3.3-V LVTTL
EX_IO[1] J14 inout 3.3-V LVTTL
EX_IO[2] H13 inout 3.3-V LVTTL
EX_IO[3] H14 inout 3.3-V LVTTL
EX_IO[4] F14 inout 3.3-V LVTTL
EX_IO[5] E10 inout 3.3-V LVTTL
EX_IO[6] D9 inout 3.3-V LVTTL



SW
Name Location Direction Standard
SW[0] AB28 input 3.3-V LVTTL
SW[1] AC28 input 3.3-V LVTTL
SW[2] AC27 input 3.3-V LVTTL
SW[3] AD27 input 3.3-V LVTTL
SW[4] AB27 input 3.3-V LVTTL
SW[5] AC26 input 3.3-V LVTTL
SW[6] AD26 input 3.3-V LVTTL
SW[7] AB26 input 3.3-V LVTTL
SW[8] AC25 input 3.3-V LVTTL
SW[9] AB25 input 3.3-V LVTTL
SW[10] AC24 input 3.3-V LVTTL
SW[11] AB24 input 3.3-V LVTTL
SW[12] AB23 input 3.3-V LVTTL
SW[13] AA24 input 3.3-V LVTTL
SW[14] AA23 input 3.3-V LVTTL
SW[15] AA22 input 3.3-V LVTTL
SW[16] Y24 input 3.3-V LVTTL
SW[17] Y23 input 3.3-V LVTTL



SEG7
Name Location Direction Standard
HEX0[0] G18 output 2.5 V
HEX0[1] F22 output 2.5 V
HEX0[2] E17 output 2.5 V
HEX0[3] L26 output 3.3-V LVTTL
HEX0[4] L25 output 3.3-V LVTTL
HEX0[5] J22 output 3.3-V LVTTL
HEX0[6] H22 output 3.3-V LVTTL
HEX1[0] M24 output 3.3-V LVTTL
HEX1[1] Y22 output 3.3-V LVTTL
HEX1[2] W21 output 3.3-V LVTTL
HEX1[3] W22 output 3.3-V LVTTL
HEX1[4] W25 output 3.3-V LVTTL
HEX1[5] U23 output 3.3-V LVTTL
HEX1[6] U24 output 3.3-V LVTTL
HEX2[0] AA25 output 3.3-V LVTTL
HEX2[1] AA26 output 3.3-V LVTTL
HEX2[2] Y25 output 3.3-V LVTTL
HEX2[3] W26 output 3.3-V LVTTL
HEX2[4] Y26 output 3.3-V LVTTL
HEX2[5] W27 output 3.3-V LVTTL
HEX2[6] W28 output 3.3-V LVTTL
HEX3[0] V21 output 3.3-V LVTTL
HEX3[1] U21 output 3.3-V LVTTL
HEX3[2] AB20 output 3.3-V LVTTL
HEX3[3] AA21 output 3.3-V LVTTL
HEX3[4] AD24 output 3.3-V LVTTL
HEX3[5] AF23 output 3.3-V LVTTL
HEX3[6] Y19 output 3.3-V LVTTL
HEX4[0] AB19 output 3.3-V LVTTL
HEX4[1] AA19 output 3.3-V LVTTL
HEX4[2] AG21 output 3.3-V LVTTL
HEX4[3] AH21 output 3.3-V LVTTL
HEX4[4] AE19 output 3.3-V LVTTL
HEX4[5] AF19 output 3.3-V LVTTL
HEX4[6] AE18 output 3.3-V LVTTL
HEX5[0] AD18 output 3.3-V LVTTL
HEX5[1] AC18 output 3.3-V LVTTL
HEX5[2] AB18 output 3.3-V LVTTL
HEX5[3] AH19 output 3.3-V LVTTL
HEX5[4] AG19 output 3.3-V LVTTL
HEX5[5] AF18 output 3.3-V LVTTL
HEX5[6] AH18 output 3.3-V LVTTL
HEX6[0] AA17 output 3.3-V LVTTL
HEX6[1] AB16 output 3.3-V LVTTL
HEX6[2] AA16 output 3.3-V LVTTL
HEX6[3] AB17 output 3.3-V LVTTL
HEX6[4] AB15 output 3.3-V LVTTL
HEX6[5] AA15 output 3.3-V LVTTL
HEX6[6] AC17 output 3.3-V LVTTL
HEX7[0] AD17 output 3.3-V LVTTL
HEX7[1] AE17 output 3.3-V LVTTL
HEX7[2] AG17 output 3.3-V LVTTL
HEX7[3] AH17 output 3.3-V LVTTL
HEX7[4] AF17 output 3.3-V LVTTL
HEX7[5] AG18 output 3.3-V LVTTL
HEX7[6] AA14 output 3.3-V LVTTL



LCD
Name Location Direction Standard
LCD_DATA[0] L3 inout 3.3-V LVTTL
LCD_DATA[1] L1 inout 3.3-V LVTTL
LCD_DATA[2] L2 inout 3.3-V LVTTL
LCD_DATA[3] K7 inout 3.3-V LVTTL
LCD_DATA[4] K1 inout 3.3-V LVTTL
LCD_DATA[5] K2 inout 3.3-V LVTTL
LCD_DATA[6] M3 inout 3.3-V LVTTL
LCD_DATA[7] M5 inout 3.3-V LVTTL
LCD_BLON L6 output 3.3-V LVTTL
LCD_RW M1 output 3.3-V LVTTL
LCD_EN L4 output 3.3-V LVTTL
LCD_RS M2 output 3.3-V LVTTL
LCD_ON L5 output 3.3-V LVTTL



RS232
Name Location Direction Standard
UART_TXD G9 output 3.3-V LVTTL
UART_RXD G12 input 3.3-V LVTTL
UART_RTS G14 output 3.3-V LVTTL
UART_CTS J13 input 3.3-V LVTTL



PS2 for Keyboard and Mouse
Name Location Direction Standard
PS2_CLK G6 inout 3.3-V LVTTL
PS2_DAT H5 inout 3.3-V LVTTL
PS2_CLK2 G5 inout 3.3-V LVTTL
PS2_DAT2 F5 inout 3.3-V LVTTL



SDCARD
Name Location Direction Standard
SD_CMD AD14 inout 3.3-V LVTTL
SD_CLK AE13 output 3.3-V LVTTL
SD_WP_N AF14 input 3.3-V LVTTL
SD_DAT[0] AE14 inout 3.3-V LVTTL
SD_DAT[1] AF13 inout 3.3-V LVTTL
SD_DAT[2] AB14 inout 3.3-V LVTTL
SD_DAT[3] AC14 inout 3.3-V LVTTL



VGA
Name Location Direction Standard
VGA_HS G13 output 3.3-V LVTTL
VGA_VS C13 output 3.3-V LVTTL
VGA_SYNC_N C10 output 3.3-V LVTTL
VGA_CLK A12 output 3.3-V LVTTL
VGA_BLANK_N F11 output 3.3-V LVTTL
VGA_R[0] E12 output 3.3-V LVTTL
VGA_R[1] E11 output 3.3-V LVTTL
VGA_R[2] D10 output 3.3-V LVTTL
VGA_R[3] F12 output 3.3-V LVTTL
VGA_R[4] G10 output 3.3-V LVTTL
VGA_R[5] J12 output 3.3-V LVTTL
VGA_R[6] H8 output 3.3-V LVTTL
VGA_R[7] H10 output 3.3-V LVTTL
VGA_G[0] G8 output 3.3-V LVTTL
VGA_G[1] G11 output 3.3-V LVTTL
VGA_G[2] F8 output 3.3-V LVTTL
VGA_G[3] H12 output 3.3-V LVTTL
VGA_G[4] C8 output 3.3-V LVTTL
VGA_G[5] B8 output 3.3-V LVTTL
VGA_G[6] F10 output 3.3-V LVTTL
VGA_G[7] C9 output 3.3-V LVTTL
VGA_B[0] B10 output 3.3-V LVTTL
VGA_B[1] A10 output 3.3-V LVTTL
VGA_B[2] C11 output 3.3-V LVTTL
VGA_B[3] B11 output 3.3-V LVTTL
VGA_B[4] A11 output 3.3-V LVTTL
VGA_B[5] C12 output 3.3-V LVTTL
VGA_B[6] D11 output 3.3-V LVTTL
VGA_B[7] D12 output 3.3-V LVTTL



Audio
Name Location Direction Standard
AUD_ADCLRCK C2 inout 3.3-V LVTTL
AUD_ADCDAT D2 input 3.3-V LVTTL
AUD_DACLRCK E3 inout 3.3-V LVTTL
AUD_DACDAT D1 output 3.3-V LVTTL
AUD_XCK E1 output 3.3-V LVTTL
AUD_BCLK F2 inout 3.3-V LVTTL



I2C for EEPROM
Name Location Direction Standard
EEP_I2C_SCLK D14 output 3.3-V LVTTL
EEP_I2C_SDAT E14 inout 3.3-V LVTTL



I2C for Audio Tv-Decoder
Name Location Direction Standard
I2C_SCLK B7 output 3.3-V LVTTL
I2C_SDAT A8 inout 3.3-V LVTTL



Ethernet 0
Name Location Direction Standard
ENETCLK_25 A14 input 3.3-V LVTTL
ENET0_TX_DATA[0] C18 output 2.5 V
ENET0_RX_DATA[0] C16 input 2.5 V
ENET0_TX_DATA[1] D19 output 2.5 V
ENET0_RX_DATA[1] D16 input 2.5 V
ENET0_TX_DATA[2] A19 output 2.5 V
ENET0_RX_DATA[2] D17 input 2.5 V
ENET0_TX_DATA[3] B19 output 2.5 V
ENET0_RX_DATA[3] C15 input 2.5 V
ENET0_GTX_CLK A17 output 2.5 V
ENET0_TX_EN A18 output 2.5 V
ENET0_TX_ER B18 output 2.5 V
ENET0_INT_N A21 input 2.5 V
ENET0_RST_N C19 output 2.5 V
ENET0_RX_DV C17 input 2.5 V
ENET0_RX_ER D18 input 2.5 V
ENET0_RX_CRS D15 input 2.5 V
ENET0_RX_COL E15 input 2.5 V
ENET0_RX_CLK A15 input 2.5 V
ENET0_TX_CLK B17 input 2.5 V
ENET0_MDC C20 output 2.5 V
ENET0_MDIO B21 inout 2.5 V
ENET0_LINK100 C14 input 3.3-V LVTTL



Ethernet 1
Name Location Direction Standard
ENET1_TX_DATA[0] C25 output 2.5 V
ENET1_RX_DATA[0] B23 input 2.5 V
ENET1_TX_DATA[1] A26 output 2.5 V
ENET1_RX_DATA[1] C21 input 2.5 V
ENET1_TX_DATA[2] B26 output 2.5 V
ENET1_RX_DATA[2] A23 input 2.5 V
ENET1_TX_DATA[3] C26 output 2.5 V
ENET1_RX_DATA[3] D21 input 2.5 V
ENET1_GTX_CLK C23 output 2.5 V
ENET1_TX_EN B25 output 2.5 V
ENET1_TX_ER A25 output 2.5 V
ENET1_INT_N D24 input 2.5 V
ENET1_RST_N D22 output 2.5 V
ENET1_RX_DV A22 input 2.5 V
ENET1_RX_ER C24 input 2.5 V
ENET1_RX_CRS D20 input 2.5 V
ENET1_RX_COL B22 input 2.5 V
ENET1_RX_CLK B15 input 2.5 V
ENET1_TX_CLK C22 input 2.5 V
ENET1_MDC D23 output 2.5 V
ENET1_MDIO D25 inout 2.5 V
ENET1_LINK100 D13 input 3.3-V LVTTL



TV Decoder
Name Location Direction Standard
TD_HS E5 input 3.3-V LVTTL
TD_VS E4 input 3.3-V LVTTL
TD_CLK27 B14 input 3.3-V LVTTL
TD_RESET_N G7 output 3.3-V LVTTL
TD_DATA[0] E8 input 3.3-V LVTTL
TD_DATA[1] A7 input 3.3-V LVTTL
TD_DATA[2] D8 input 3.3-V LVTTL
TD_DATA[3] C7 input 3.3-V LVTTL
TD_DATA[4] D7 input 3.3-V LVTTL
TD_DATA[5] D6 input 3.3-V LVTTL
TD_DATA[6] E7 input 3.3-V LVTTL
TD_DATA[7] F7 input 3.3-V LVTTL



USB 2.0 OTG (Cypress CY7C67200)
Name Location Direction Standard
OTG_DATA[0] J6 inout 3.3-V LVTTL
OTG_DATA[1] K4 inout 3.3-V LVTTL
OTG_DATA[2] J5 inout 3.3-V LVTTL
OTG_DATA[3] K3 inout 3.3-V LVTTL
OTG_DATA[4] J4 inout 3.3-V LVTTL
OTG_DATA[5] J3 inout 3.3-V LVTTL
OTG_DATA[6] J7 inout 3.3-V LVTTL
OTG_DATA[7] H6 inout 3.3-V LVTTL
OTG_DATA[8] H3 inout 3.3-V LVTTL
OTG_DATA[9] H4 inout 3.3-V LVTTL
OTG_DATA[10] G1 inout 3.3-V LVTTL
OTG_DATA[11] G2 inout 3.3-V LVTTL
OTG_DATA[12] G3 inout 3.3-V LVTTL
OTG_DATA[13] F1 inout 3.3-V LVTTL
OTG_DATA[14] F3 inout 3.3-V LVTTL
OTG_DATA[15] G4 inout 3.3-V LVTTL
OTG_ADDR[0] H7 output 3.3-V LVTTL
OTG_ADDR[1] C3 output 3.3-V LVTTL
OTG_INT D5 input 3.3-V LVTTL
OTG_RST_N C5 output 3.3-V LVTTL
OTG_CS_N A3 output 3.3-V LVTTL
OTG_RD_N B3 output 3.3-V LVTTL
OTG_WE_N A4 output 3.3-V LVTTL



IR Receiver
Name Location Direction Standard
IRDA_RXD Y15 input 3.3-V LVTTL



SDRAM
Name Location Direction Standard
DRAM_BA[0] U7 output 3.3-V LVTTL
DRAM_BA[1] R4 output 3.3-V LVTTL
DRAM_DQM[0] U2 output 3.3-V LVTTL
DRAM_DQM[1] W4 output 3.3-V LVTTL
DRAM_DQM[2] K8 output 3.3-V LVTTL
DRAM_DQM[3] N8 output 3.3-V LVTTL
DRAM_RAS_N U6 output 3.3-V LVTTL
DRAM_CAS_N V7 output 3.3-V LVTTL
DRAM_CKE AA6 output 3.3-V LVTTL
DRAM_CLK AE5 output 3.3-V LVTTL
DRAM_WE_N V6 output 3.3-V LVTTL
DRAM_CS_N T4 output 3.3-V LVTTL
DRAM_DQ[0] W3 inout 3.3-V LVTTL
DRAM_DQ[1] W2 inout 3.3-V LVTTL
DRAM_DQ[2] V4 inout 3.3-V LVTTL
DRAM_DQ[3] W1 inout 3.3-V LVTTL
DRAM_DQ[4] V3 inout 3.3-V LVTTL
DRAM_DQ[5] V2 inout 3.3-V LVTTL
DRAM_DQ[6] V1 inout 3.3-V LVTTL
DRAM_DQ[7] U3 inout 3.3-V LVTTL
DRAM_DQ[8] Y3 inout 3.3-V LVTTL
DRAM_DQ[9] Y4 inout 3.3-V LVTTL
DRAM_DQ[10] AB1 inout 3.3-V LVTTL
DRAM_DQ[11] AA3 inout 3.3-V LVTTL
DRAM_DQ[12] AB2 inout 3.3-V LVTTL
DRAM_DQ[13] AC1 inout 3.3-V LVTTL
DRAM_DQ[14] AB3 inout 3.3-V LVTTL
DRAM_DQ[15] AC2 inout 3.3-V LVTTL
DRAM_DQ[16] M8 inout 3.3-V LVTTL
DRAM_DQ[17] L8 inout 3.3-V LVTTL
DRAM_DQ[18] P2 inout 3.3-V LVTTL
DRAM_DQ[19] N3 inout 3.3-V LVTTL
DRAM_DQ[20] N4 inout 3.3-V LVTTL
DRAM_DQ[21] M4 inout 3.3-V LVTTL
DRAM_DQ[22] M7 inout 3.3-V LVTTL
DRAM_DQ[23] L7 inout 3.3-V LVTTL
DRAM_DQ[24] U5 inout 3.3-V LVTTL
DRAM_DQ[25] R7 inout 3.3-V LVTTL
DRAM_DQ[26] R1 inout 3.3-V LVTTL
DRAM_DQ[27] R2 inout 3.3-V LVTTL
DRAM_DQ[28] R3 inout 3.3-V LVTTL
DRAM_DQ[29] T3 inout 3.3-V LVTTL
DRAM_DQ[30] U4 inout 3.3-V LVTTL
DRAM_DQ[31] U1 inout 3.3-V LVTTL
DRAM_ADDR[0] R6 output 3.3-V LVTTL
DRAM_ADDR[1] V8 output 3.3-V LVTTL
DRAM_ADDR[2] U8 output 3.3-V LVTTL
DRAM_ADDR[3] P1 output 3.3-V LVTTL
DRAM_ADDR[4] V5 output 3.3-V LVTTL
DRAM_ADDR[5] W8 output 3.3-V LVTTL
DRAM_ADDR[6] W7 output 3.3-V LVTTL
DRAM_ADDR[7] AA7 output 3.3-V LVTTL
DRAM_ADDR[8] Y5 output 3.3-V LVTTL
DRAM_ADDR[9] Y6 output 3.3-V LVTTL
DRAM_ADDR[10] R5 output 3.3-V LVTTL
DRAM_ADDR[11] AA5 output 3.3-V LVTTL
DRAM_ADDR[12] Y7 output 3.3-V LVTTL



SRAM
Name Location Direction Standard
SRAM_ADDR[0] AB7 output 3.3-V LVTTL
SRAM_ADDR[1] AD7 output 3.3-V LVTTL
SRAM_ADDR[2] AE7 output 3.3-V LVTTL
SRAM_ADDR[3] AC7 output 3.3-V LVTTL
SRAM_ADDR[4] AB6 output 3.3-V LVTTL
SRAM_ADDR[5] AE6 output 3.3-V LVTTL
SRAM_ADDR[6] AB5 output 3.3-V LVTTL
SRAM_ADDR[7] AC5 output 3.3-V LVTTL
SRAM_ADDR[8] AF5 output 3.3-V LVTTL
SRAM_ADDR[9] T7 output 3.3-V LVTTL
SRAM_ADDR[10] AF2 output 3.3-V LVTTL
SRAM_ADDR[11] AD3 output 3.3-V LVTTL
SRAM_ADDR[12] AB4 output 3.3-V LVTTL
SRAM_ADDR[13] AC3 output 3.3-V LVTTL
SRAM_ADDR[14] AA4 output 3.3-V LVTTL
SRAM_ADDR[15] AB11 output 3.3-V LVTTL
SRAM_ADDR[16] AC11 output 3.3-V LVTTL
SRAM_ADDR[17] AB9 output 3.3-V LVTTL
SRAM_ADDR[18] AB8 output 3.3-V LVTTL
SRAM_ADDR[19] T8 output 3.3-V LVTTL
SRAM_DQ[0] AH3 inout 3.3-V LVTTL
SRAM_DQ[1] AF4 inout 3.3-V LVTTL
SRAM_DQ[2] AG4 inout 3.3-V LVTTL
SRAM_DQ[3] AH4 inout 3.3-V LVTTL
SRAM_DQ[4] AF6 inout 3.3-V LVTTL
SRAM_DQ[5] AG6 inout 3.3-V LVTTL
SRAM_DQ[6] AH6 inout 3.3-V LVTTL
SRAM_DQ[7] AF7 inout 3.3-V LVTTL
SRAM_DQ[8] AD1 inout 3.3-V LVTTL
SRAM_DQ[9] AD2 inout 3.3-V LVTTL
SRAM_DQ[10] AE2 inout 3.3-V LVTTL
SRAM_DQ[11] AE1 inout 3.3-V LVTTL
SRAM_DQ[12] AE3 inout 3.3-V LVTTL
SRAM_DQ[13] AE4 inout 3.3-V LVTTL
SRAM_DQ[14] AF3 inout 3.3-V LVTTL
SRAM_DQ[15] AG3 inout 3.3-V LVTTL
SRAM_UB_N AC4 output 3.3-V LVTTL
SRAM_LB_N AD4 output 3.3-V LVTTL
SRAM_CE_N AF8 output 3.3-V LVTTL
SRAM_OE_N AD5 output 3.3-V LVTTL
SRAM_WE_N AE8 output 3.3-V LVTTL



Flash
Name Location Direction Standard
FL_ADDR[0] AG12 output 3.3-V LVTTL
FL_ADDR[1] AH7 output 3.3-V LVTTL
FL_ADDR[2] Y13 output 3.3-V LVTTL
FL_ADDR[3] Y14 output 3.3-V LVTTL
FL_ADDR[4] Y12 output 3.3-V LVTTL
FL_ADDR[5] AA13 output 3.3-V LVTTL
FL_ADDR[6] AA12 output 3.3-V LVTTL
FL_ADDR[7] AB13 output 3.3-V LVTTL
FL_ADDR[8] AB12 output 3.3-V LVTTL
FL_ADDR[9] AB10 output 3.3-V LVTTL
FL_ADDR[10] AE9 output 3.3-V LVTTL
FL_ADDR[11] AF9 output 3.3-V LVTTL
FL_ADDR[12] AA10 output 3.3-V LVTTL
FL_ADDR[13] AD8 output 3.3-V LVTTL
FL_ADDR[14] AC8 output 3.3-V LVTTL
FL_ADDR[15] Y10 output 3.3-V LVTTL
FL_ADDR[16] AA8 output 3.3-V LVTTL
FL_ADDR[17] AH12 output 3.3-V LVTTL
FL_ADDR[18] AC12 output 3.3-V LVTTL
FL_ADDR[19] AD12 output 3.3-V LVTTL
FL_ADDR[20] AE10 output 3.3-V LVTTL
FL_ADDR[21] AD10 output 3.3-V LVTTL
FL_ADDR[22] AD11 output 3.3-V LVTTL
FL_DQ[0] AH8 inout 3.3-V LVTTL
FL_DQ[1] AF10 inout 3.3-V LVTTL
FL_DQ[2] AG10 inout 3.3-V LVTTL
FL_DQ[3] AH10 inout 3.3-V LVTTL
FL_DQ[4] AF11 inout 3.3-V LVTTL
FL_DQ[5] AG11 inout 3.3-V LVTTL
FL_DQ[6] AH11 inout 3.3-V LVTTL
FL_DQ[7] AF12 inout 3.3-V LVTTL
FL_CE_N AG7 output 3.3-V LVTTL
FL_OE_N AG8 output 3.3-V LVTTL
FL_RST_N AE11 output 3.3-V LVTTL
FL_RY Y1 input 3.3-V LVTTL
FL_WE_N AC10 output 3.3-V LVTTL
FL_WP_N AE12 output 3.3-V LVTTL



GPIO connect to GPIO Default
Name Location Direction Standard GPIO Pin Index
GPIO[0] AB22 inout 3.3-V LVTTL 1
GPIO[1] AC15 inout 3.3-V LVTTL 2
GPIO[2] AB21 inout 3.3-V LVTTL 3
GPIO[3] Y17 inout 3.3-V LVTTL 4
GPIO[4] AC21 inout 3.3-V LVTTL 5
GPIO[5] Y16 inout 3.3-V LVTTL 6
GPIO[6] AD21 inout 3.3-V LVTTL 7
GPIO[7] AE16 inout 3.3-V LVTTL 8
GPIO[8] AD15 inout 3.3-V LVTTL 9
GPIO[9] AE15 inout 3.3-V LVTTL 10
GPIO[10] AC19 inout 3.3-V LVTTL 13
GPIO[11] AF16 inout 3.3-V LVTTL 14
GPIO[12] AD19 inout 3.3-V LVTTL 15
GPIO[13] AF15 inout 3.3-V LVTTL 16
GPIO[14] AF24 inout 3.3-V LVTTL 17
GPIO[15] AE21 inout 3.3-V LVTTL 18
GPIO[16] AF25 inout 3.3-V LVTTL 19
GPIO[17] AC22 inout 3.3-V LVTTL 20
GPIO[18] AE22 inout 3.3-V LVTTL 21
GPIO[19] AF21 inout 3.3-V LVTTL 22
GPIO[20] AF22 inout 3.3-V LVTTL 23
GPIO[21] AD22 inout 3.3-V LVTTL 24
GPIO[22] AG25 inout 3.3-V LVTTL 25
GPIO[23] AD25 inout 3.3-V LVTTL 26
GPIO[24] AH25 inout 3.3-V LVTTL 27
GPIO[25] AE25 inout 3.3-V LVTTL 28
GPIO[26] AG22 inout 3.3-V LVTTL 31
GPIO[27] AE24 inout 3.3-V LVTTL 32
GPIO[28] AH22 inout 3.3-V LVTTL 33
GPIO[29] AF26 inout 3.3-V LVTTL 34
GPIO[30] AE20 inout 3.3-V LVTTL 35
GPIO[31] AG23 inout 3.3-V LVTTL 36
GPIO[32] AF20 inout 3.3-V LVTTL 37
GPIO[33] AH26 inout 3.3-V LVTTL 38
GPIO[34] AH23 inout 3.3-V LVTTL 39
GPIO[35] AG26 inout 3.3-V LVTTL 40