Skip to content
[Jenkins]Jenkins
log in

Workspace

/ T03x /
.git
.Xil
klessydra-t0-3th
pics
build_digilent_arty_a7_100t.tclSep 12, 2026, 2:17:47 AM2.98 KiB
clockInfo.txtSep 12, 2026, 2:19:52 AM375 B
digilent_arty_a7_100t.bitSep 12, 2026, 2:21:31 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 12, 2026, 2:20:12 AM56.49 KiB
digilent_arty_a7_control_sets.rptSep 12, 2026, 2:20:11 AM78.78 KiB
digilent_arty_a7_drc.rptSep 12, 2026, 2:21:04 AM4.93 KiB
digilent_arty_a7_io.rptSep 12, 2026, 2:20:11 AM96.81 KiB
digilent_arty_a7_power.rptSep 12, 2026, 2:21:09 AM8.76 KiB
digilent_arty_a7_route_status.rptSep 12, 2026, 2:21:02 AM651 B
digilent_arty_a7_timing.rptSep 12, 2026, 2:21:06 AM74.41 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 12, 2026, 2:20:10 AM4.69 KiB
digilent_arty_a7_utilization_place.rptSep 12, 2026, 2:20:11 AM10.73 KiB
processor_ci_defines.vhSep 12, 2026, 2:17:47 AM300 B
README.mdSep 12, 2026, 2:17:15 AM1.37 KiB
src_files.ymlSep 12, 2026, 2:17:15 AM434 B