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build_digilent_arty_a7_100t.tclSep 12, 2026, 3:12:11 AM5.10 KiB
clockInfo.txtSep 12, 2026, 3:18:56 AM375 B
digilent_arty_a7_100t.bitSep 12, 2026, 3:20:09 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 12, 2026, 3:19:07 AM23.67 KiB
digilent_arty_a7_control_sets.rptSep 12, 2026, 3:19:06 AM33.64 KiB
digilent_arty_a7_drc.rptSep 12, 2026, 3:19:47 AM16.83 KiB
digilent_arty_a7_io.rptSep 12, 2026, 3:19:06 AM96.81 KiB
digilent_arty_a7_power.rptSep 12, 2026, 3:19:49 AM8.74 KiB
digilent_arty_a7_route_status.rptSep 12, 2026, 3:19:45 AM651 B
digilent_arty_a7_timing.rptSep 12, 2026, 3:19:48 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 12, 2026, 3:19:06 AM7.02 KiB
digilent_arty_a7_utilization_place.rptSep 12, 2026, 3:19:06 AM10.78 KiB
LICENSESep 12, 2026, 3:12:04 AM11.09 KiB
processor_ci_defines.vhSep 12, 2026, 3:12:11 AM300 B
README.mdSep 12, 2026, 3:12:04 AM6.30 KiB