read_verilog -sv /eda/processor_ci/rtl/cv32e40s.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffr.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffs.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alert.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alignment_buffer.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu_b_cpop.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_b_decoder.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_clic_int_controller.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_bypass.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_core.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_data_obi_interface.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_debug_triggers.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_decoder.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_div.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_dummy_instr.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ff_one.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_c_obi.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_stage.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_instr_obi_interface.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_int_controller.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lfsr.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lsu_response_filter.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_m_decoder.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mpu.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mult.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_check.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_target.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pma.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pmp.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_popcnt.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetch_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetcher.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_rchk_check.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_ecc.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_wrapper.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sequencer.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sleep_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wb_stage.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wpt.sv
read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_write_buffer.sv
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit