Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Mon Aug  3 00:31:48 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
| Design       : fpga_top
| Device       : xc7a100tcsg324-1
| Speed File   : -1
| Design State : Fully Placed
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Utilization Design Information

Table of Contents
-----------------
1. Utilization by Hierarchy

1. Utilization by Hierarchy
---------------------------

+-----------------------------------------------------------------------------------------+---------------------------------------------+------------+------------+---------+------+------+--------+--------+------------+
|                                         Instance                                        |                    Module                   | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs | RAMB36 | RAMB18 | DSP Blocks |
+-----------------------------------------------------------------------------------------+---------------------------------------------+------------+------------+---------+------+------+--------+--------+------------+
| fpga_top                                                                                |                                       (top) |       6706 |       5158 |    1548 |    0 | 3281 |      0 |      0 |          3 |
|   (fpga_top)                                                                            |                                       (top) |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|   ResetBootSystem                                                                       |                             ResetBootSystem |         14 |         14 |       0 |    0 |    9 |      0 |      0 |          0 |
|   ptop                                                                                  |                             processorci_top |       6691 |       5143 |    1548 |    0 | 3271 |      0 |      0 |          3 |
|     (ptop)                                                                              |                             processorci_top |          5 |          5 |       0 |    0 |   66 |      0 |      0 |          0 |
|     cv32e40s_core_i                                                                     |                               cv32e40s_core |       4340 |       4340 |       0 |    0 | 2488 |      0 |      0 |          3 |
|       controller_i                                                                      |                         cv32e40s_controller |        156 |        156 |       0 |    0 |   15 |      0 |      0 |          0 |
|         bypass_i                                                                        |                  cv32e40s_controller_bypass |          1 |          1 |       0 |    0 |    0 |      0 |      0 |          0 |
|         controller_fsm_i                                                                |                     cv32e40s_controller_fsm |        155 |        155 |       0 |    0 |   15 |      0 |      0 |          0 |
|       cs_registers_i                                                                    |                       cv32e40s_cs_registers |        174 |        174 |       0 |    0 |  445 |      0 |      0 |          0 |
|         (cs_registers_i)                                                                |                       cv32e40s_cs_registers |          0 |          0 |       0 |    0 |  130 |      0 |      0 |          0 |
|         basic_mode_csrs.mcause_csr_i                                                    |                                cv32e40s_csr |          9 |          9 |       0 |    0 |   13 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                     cv32e40s_clock_gate_162 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_163 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_164 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_165 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_166 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_167 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_168 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_169 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[5].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_170 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_171 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_172 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_173 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_174 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|         basic_mode_csrs.mie_csr_i                                                       |                cv32e40s_csr__parameterized1 |         15 |         15 |       0 |    0 |   20 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                     cv32e40s_clock_gate_142 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_143 |          3 |          3 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_144 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_145 |          3 |          3 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_146 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_147 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_148 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_149 |          3 |          3 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_150 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_151 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_152 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_153 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_154 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_155 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_156 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_157 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[30].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_158 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_159 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_160 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_161 |          3 |          3 |       0 |    0 |    1 |      0 |      0 |          0 |
|         basic_mode_csrs.mtvec_csr_i                                                     |                cv32e40s_csr__parameterized0 |          1 |          1 |       0 |    0 |   27 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                     cv32e40s_clock_gate_115 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg  |                           cv32e40s_sffs_116 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_117 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_118 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_119 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_120 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_121 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_122 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_123 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_124 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_125 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_126 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_127 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_128 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_129 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_130 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_131 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_132 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_133 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_134 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_135 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_136 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[30].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_137 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_138 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_139 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_140 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_141 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         debug_triggers_i                                                                |                     cv32e40s_debug_triggers |         97 |         97 |       0 |    0 |   46 |      0 |      0 |          0 |
|           gen_triggers.tmatch_csr[0].tdata1_csr_i                                       |                cv32e40s_csr__parameterized9 |         35 |         35 |       0 |    0 |   14 |      0 |      0 |          0 |
|           gen_triggers.tmatch_csr[0].tdata2_csr_i                                       |               cv32e40s_csr__parameterized10 |         62 |         62 |       0 |    0 |   32 |      0 |      0 |          0 |
|         jvt_csr_i                                                                       |                cv32e40s_csr__parameterized5 |         11 |         11 |       0 |    0 |   27 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                      cv32e40s_clock_gate_88 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_89 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_90 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_91 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_92 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_93 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_94 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_95 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_96 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_97 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_98 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_99 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_100 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_101 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_102 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_103 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_104 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_105 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_106 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_107 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_108 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[30].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_109 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                           cv32e40s_sffr_110 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_111 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_112 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_113 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                           cv32e40s_sffr_114 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         mepc_csr_i                                                                      |                cv32e40s_csr__parameterized6 |          4 |          4 |       0 |    0 |   32 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                      cv32e40s_clock_gate_56 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_57 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_58 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_59 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_60 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_61 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_62 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_63 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_64 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_65 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_66 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_67 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_68 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_69 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_70 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_71 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_72 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_73 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_74 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_75 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_76 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_77 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_78 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[30].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_79 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_80 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_81 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_82 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[5].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_83 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_84 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_85 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_86 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_87 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         mscratch_csr_i                                                                  |                cv32e40s_csr__parameterized7 |          0 |          0 |       0 |    0 |   33 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                      cv32e40s_clock_gate_23 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_24 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_25 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_26 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_27 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_28 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_29 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_30 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_31 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_32 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_33 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_34 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_35 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_36 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_37 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_38 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_39 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_40 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_41 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_42 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_43 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_44 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_45 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_46 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[30].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_47 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_48 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_49 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_50 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[5].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_51 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_52 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_53 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_54 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_55 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         mstateen0_csr_i                                                                 |                cv32e40s_csr__parameterized4 |          0 |          0 |       0 |    0 |    2 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                      cv32e40s_clock_gate_21 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_22 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         mstatus_csr_i                                                                   |                cv32e40s_csr__parameterized8 |          5 |          5 |       0 |    0 |    7 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                      cv32e40s_clock_gate_14 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv1.sffs_rdatareg |                            cv32e40s_sffs_15 |          2 |          2 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv1.sffs_rdatareg |                            cv32e40s_sffs_16 |          3 |          3 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_17 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                            cv32e40s_sffr_18 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_19 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                            cv32e40s_sffr_20 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         privlvl_user.priv_lvl_i                                                         |                cv32e40s_csr__parameterized3 |          0 |          0 |       0 |    0 |    3 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                      cv32e40s_clock_gate_11 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg  |                            cv32e40s_sffs_12 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv1.sffs_rdatareg  |                            cv32e40s_sffs_13 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         xsecure.cpuctrl_csr_i                                                           |                cv32e40s_csr__parameterized2 |          6 |          6 |       0 |    0 |   10 |      0 |      0 |          0 |
|           gen_hardened.core_clock_gate_i                                                |                       cv32e40s_clock_gate_3 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg  |                               cv32e40s_sffs |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                               cv32e40s_sffr |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                             cv32e40s_sffr_4 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                             cv32e40s_sffr_5 |          2 |          2 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg |                             cv32e40s_sffr_6 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                             cv32e40s_sffr_7 |          1 |          1 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg  |                             cv32e40s_sffr_8 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv1.sffs_rdatareg  |                             cv32e40s_sffs_9 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|           gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv1.sffs_rdatareg  |                            cv32e40s_sffs_10 |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|         xsecure.lfsr0_i                                                                 |                               cv32e40s_lfsr |         10 |         10 |       0 |    0 |   31 |      0 |      0 |          0 |
|         xsecure.lfsr1_i                                                                 |                             cv32e40s_lfsr_1 |          8 |          8 |       0 |    0 |   32 |      0 |      0 |          0 |
|         xsecure.lfsr2_i                                                                 |                             cv32e40s_lfsr_2 |          8 |          8 |       0 |    0 |   32 |      0 |      0 |          0 |
|       ex_stage_i                                                                        |                           cv32e40s_ex_stage |        761 |        761 |       0 |    0 |  286 |      0 |      0 |          3 |
|         (ex_stage_i)                                                                    |                           cv32e40s_ex_stage |        501 |        501 |       0 |    0 |  142 |      0 |      0 |          0 |
|         alu_i                                                                           |                                cv32e40s_alu |          0 |          0 |       0 |    0 |    0 |      0 |      0 |          0 |
|         div.div_i                                                                       |                                cv32e40s_div |        182 |        182 |       0 |    0 |  109 |      0 |      0 |          0 |
|         mul.mult_i                                                                      |                               cv32e40s_mult |         78 |         78 |       0 |    0 |   35 |      0 |      0 |          3 |
|       id_stage_i                                                                        |                           cv32e40s_id_stage |       1322 |       1322 |       0 |    0 |  276 |      0 |      0 |          0 |
|         (id_stage_i)                                                                    |                           cv32e40s_id_stage |       1320 |       1320 |       0 |    0 |  276 |      0 |      0 |          0 |
|         cv32e40s_pc_target_i                                                            |                          cv32e40s_pc_target |          2 |          2 |       0 |    0 |    0 |      0 |      0 |          0 |
|       if_stage_i                                                                        |                           cv32e40s_if_stage |       1218 |       1218 |       0 |    0 |  384 |      0 |      0 |          0 |
|         (if_stage_i)                                                                    |                           cv32e40s_if_stage |        426 |        426 |       0 |    0 |  119 |      0 |      0 |          0 |
|         gen_dummy_instr.dummy_instr_i                                                   |                        cv32e40s_dummy_instr |          7 |          7 |       0 |    0 |    7 |      0 |      0 |          0 |
|         gen_seq.sequencer_i                                                             |                          cv32e40s_sequencer |         41 |         41 |       0 |    0 |    7 |      0 |      0 |          0 |
|         instruction_obi_i                                                               |                cv32e40s_instr_obi_interface |         50 |         50 |       0 |    0 |   36 |      0 |      0 |          0 |
|           (instruction_obi_i)                                                           |                cv32e40s_instr_obi_interface |         46 |         46 |       0 |    0 |   31 |      0 |      0 |          0 |
|           secure.integrity_fifo_i                                                       |                 cv32e40s_obi_integrity_fifo |          4 |          4 |       0 |    0 |    5 |      0 |      0 |          0 |
|         mpu_i                                                                           |                                cv32e40s_mpu |          1 |          1 |       0 |    0 |    2 |      0 |      0 |          0 |
|         prefetch_unit_i                                                                 |                      cv32e40s_prefetch_unit |        696 |        696 |       0 |    0 |  213 |      0 |      0 |          0 |
|           alignment_buffer_i                                                            |                   cv32e40s_alignment_buffer |        648 |        648 |       0 |    0 |  178 |      0 |      0 |          0 |
|           prefetcher_i                                                                  |                         cv32e40s_prefetcher |         48 |         48 |       0 |    0 |   35 |      0 |      0 |          0 |
|       load_store_unit_i                                                                 |                    cv32e40s_load_store_unit |        173 |        173 |       0 |    0 |   51 |      0 |      0 |          0 |
|         (load_store_unit_i)                                                             |                    cv32e40s_load_store_unit |        137 |        137 |       0 |    0 |   35 |      0 |      0 |          0 |
|         data_obi_i                                                                      |                 cv32e40s_data_obi_interface |          5 |          5 |       0 |    0 |    5 |      0 |      0 |          0 |
|           secure.integrity_fifo_i                                                       | cv32e40s_obi_integrity_fifo__parameterized0 |          5 |          5 |       0 |    0 |    5 |      0 |      0 |          0 |
|         gen_wpt.wpt_i                                                                   |                                cv32e40s_wpt |          7 |          7 |       0 |    0 |    4 |      0 |      0 |          0 |
|         mpu_i                                                                           |                cv32e40s_mpu__parameterized0 |         21 |         21 |       0 |    0 |    3 |      0 |      0 |          0 |
|         response_filter_i                                                               |                cv32e40s_lsu_response_filter |          4 |          4 |       0 |    0 |    4 |      0 |      0 |          0 |
|       register_file_wrapper_i                                                           |              cv32e40s_register_file_wrapper |        551 |        551 |       0 |    0 | 1024 |      0 |      0 |          0 |
|         register_file_i                                                                 |                      cv32e40s_register_file |        551 |        551 |       0 |    0 | 1024 |      0 |      0 |          0 |
|       sleep_unit_i                                                                      |                         cv32e40s_sleep_unit |          7 |          7 |       0 |    0 |    3 |      0 |      0 |          0 |
|         (sleep_unit_i)                                                                  |                         cv32e40s_sleep_unit |          2 |          2 |       0 |    0 |    2 |      0 |      0 |          0 |
|         core_clock_gate_i                                                               |                         cv32e40s_clock_gate |          5 |          5 |       0 |    0 |    1 |      0 |      0 |          0 |
|       wb_stage_i                                                                        |                           cv32e40s_wb_stage |          3 |          3 |       0 |    0 |    4 |      0 |      0 |          0 |
|     u_Controller                                                                        |                                  Controller |       2349 |        801 |    1548 |    0 |  717 |      0 |      0 |          0 |
|       (u_Controller)                                                                    |                                  Controller |          0 |          0 |       0 |    0 |    1 |      0 |      0 |          0 |
|       ClkDivider                                                                        |                                  ClkDivider |         19 |         19 |       0 |    0 |   32 |      0 |      0 |          0 |
|       Core_Data_Memory                                                                  |                      Memory__parameterized0 |        544 |         32 |     512 |    0 |    0 |      0 |      0 |          0 |
|       Core_Memory                                                                       |                                      Memory |       1088 |         64 |    1024 |    0 |    0 |      0 |      0 |          0 |
|       Interpreter                                                                       |                                 Interpreter |        565 |        565 |       0 |    0 |  421 |      0 |      0 |          0 |
|       Uart                                                                              |                                        UART |        132 |        120 |      12 |    0 |  199 |      0 |      0 |          0 |
|         (Uart)                                                                          |                                        UART |         31 |         31 |       0 |    0 |  111 |      0 |      0 |          0 |
|         i_uart_rx                                                                       |                                     uart_rx |         27 |         27 |       0 |    0 |   35 |      0 |      0 |          0 |
|         i_uart_tx                                                                       |                                     uart_tx |         30 |         30 |       0 |    0 |   25 |      0 |      0 |          0 |
|         rx_fifo                                                                         |                                        FIFO |         25 |         19 |       6 |    0 |   14 |      0 |      0 |          0 |
|         tx_fifo                                                                         |                                      FIFO_0 |         20 |         14 |       6 |    0 |   14 |      0 |      0 |          0 |
|       timer                                                                             |                                       Timer |          1 |          1 |       0 |    0 |   64 |      0 |      0 |          0 |
+-----------------------------------------------------------------------------------------+---------------------------------------------+------------+------------+---------+------+------+--------+--------+------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining


