Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Mon Aug  3 00:32:32 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
| Design       : fpga_top
| Device       : 7a100t-csg324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
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Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (89217)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (24653)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (1)

1. checking no_clock (89217)
----------------------------
 There are 4840 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)

 There are 12 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 19 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 26 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 26 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 31 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mepc_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 32 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mscratch_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mstateen0_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 6 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 2 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 9 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 2485 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/clk_en_reg/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH)

 There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (24653)
----------------------------------------------------
 There are 24653 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (1)
----------------------------
 There is 1 combinational latch loop in the design through latch input (HIGH)



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      8.385        0.000                      0                    1        0.530        0.000                      0                    1        4.500        0.000                       0                     2  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)         Period(ns)      Frequency(MHz)
-----        ------------         ----------      --------------
sck          {0.000 50.000}       100.000         10.000          
sys_clk_pin  {0.000 5.000}        10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         8.385        0.000                      0                    1        0.530        0.000                      0                    1        4.500        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_pin
  To Clock:  sys_clk_pin

Setup :            0  Failing Endpoints,  Worst Slack        8.385ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.530ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             8.385ns  (required time - arrival time)
  Source:                 clk_o_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            clk_o_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.609ns  (logic 0.580ns (36.045%)  route 1.029ns (63.955%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.919ns = ( 14.919 - 10.000 ) 
    Source Clock Delay      (SCD):    5.220ns
    Clock Pessimism Removal (CPR):    0.301ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  clk_IBUF_inst/O
                         net (fo=1, routed)           2.025     3.506    clk_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096     3.602 r  clk_IBUF_BUFG_inst/O
                         net (fo=1, routed)           1.618     5.220    clk_IBUF_BUFG
    SLICE_X48Y103        FDRE                                         r  clk_o_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y103        FDRE (Prop_fdre_C_Q)         0.456     5.676 f  clk_o_reg/Q
                         net (fo=16, routed)          1.029     6.705    clk_o
    SLICE_X48Y103        LUT1 (Prop_lut1_I0_O)        0.124     6.829 r  clk_o_i_1/O
                         net (fo=1, routed)           0.000     6.829    p_0_in
    SLICE_X48Y103        FDRE                                         r  clk_o_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                     10.000    10.000 r  
    E3                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    E3                   IBUF (Prop_ibuf_I_O)         1.411    11.411 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.920    13.331    clk_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    13.422 r  clk_IBUF_BUFG_inst/O
                         net (fo=1, routed)           1.497    14.919    clk_IBUF_BUFG
    SLICE_X48Y103        FDRE                                         r  clk_o_reg/C
                         clock pessimism              0.301    15.220    
                         clock uncertainty           -0.035    15.185    
    SLICE_X48Y103        FDRE (Setup_fdre_C_D)        0.029    15.214    clk_o_reg
  -------------------------------------------------------------------
                         required time                         15.214    
                         arrival time                          -6.829    
  -------------------------------------------------------------------
                         slack                                  8.385    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.530ns  (arrival time - required time)
  Source:                 clk_o_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            clk_o_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.621ns  (logic 0.186ns (29.946%)  route 0.435ns (70.054%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.996ns
    Source Clock Delay      (SCD):    1.479ns
    Clock Pessimism Removal (CPR):    0.516ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.644     0.894    clk_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.920 r  clk_IBUF_BUFG_inst/O
                         net (fo=1, routed)           0.560     1.479    clk_IBUF_BUFG
    SLICE_X48Y103        FDRE                                         r  clk_o_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y103        FDRE (Prop_fdre_C_Q)         0.141     1.620 f  clk_o_reg/Q
                         net (fo=16, routed)          0.435     2.056    clk_o
    SLICE_X48Y103        LUT1 (Prop_lut1_I0_O)        0.045     2.101 r  clk_o_i_1/O
                         net (fo=1, routed)           0.000     2.101    p_0_in
    SLICE_X48Y103        FDRE                                         r  clk_o_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.699     1.136    clk_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.165 r  clk_IBUF_BUFG_inst/O
                         net (fo=1, routed)           0.831     1.996    clk_IBUF_BUFG
    SLICE_X48Y103        FDRE                                         r  clk_o_reg/C
                         clock pessimism             -0.516     1.479    
    SLICE_X48Y103        FDRE (Hold_fdre_C_D)         0.091     1.570    clk_o_reg
  -------------------------------------------------------------------
                         required time                         -1.570    
                         arrival time                           2.101    
  -------------------------------------------------------------------
                         slack                                  0.530    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sys_clk_pin
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clk }

Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I   n/a            2.155         10.000      7.845      BUFGCTRL_X0Y16  clk_IBUF_BUFG_inst/I
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X48Y103   clk_o_reg/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X48Y103   clk_o_reg/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X48Y103   clk_o_reg/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X48Y103   clk_o_reg/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X48Y103   clk_o_reg/C



------------------------------------------------------------------------------------------------
| Data sheet
| ----------
------------------------------------------------------------------------------------------------

Setup between Clocks

------------+-------------+---------------+---------+---------------+---------+---------------+---------+---------------+---------+
Source      | Destination |  Src:Rise     | Process |  Src:Rise     | Process |  Src:Fall     | Process |  Src:Fall     | Process |
Clock       | Clock       | Dest:Rise(ns) | Corner  | Dest:Fall(ns) | Corner  | Dest:Rise(ns) | Corner  | Dest:Fall(ns) | Corner  |
------------+-------------+---------------+---------+---------------+---------+---------------+---------+---------------+---------+
sys_clk_pin | sys_clk_pin |         1.615 | SLOW    |               |         |               |         |               |         |
------------+-------------+---------------+---------+---------------+---------+---------------+---------+---------------+---------+



