[[Sscofpmf]]
== "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0

The current Privileged specification defines mhpmevent CSRs to select and
control event counting by the associated hpmcounter CSRs, but provides no
standardization of any fields within these CSRs. For at least Linux-class
rich-OS systems it is desirable to standardize certain basic features that are
broadly desired (and have come up over the past year plus on RISC-V lists, as
well as have been the subject of past proposals). This enables there to be
standard upstream software support that eliminates the need for implementations
to provide their own custom software support.

This extension serves to accomplish exactly this within the existing mhpmevent
CSRs (and correspondingly avoids the unnecessary creation of whole new sets of
CSRs - past just one new CSR).

This extension sticks to addressing two basic well-understood needs that have
been requested by various people. To make it easy to understand the deltas from
the current Priv 1.11/1.12 specs, this is written as the actual exact changes
to be made to existing paragraphs of Priv spec text (or additional paragraphs
within the existing text).

The extension name is "Sscofpmf" ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering).

Note that the new count overflow interrupt will be treated as a standard local
interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers.

=== Count Overflow Control

The following bits are added to `mhpmevent`:

[cols="^1,^1,^1,^1,^1,^1,^1,^1",stripes=even,options="header"]
|====
|63 |62 |61 |60 |59 |58 |57 |56
|OF |MINH |SINH |UINH |VSINH |VUINH |_WPRI_ |_WPRI_
|====

[cols="15%,85%",options="header"]
|====
| Field | Description
| OF | Overflow status and interrupt disable bit that is set when counter overflows
| MINH | If set, then counting of events in M-mode is inhibited
| SINH | If set, then counting of events in S/HS-mode is inhibited
| UINH | If set, then counting of events in U-mode is inhibited
| VSINH | If set, then counting of events in VS-mode is inhibited
| VUINH | If set, then counting of events in VU-mode is inhibited
| _WPRI_ | Reserved
| _WPRI_ | Reserved
|====

For each ``x``INH bit, if the associated privilege mode is not implemented,
the bit is read-only zero.

Each of the five ``x``INH bits, when set, inhibit counting of events while in
privilege mode ``x``. All-zeroes for these bits results in counting of events in
all modes.

The OF bit is set when the corresponding hpmcounter overflows, and remains set
until written by software. Since hpmcounter values are unsigned values,
overflow is defined as unsigned overflow of the implemented counter bits. Note
that there is no loss of information after an overflow since the counter wraps
around and keeps counting while the sticky OF bit remains set.

If supervisor mode is implemented, the 32-bit scountovf register contains
read-only shadow copies of the OF bits in all 32 mhpmevent registers.

If an hpmcounter overflows while the associated OF bit is zero, then a "count
overflow interrupt request" is generated. If the OF bit is one, then no
interrupt request is generated. Consequently the OF bit also functions as a
count overflow interrupt disable for the associated hpmcounter.

Count overflow never results from writes to the mhpmcounter__n__ or
mhpmevent__n__ registers, only from hardware increments of counter registers.

This count-overflow-interrupt-request signal is treated as a standard local
interrupt that corresponds to bit 13 in the `mip`/`mie`/`sip`/`sie` registers.
The `mip`/`sip` LCOFIP and `mie`/`sie` LCOFIE bits are, respectively, the
interrupt-pending and interrupt-enable bits for this interrupt.
('LCOFI' represents 'Local Count Overflow Interrupt'.)

Generation of a count-overflow-interrupt request by an `hpmcounter` sets the
associated OF bit.
When an OF bit is set, it eventually, but not necessarily immediately, sets
the LCOFIP bit in the `mip`/`sip` registers.
The LCOFIP bit is cleared by software before servicing the count overflow
interrupt resulting from one or more count overflows.
The `mideleg` register controls the delegation of this interrupt to S-mode
versus M-mode.

[NOTE]
====
There are not separate overflow status and overflow interrupt enable bits. In
practice, enabling overflow interrupt generation (by clearing the OF bit) is
done in conjunction with initializing the counter to a starting value. Once a
counter has overflowed, it and the OF bit must be reinitialized before another
overflow interrupt can be generated.
====

[NOTE]
====
Software can distinguish newly overflowed counters (yet to be serviced by an
overflow interrupt handler) from overflowed counters that have already been
serviced or that are configured to not generate an interrupt on overflow, by
maintaining a bit mask reflecting which counters are active and due to
eventually overflow.
====

=== Supervisor Count Overflow (`scountovf`) Register

This extension adds the `scountovf` CSR,
a 32-bit read-only register that contains shadow copies of
the OF bits in the 29 mhpmevent CSRs (mhpmevent__3__ - mhpmevent__31__) - where
scountovf bit _X_ corresponds to mhpmevent__X__.

This register enables supervisor-level overflow interrupt handler software to
quickly and easily determine which counter(s) have overflowed (without needing
to make an execution environment call or series of calls ultimately up to
M-mode).

Read access to bit _X_ is subject to the same mcounteren (or mcounteren and
hcounteren) CSRs that mediate access to the hpmcounter CSRs by S-mode (or
VS-mode). In M-mode, scountovf bit _X_ is always readable. In S/HS-mode, scountovf bit _X_ is readable when mcounteren bit
_X_ is set, and otherwise reads as zero. Similarly, in VS mode, scountovf bit
_X_ is readable when mcounteren bit _X_ and hcounteren bit _X_ are both set,
and otherwise reads as zero.
