# Copyright Google LLC
# Copyright 2021 Thales DIS Design Services SAS
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

- tool: vcs
  compile:
    cmd:
      - "vcs -file <cwd>/dv/vcs.compile.option.f
              +incdir+<setting>
              +incdir+<user_extension>
             -f <cwd>/dv/files.f -full64
             -l <out>/compile.log
             -LDFLAGS '-Wl,--no-as-needed'
             -Mdir=<out>/vcs_simv.csrc
             -o <out>/vcs_simv <cmp_opts> <cov_opts> "
    cov_opts: >
      -cm_dir <out>/test.vdb
  sim:
    cmd: >
      <out>/vcs_simv +vcs+lic+wait gen="true" <sim_opts> +ntb_random_seed=<seed> <cov_opts>
    cov_opts: >
      -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>_<test_id>

- tool: ius
  compile:
    cmd:
      - "irun -64bit -access +rwc -f <cwd>/dv/files.f
              +incdir+<setting>
              +incdir+<user_extension>
              -q -sv -uvm -vlog_ext +.vh -I.
              -uvmhome CDNS-1.2
              -elaborate
              -l <out>/compile.log <cmp_opts>"
  sim:
    cmd: >
      irun -R <sim_opts> -svseed <seed> -svrnc rand_struct

- tool: questa
  compile:
    cmd:
      - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
      - "vlog -64
        +incdir+<setting>
        +incdir+<user_extension>
        -access=rwc
        -f <cwd>/dv/files.f
        -sv
        -mfcu -cuname design_cuname
        +define+UVM_REGEX_NO_DPI
        -writetoplevels <out>/top.list
        -l <out>/compile.log <cmp_opts>"
      - "vopt -64 -debug
        +designfile -f <out>/top.list
        -l <out>/optimize.log <cmp_opts>
        -o design_opt"
  sim:
    cmd: >
      vsim -64 -c <cov_opts> -do <cwd>/dv/questa_sim.tcl design_opt <sim_opts>  -sv_seed <seed>
    cov_opts: >
      -do "coverage save -onexit <out>/cov.ucdb;"

- tool: dsim
  env_var: DSIM,DSIM_LIB_PATH
  compile:
    cmd:
      - "mkdir -p <out>/dsim"
      - "<DSIM> -sv -work <out>/dsim
                -genimage image
                +incdir+$UVM_HOME/src
                $UVM_HOME/src/uvm_pkg.sv
                +define+DSIM
                -suppress EnumMustBePositive
                +incdir+<setting>
                +incdir+<user_extension>
                -f <cwd>/dv/files.f
                -l <out>/dsim/compile.log <cmp_opts>"
  sim:
    cmd: >
      <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim

- tool: qrun
  compile:
    cmd:
      - "qrun -f <cwd>/dv/qrun_option.f
        +incdir+<setting>
        +incdir+<user_extension>
        -f <cwd>/dv/files.f <cmp_opts>
        -l <out>/qrun_compile_optimize.log
        -outdir <out>/qrun.out"
  sim:
    cmd: >
      qrun -64 -simulate -snapshot design_opt -c <cov_opts> <sim_opts> -sv_seed <seed> -outdir <out>/qrun.out
    cov_opts: >
      -coverage -ucdb <out>/cov.ucdb
