# Copyright Google LLC
# Copyright 2022 Thales DIS Design Services SAS
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

###### This file is based on <cwd>/cva6-simulator.yaml

- tool: xrun
  compile:
    cmd: 
      - "xrun -elaborate
              -messages
              -sv
              -uvm 
              -uvmhome CDNS-1.2
              -64
              +incdir+<setting>
              +incdir+<user_extension>
              -f <cwd>/../env/corev-dv/cva6-files.f
              +define+UVM_REGEX_NO_DPI
              -timescale 1ns/10ps
	      -status
	      -access +rwc
              -log <out>/compile.log  <cmp_opts> <cov_opts> "
    cov_opts: >
  sim:
    cmd: >
      xrun -R -messages -licqueue +gen="true" <sim_opts> -svseed <seed>  <cov_opts> 
      
    cov_opts: >

- tool: vcs
  compile:
    cmd:
      - "vcs -file <cwd>/dv/vcs.compile.option.f
              +incdir+<setting>
              +incdir+<user_extension>
             -f <cwd>/../env/corev-dv/cva6-files.f
             -full64
             -l <out>/compile.log
             -LDFLAGS '-Wl,--no-as-needed'
             -Mdir=<out>/vcs_simv.csrc
             -o <out>/vcs_simv <cmp_opts> <cov_opts> "
    cov_opts: >
      -cm_dir <out>/test.vdb
  sim:
    cmd: >
      <out>/vcs_simv +vcs+lic+wait gen="true" <sim_opts> +ntb_random_seed=<seed> <cov_opts>
    cov_opts: >
      -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>_<test_id>

- tool: questa
  compile:
    cmd:
      - "vlog -64
        +incdir+$QUESTASIM_HOME/verilog_src/uvm-1.2/src
        +incdir+<setting>
        +incdir+<user_extension>
        +acc
     	$QUESTASIM_HOME/verilog_src/uvm-1.2/src/uvm_pkg.sv
        -f <cwd>/../env/corev-dv/cva6-files.f
        -sv
        -mfcu -cuname design_cuname
        +define+UVM_REGEX_NO_DPI
        -writetoplevels <out>/top.list
        -l <out>/compile.log <cmp_opts>"
      - "vopt -64 -debug
        +designfile -f <out>/top.list
        -l <out>/optimize.log <cmp_opts>
        -o design_opt"
  sim:
    cmd: >
      vsim -64 -c <cov_opts> -do <cwd>/dv/questa_sim.tcl design_opt <sim_opts>  -sv_seed <seed> -sv_lib $QUESTASIM_HOME/uvm-1.2/linux_x86_64/uvm_dpi
    cov_opts: >
      -do "coverage save -onexit <out>/cov.ucdb;"

