load("@bazel-orfs//:openroad.bzl", "orfs_flow")

FASTER = {
    # ignore timing repair for now
    "SETUP_SLACK_MARGIN": "-1000",
    "SKIP_REPORT_METRICS": "1",
    "SKIP_LAST_GASP": "1",
    # skip checks for now, faster
    "PWR_NETS_VOLTAGES": "",
    "GND_NETS_VOLTAGES": "",
}

# SRAMs are specific to PDK, mock one here by
# creating it from flip flops and use mock_area
# to reduce the size of the SRAM to something that
# is a bit more reasonable.
orfs_flow(
    name = "darkram",
    abstract_stage = "cts",
    arguments = FASTER | {
        "CORE_UTILIZATION": "10",
        "SYNTH_MEMORY_MAX_BITS": "65536",
        "MACRO_BLOCKAGE_HALO": "0",
        "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl",
    },
    # The width/height of a real SRAM might be, say,
    # 25% of that of a flip flop based SRAM.
    mock_area = 0.25,
    sources = {
        "SDC_FILE": [":constraints_darkram.sdc"],
    },
    stage_data = {
        "synth": [
            "//:verilog_data",
            "//:verilog_include",
        ],
    },
    # OpenROAD version of the darkram.v file
    verilog_files = [":darkram.v"],
)

orfs_flow(
    name = "darksocv",
    arguments = FASTER | {
        "SYNTH_HIERARCHICAL": "1",
        #"SYNTH_MINIMUM_KEEP_SIZE": "1",
        "CORE_UTILIZATION": "40",
        "MIN_ROUTING_LAYER": "M2",
        "MAX_ROUTING_LAYER": "M7",
        "CORE_MARGIN": "2",
        "MACRO_PLACE_HALO": "2 2",
        "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl",
        "GDS_ALLOW_EMPTY": "darkram",
    },
    macros = ["darkram_generate_abstract"],
    sources = {
        "SDC_FILE": [":constraints.sdc"],
    },
    stage_data = {
        "synth": [
            "//:verilog_data",
            "//:verilog_include",
        ],
    },
    verilog_files = [
        "//:verilog",
    ],
)
