BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
#i5-v6.0
LOCATE COMP "XCLK" SITE "G2";
IOBUF  PORT "XCLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "XCLK" 25 MHZ;
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
# on PCB v1.7 shutdown is not connected to FPGA
LOCATE COMP "XRES" SITE "D6"; # FPGA receives
IOBUF  PORT "XRES" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "UART_TXD" SITE "L4"; # FPGA transmits to ftdi
IOBUF  PORT "UART_TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "UART_RXD" SITE "M1"; # FPGA received to ftdi
IOBUF  PORT "UART_RXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#
## upper
LOCATE COMP "LED[0]" SITE "D2";
LOCATE COMP "LED[1]" SITE "C1";
LOCATE COMP "LED[2]" SITE "C2";
LOCATE COMP "LED[3]" SITE "B2";

## bottom
LOCATE COMP "DEBUG[0]" SITE "D1";
LOCATE COMP "DEBUG[1]" SITE "E2";
LOCATE COMP "DEBUG[2]" SITE "E1";
LOCATE COMP "DEBUG[3]" SITE "H3";

# if you use spi bitbang, just remove PULLMODE=UP from property
IOBUF  PORT "LED[0]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "LED[1]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "LED[2]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "LED[3]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "DEBUG[0]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "DEBUG[1]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "DEBUG[2]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF  PORT "DEBUG[3]"  PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;


## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
# PCB v2.0.5 and higher
LOCATE COMP "user_programn" SITE "M4";
IOBUF  PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
# on PCB v1.7 shutdown is not connected to FPGA
LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
IOBUF  PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;

