Skip to content

Workspace

.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreSep 13, 2026, 4:36:36 AM216 B
book2pic.jpgSep 13, 2026, 4:36:36 AM69.45 KiB
bookpic.jpgSep 13, 2026, 4:36:36 AM71.73 KiB
build_digilent_arty_a7_100t.tclSep 13, 2026, 4:37:05 AM6.48 KiB
clockInfo.txtSep 13, 2026, 4:38:04 AM375 B
digilent_arty_a7_100t.bitSep 13, 2026, 4:38:59 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 13, 2026, 4:38:09 AM16.56 KiB
digilent_arty_a7_control_sets.rptSep 13, 2026, 4:38:08 AM12.95 KiB
digilent_arty_a7_drc.rptSep 13, 2026, 4:38:40 AM2.34 KiB
digilent_arty_a7_io.rptSep 13, 2026, 4:38:08 AM96.81 KiB
digilent_arty_a7_power.rptSep 13, 2026, 4:38:41 AM8.59 KiB
digilent_arty_a7_route_status.rptSep 13, 2026, 4:38:39 AM651 B
digilent_arty_a7_timing.rptSep 13, 2026, 4:38:41 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 13, 2026, 4:38:08 AM3.22 KiB
digilent_arty_a7_utilization_place.rptSep 13, 2026, 4:38:08 AM10.57 KiB
LICENSESep 13, 2026, 4:36:36 AM11.09 KiB
processor_ci_defines.vhSep 13, 2026, 4:37:05 AM300 B
README.mdSep 13, 2026, 4:36:36 AM8.75 KiB