Skip to content

Workspace

.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreJul 30, 2026, 4:34:00 AM216 B
book2pic.jpgJul 30, 2026, 4:34:01 AM69.45 KiB
bookpic.jpgJul 30, 2026, 4:34:01 AM71.73 KiB
build_digilent_arty_a7_100t.tclJul 30, 2026, 4:37:47 AM6.48 KiB
clockInfo.txtJul 30, 2026, 4:38:48 AM375 B
digilent_arty_a7_100t.bitJul 30, 2026, 4:39:45 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 30, 2026, 4:38:52 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 30, 2026, 4:38:52 AM12.95 KiB
digilent_arty_a7_drc.rptJul 30, 2026, 4:39:25 AM2.34 KiB
digilent_arty_a7_io.rptJul 30, 2026, 4:38:52 AM96.81 KiB
digilent_arty_a7_power.rptJul 30, 2026, 4:39:26 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 30, 2026, 4:39:24 AM651 B
digilent_arty_a7_timing.rptJul 30, 2026, 4:39:26 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 30, 2026, 4:38:52 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 30, 2026, 4:38:52 AM10.57 KiB
LICENSEJul 30, 2026, 4:34:00 AM11.09 KiB
processor_ci_defines.vhJul 30, 2026, 4:37:47 AM300 B
README.mdJul 30, 2026, 4:34:00 AM8.75 KiB