Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e200_opensource /
.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreJul 29, 2026, 4:37:31 AM216 B
book2pic.jpgJul 29, 2026, 4:37:32 AM69.45 KiB
bookpic.jpgJul 29, 2026, 4:37:32 AM71.73 KiB
build_digilent_arty_a7_100t.tclJul 29, 2026, 4:38:09 AM6.48 KiB
clockInfo.txtJul 29, 2026, 4:39:07 AM375 B
digilent_arty_a7_100t.bitJul 29, 2026, 4:40:03 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 29, 2026, 4:39:12 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 29, 2026, 4:39:11 AM12.95 KiB
digilent_arty_a7_drc.rptJul 29, 2026, 4:39:43 AM2.34 KiB
digilent_arty_a7_io.rptJul 29, 2026, 4:39:11 AM96.81 KiB
digilent_arty_a7_power.rptJul 29, 2026, 4:39:44 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 29, 2026, 4:39:42 AM651 B
digilent_arty_a7_timing.rptJul 29, 2026, 4:39:43 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 29, 2026, 4:39:11 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 29, 2026, 4:39:11 AM10.57 KiB
LICENSEJul 29, 2026, 4:37:31 AM11.09 KiB
processor_ci_defines.vhJul 29, 2026, 4:38:09 AM300 B
README.mdJul 29, 2026, 4:37:31 AM8.75 KiB