read_verilog -sv /eda/processor_ci/rtl/e203_hbirdv2.sv
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/config.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_biu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_clk_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_clkgate.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_core.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_cpu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_cpu_top.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_defines.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_dtcm_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_dtcm_ram.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_extend_csr.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_bjp.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_csrctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_dpath.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_lsuagu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_muldiv.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_alu_rglr.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_branchslv.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_commit.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_csr.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_decode.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_disp.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_excp.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_longpwbck.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_nice.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_oitf.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_regfile.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_exu_wbck.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_ifetch.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_ift2icb.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_litebpu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_ifu_minidec.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_irq_sync.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_itcm_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_itcm_ram.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_lsu.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_lsu_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_reset_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/e203_srams.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_1cyc_sram_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_bufs.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_dffs.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_icbs.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_ram.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_gnrl_xchecker.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_sim_ram.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/general/sirv_sram_icb_ctrl.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_clint.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_gfcm.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_main.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_mems.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_nice_core.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_perips.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_plic.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_pll.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_pllclkdiv.v
read_verilog /var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/subsys/e203_subsys_top.v
set_property include_dirs [list "/var/jenkins_home/workspace/e203_hbirdv2/e203_hbirdv2/rtl/e203/core/" ] [get_filesets sources_1]
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit