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.gitignoreAug 24, 2026, 3:18:07 AM46 B
build_digilent_arty_a7_100t.tclAug 24, 2026, 3:20:39 AM8.34 KiB
clockInfo.txtAug 24, 2026, 3:21:37 AM375 B
digilent_arty_a7_100t.bitAug 24, 2026, 3:22:33 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 24, 2026, 3:21:42 AM16.56 KiB
digilent_arty_a7_control_sets.rptAug 24, 2026, 3:21:42 AM12.95 KiB
digilent_arty_a7_drc.rptAug 24, 2026, 3:22:14 AM2.34 KiB
digilent_arty_a7_io.rptAug 24, 2026, 3:21:42 AM96.81 KiB
digilent_arty_a7_power.rptAug 24, 2026, 3:22:15 AM8.59 KiB
digilent_arty_a7_route_status.rptAug 24, 2026, 3:22:13 AM651 B
digilent_arty_a7_timing.rptAug 24, 2026, 3:22:14 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 24, 2026, 3:21:41 AM3.22 KiB
digilent_arty_a7_utilization_place.rptAug 24, 2026, 3:21:42 AM10.57 KiB
e203_core.coreAug 24, 2026, 3:18:08 AM2.49 KiB
e203_soc.coreAug 24, 2026, 3:18:08 AM4.26 KiB
LICENSEAug 24, 2026, 3:18:07 AM11.09 KiB
processor_ci_defines.vhAug 24, 2026, 3:20:39 AM300 B
README.mdAug 24, 2026, 3:18:07 AM4.58 KiB