Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e203_hbirdv2 /
.git
.github
.Xil
doc
fpga
pics
riscv-tools
rtl/e203
tb
vsim
.gitignoreJul 29, 2026, 3:18:07 AM46 B
build_digilent_arty_a7_100t.tclJul 29, 2026, 3:21:01 AM8.34 KiB
clockInfo.txtJul 29, 2026, 3:22:02 AM375 B
digilent_arty_a7_100t.bitJul 29, 2026, 3:23:04 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 29, 2026, 3:22:09 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 29, 2026, 3:22:09 AM12.95 KiB
digilent_arty_a7_drc.rptJul 29, 2026, 3:22:44 AM2.34 KiB
digilent_arty_a7_io.rptJul 29, 2026, 3:22:09 AM96.81 KiB
digilent_arty_a7_power.rptJul 29, 2026, 3:22:44 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 29, 2026, 3:22:42 AM651 B
digilent_arty_a7_timing.rptJul 29, 2026, 3:22:44 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 29, 2026, 3:22:08 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 29, 2026, 3:22:08 AM10.57 KiB
e203_core.coreJul 29, 2026, 3:18:08 AM2.49 KiB
e203_soc.coreJul 29, 2026, 3:18:08 AM4.26 KiB
LICENSEJul 29, 2026, 3:18:07 AM11.09 KiB
processor_ci_defines.vhJul 29, 2026, 3:21:01 AM300 B
README.mdJul 29, 2026, 3:18:07 AM4.58 KiB