
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Sun Aug  7 17:43:57 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/anku/work2/bmanip/32/dataset.yaml \
//                  --cgf /home/anku/work2/bmanip/32/rv32ib.yaml \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the binvi instruction of the RISC-V RV32Zbs extension for the binvi covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IZbs")

.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zbs.*);def TEST_CASE_1=True;",binvi)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd, rs1==x31, rd==x31, 
// opcode: binvi ; op1:x31; dest:x31; op1val:0xffffffff;  immval:0x2
TEST_IMM_OP( binvi, x31, x31, 0x00000000, 0xffffffff, 0x2, x1, 0, x2)

inst_1:
// rs1 != rd, rs1==x29, rd==x30, 
// opcode: binvi ; op1:x29; dest:x30; op1val:0x2dedb6a7;  immval:0x0
TEST_IMM_OP( binvi, x30, x29, 0x00000000, 0x2dedb6a7, 0x0, x1, 4, x2)

inst_2:
// rs1==x30, rd==x29, 
// opcode: binvi ; op1:x30; dest:x29; op1val:0x3c272728;  immval:0x10
TEST_IMM_OP( binvi, x29, x30, 0x00000000, 0x3c272728, 0x10, x1, 8, x2)

inst_3:
// rs1==x27, rd==x28, 
// opcode: binvi ; op1:x27; dest:x28; op1val:0x4f55c73d;  immval:0x18
TEST_IMM_OP( binvi, x28, x27, 0x00000000, 0x4f55c73d, 0x18, x1, 12, x2)

inst_4:
// rs1==x28, rd==x27, 
// opcode: binvi ; op1:x28; dest:x27; op1val:0xb0ab577a;  immval:0x14
TEST_IMM_OP( binvi, x27, x28, 0x00000000, 0xb0ab577a, 0x14, x1, 16, x2)

inst_5:
// rs1==x25, rd==x26, 
// opcode: binvi ; op1:x25; dest:x26; op1val:0xf0eb21aa;  immval:0x1a
TEST_IMM_OP( binvi, x26, x25, 0x00000000, 0xf0eb21aa, 0x1a, x1, 20, x2)

inst_6:
// rs1==x26, rd==x25, 
// opcode: binvi ; op1:x26; dest:x25; op1val:0xa9e16e27;  immval:0x1b
TEST_IMM_OP( binvi, x25, x26, 0x00000000, 0xa9e16e27, 0x1b, x1, 24, x2)

inst_7:
// rs1==x23, rd==x24, 
// opcode: binvi ; op1:x23; dest:x24; op1val:0x0;  immval:0xc
TEST_IMM_OP( binvi, x24, x23, 0x00000000, 0x0, 0xc, x1, 28, x2)

inst_8:
// rs1==x24, rd==x23, 
// opcode: binvi ; op1:x24; dest:x23; op1val:0x80000000;  immval:0x5
TEST_IMM_OP( binvi, x23, x24, 0x00000000, 0x80000000, 0x5, x1, 32, x2)

inst_9:
// rs1==x21, rd==x22, 
// opcode: binvi ; op1:x21; dest:x22; op1val:0x40000000;  immval:0x1
TEST_IMM_OP( binvi, x22, x21, 0x00000000, 0x40000000, 0x1, x1, 36, x2)

inst_10:
// rs1==x22, rd==x21, 
// opcode: binvi ; op1:x22; dest:x21; op1val:0x60000000;  immval:0x18
TEST_IMM_OP( binvi, x21, x22, 0x00000000, 0x60000000, 0x18, x1, 40, x2)

inst_11:
// rs1==x19, rd==x20, 
// opcode: binvi ; op1:x19; dest:x20; op1val:0xb0000000;  immval:0x1e
TEST_IMM_OP( binvi, x20, x19, 0x00000000, 0xb0000000, 0x1e, x1, 44, x2)

inst_12:
// rs1==x20, rd==x19, 
// opcode: binvi ; op1:x20; dest:x19; op1val:0x8000000;  immval:0x1a
TEST_IMM_OP( binvi, x19, x20, 0x00000000, 0x8000000, 0x1a, x1, 48, x2)

inst_13:
// rs1==x17, rd==x18, 
// opcode: binvi ; op1:x17; dest:x18; op1val:0xf4000000;  immval:0x5
TEST_IMM_OP( binvi, x18, x17, 0x00000000, 0xf4000000, 0x5, x1, 52, x2)

inst_14:
// rs1==x18, rd==x17, 
// opcode: binvi ; op1:x18; dest:x17; op1val:0x82000000;  immval:0xa
TEST_IMM_OP( binvi, x17, x18, 0x00000000, 0x82000000, 0xa, x1, 56, x2)

inst_15:
// rs1==x15, rd==x16, 
// opcode: binvi ; op1:x15; dest:x16; op1val:0xfd000000;  immval:0x3
TEST_IMM_OP( binvi, x16, x15, 0x00000000, 0xfd000000, 0x3, x1, 60, x2)

inst_16:
// rs1==x16, rd==x15, 
// opcode: binvi ; op1:x16; dest:x15; op1val:0xd8800000;  immval:0xa
TEST_IMM_OP( binvi, x15, x16, 0x00000000, 0xd8800000, 0xa, x1, 64, x2)

inst_17:
// rs1==x13, rd==x14, 
// opcode: binvi ; op1:x13; dest:x14; op1val:0xc8c00000;  immval:0x14
TEST_IMM_OP( binvi, x14, x13, 0x00000000, 0xc8c00000, 0x14, x1, 68, x2)

inst_18:
// rs1==x14, rd==x13, 
// opcode: binvi ; op1:x14; dest:x13; op1val:0xa3200000;  immval:0x8
TEST_IMM_OP( binvi, x13, x14, 0x00000000, 0xa3200000, 0x8, x1, 72, x2)

inst_19:
// rs1==x11, rd==x12, 
// opcode: binvi ; op1:x11; dest:x12; op1val:0xc7900000;  immval:0x1b
TEST_IMM_OP( binvi, x12, x11, 0x00000000, 0xc7900000, 0x1b, x1, 76, x2)

inst_20:
// rs1==x12, rd==x11, 
// opcode: binvi ; op1:x12; dest:x11; op1val:0x46880000;  immval:0x1c
TEST_IMM_OP( binvi, x11, x12, 0x00000000, 0x46880000, 0x1c, x1, 80, x2)

inst_21:
// rs1==x9, rd==x10, 
// opcode: binvi ; op1:x9; dest:x10; op1val:0x55440000;  immval:0x1b
TEST_IMM_OP( binvi, x10, x9, 0x00000000, 0x55440000, 0x1b, x1, 84, x2)

inst_22:
// rs1==x10, rd==x9, 
// opcode: binvi ; op1:x10; dest:x9; op1val:0xa56a0000;  immval:0xe
TEST_IMM_OP( binvi, x9, x10, 0x00000000, 0xa56a0000, 0xe, x1, 88, x2)

inst_23:
// rs1==x7, rd==x8, 
// opcode: binvi ; op1:x7; dest:x8; op1val:0x405d0000;  immval:0x3
TEST_IMM_OP( binvi, x8, x7, 0x00000000, 0x405d0000, 0x3, x1, 92, x2)

inst_24:
// rs1==x8, rd==x7, 
// opcode: binvi ; op1:x8; dest:x7; op1val:0xcd2f8000;  immval:0x5
TEST_IMM_OP( binvi, x7, x8, 0x00000000, 0xcd2f8000, 0x5, x1, 96, x2)

inst_25:
// rs1==x5, rd==x6, 
// opcode: binvi ; op1:x5; dest:x6; op1val:0xa6c04000;  immval:0x19
TEST_IMM_OP( binvi, x6, x5, 0x00000000, 0xa6c04000, 0x19, x1, 100, x2)

inst_26:
// rs1==x6, rd==x5, 
// opcode: binvi ; op1:x6; dest:x5; op1val:0x33bc2000;  immval:0x15
TEST_IMM_OP( binvi, x5, x6, 0x00000000, 0x33bc2000, 0x15, x1, 104, x7)

inst_27:
// rs1==x3, rd==x4, 
// opcode: binvi ; op1:x3; dest:x4; op1val:0xf1c6b000;  immval:0xc
TEST_IMM_OP( binvi, x4, x3, 0x00000000, 0xf1c6b000, 0xc, x1, 108, x7)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_28:
// rs1==x4, rd==x3, 
// opcode: binvi ; op1:x4; dest:x3; op1val:0xaa3d6800;  immval:0xd
TEST_IMM_OP( binvi, x3, x4, 0x00000000, 0xaa3d6800, 0xd, x5, 0, x7)

inst_29:
// rs1==x1, rd==x2, 
// opcode: binvi ; op1:x1; dest:x2; op1val:0x7aa5e400;  immval:0xa
TEST_IMM_OP( binvi, x2, x1, 0x00000000, 0x7aa5e400, 0xa, x5, 4, x7)

inst_30:
// rs1==x2, rd==x1, 
// opcode: binvi ; op1:x2; dest:x1; op1val:0xc1b7ae00;  immval:0x1c
TEST_IMM_OP( binvi, x1, x2, 0x00000000, 0xc1b7ae00, 0x1c, x5, 8, x7)

inst_31:
// rs1==x0, 
// opcode: binvi ; op1:x0; dest:x31; op1val:0x0;  immval:0x9
TEST_IMM_OP( binvi, x31, x0, 0x00000000, 0x0, 0x9, x5, 12, x7)

inst_32:
// rd==x0, 
// opcode: binvi ; op1:x31; dest:x0; op1val:0x72c58380;  immval:0x0
TEST_IMM_OP( binvi, x0, x31, 0x00000000, 0x72c58380, 0x0, x5, 16, x7)

inst_33:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x32ab8740;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x32ab8740, 0xe, x5, 20, x7)

inst_34:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x96cdf1a0;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x96cdf1a0, 0x1d, x5, 24, x7)

inst_35:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xb87a9e30;  immval:0x11
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xb87a9e30, 0x11, x5, 28, x7)

inst_36:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x163dff98;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x163dff98, 0x17, x5, 32, x7)

inst_37:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x9205d39c;  immval:0x18
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x9205d39c, 0x18, x5, 36, x7)

inst_38:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x50a03c5a;  immval:0x16
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x50a03c5a, 0x16, x5, 40, x7)

inst_39:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x797d76df;  immval:0x11
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x797d76df, 0x11, x5, 44, x7)

inst_40:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x24496fe3;  immval:0x8
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x24496fe3, 0x8, x5, 48, x7)

inst_41:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xde14bff2;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xde14bff2, 0x1d, x5, 52, x7)

inst_42:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xb808a677;  immval:0x3
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xb808a677, 0x3, x5, 56, x7)

inst_43:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x76b1fd3d;  immval:0x7
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x76b1fd3d, 0x7, x5, 60, x7)

inst_44:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x5dcf019d;  immval:0xf
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x5dcf019d, 0xf, x5, 64, x7)

inst_45:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x47b7097b;  immval:0x1f
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x47b7097b, 0x1f, x5, 68, x7)

inst_46:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x759f1b44;  immval:0x10
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x759f1b44, 0x10, x5, 72, x7)

inst_47:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x40d90a1d;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x40d90a1d, 0x17, x5, 76, x7)

inst_48:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x2dedf123;  immval:0x16
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x2dedf123, 0x16, x5, 80, x7)

inst_49:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x4b1634e7;  immval:0xc
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x4b1634e7, 0xc, x5, 84, x7)

inst_50:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x8935b82f;  immval:0xb
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x8935b82f, 0xb, x5, 88, x7)

inst_51:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x70bcb8df;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x70bcb8df, 0x1c, x5, 92, x7)

inst_52:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x8de1c73f;  immval:0x8
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x8de1c73f, 0x8, x5, 96, x7)

inst_53:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xb0e04e7f;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xb0e04e7f, 0x1c, x5, 100, x7)

inst_54:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x589218ff;  immval:0x10
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x589218ff, 0x10, x5, 104, x7)

inst_55:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xa7be99ff;  immval:0x7
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xa7be99ff, 0x7, x5, 108, x7)

inst_56:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xa37e33ff;  immval:0x14
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xa37e33ff, 0x14, x5, 112, x7)

inst_57:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xe37d37ff;  immval:0x1b
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xe37d37ff, 0x1b, x5, 116, x7)

inst_58:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xabb4cfff;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xabb4cfff, 0x17, x5, 120, x7)

inst_59:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x7c9ddfff;  immval:0x1b
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x7c9ddfff, 0x1b, x5, 124, x7)

inst_60:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x5b11bfff;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x5b11bfff, 0xe, x5, 128, x7)

inst_61:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xcb347fff;  immval:0x10
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xcb347fff, 0x10, x5, 132, x7)

inst_62:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xf306ffff;  immval:0x8
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xf306ffff, 0x8, x5, 136, x7)

inst_63:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xbea5ffff;  immval:0x1b
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xbea5ffff, 0x1b, x5, 140, x7)

inst_64:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xd38bffff;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xd38bffff, 0x1c, x5, 144, x7)

inst_65:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x15b7ffff;  immval:0x10
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x15b7ffff, 0x10, x5, 148, x7)

inst_66:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xd58fffff;  immval:0x9
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xd58fffff, 0x9, x5, 152, x7)

inst_67:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfe1fffff;  immval:0x11
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfe1fffff, 0x11, x5, 156, x7)

inst_68:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x203fffff;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x203fffff, 0x0, x5, 160, x7)

inst_69:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x77fffff;  immval:0x1b
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x77fffff, 0x1b, x5, 164, x7)

inst_70:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xbeffffff;  immval:0x12
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xbeffffff, 0x12, x5, 168, x7)

inst_71:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x89ffffff;  immval:0xd
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x89ffffff, 0xd, x5, 172, x7)

inst_72:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x23ffffff;  immval:0x4
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x23ffffff, 0x4, x5, 176, x7)

inst_73:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xa7ffffff;  immval:0xb
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xa7ffffff, 0xb, x5, 180, x7)

inst_74:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xcfffffff;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xcfffffff, 0xe, x5, 184, x7)

inst_75:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x9fffffff;  immval:0x9
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x9fffffff, 0x9, x5, 188, x7)

inst_76:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xbfffffff;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xbfffffff, 0xe, x5, 192, x7)

inst_77:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x7fffffff;  immval:0xb
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x7fffffff, 0xb, x5, 196, x7)

inst_78:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffffff;  immval:0x12
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffffff, 0x12, x5, 200, x7)

inst_79:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x164f1513;  immval:0x1b
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x164f1513, 0x1b, x5, 204, x7)

inst_80:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xacc6d8f2;  immval:0x9
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xacc6d8f2, 0x9, x5, 208, x7)

inst_81:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xa123f501;  immval:0x6
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xa123f501, 0x6, x5, 212, x7)

inst_82:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xb57a6a1d;  immval:0x2
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xb57a6a1d, 0x2, x5, 216, x7)

inst_83:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xe90794df;  immval:0x1
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xe90794df, 0x1, x5, 220, x7)

inst_84:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xaf5570ee;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xaf5570ee, 0x0, x5, 224, x7)

inst_85:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xf542441e;  immval:0x1
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xf542441e, 0x1, x5, 228, x7)

inst_86:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x62f28d1b;  immval:0x4
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x62f28d1b, 0x4, x5, 232, x7)

inst_87:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x38b9b45d;  immval:0x12
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x38b9b45d, 0x12, x5, 236, x7)

inst_88:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x16809a12;  immval:0x6
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x16809a12, 0x6, x5, 240, x7)

inst_89:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x82a1750;  immval:0x6
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x82a1750, 0x6, x5, 244, x7)

inst_90:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x79dd25b;  immval:0x4
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x79dd25b, 0x4, x5, 248, x7)

inst_91:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x34c687b;  immval:0x12
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x34c687b, 0x12, x5, 252, x7)

inst_92:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x1b601fd;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x1b601fd, 0xe, x5, 256, x7)

inst_93:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xb302fd;  immval:0x10
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xb302fd, 0x10, x5, 260, x7)

inst_94:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x62a6b3;  immval:0x5
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x62a6b3, 0x5, x5, 264, x7)

inst_95:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x339238;  immval:0x11
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x339238, 0x11, x5, 268, x7)

inst_96:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x164af0;  immval:0x5
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x164af0, 0x5, x5, 272, x7)

inst_97:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x9222a;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x9222a, 0x0, x5, 276, x7)

inst_98:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x6284e;  immval:0x12
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x6284e, 0x12, x5, 280, x7)

inst_99:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x35161;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x35161, 0xe, x5, 284, x7)

inst_100:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x11e24;  immval:0xc
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x11e24, 0xc, x5, 288, x7)

inst_101:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xf614;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xf614, 0x1c, x5, 292, x7)

inst_102:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x5cc1;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x5cc1, 0x1d, x5, 296, x7)

inst_103:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x3226;  immval:0x1
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x3226, 0x1, x5, 300, x7)

inst_104:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x1d0c;  immval:0xf
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x1d0c, 0xf, x5, 304, x7)

inst_105:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xdd4;  immval:0x2
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xdd4, 0x2, x5, 308, x7)

inst_106:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x5d1;  immval:0x4
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x5d1, 0x4, x5, 312, x7)

inst_107:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x2a7;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x2a7, 0x0, x5, 316, x7)

inst_108:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x197;  immval:0xa
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x197, 0xa, x5, 320, x7)

inst_109:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xb9;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xb9, 0x1c, x5, 324, x7)

inst_110:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x4c;  immval:0x19
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x4c, 0x19, x5, 328, x7)

inst_111:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x26;  immval:0x2
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x26, 0x2, x5, 332, x7)

inst_112:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x12;  immval:0x9
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x12, 0x9, x5, 336, x7)

inst_113:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xc;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xc, 0x1c, x5, 340, x7)

inst_114:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x6;  immval:0xb
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x6, 0xb, x5, 344, x7)

inst_115:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x3;  immval:0x1e
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x3, 0x1e, x5, 348, x7)

inst_116:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x1;  immval:0xc
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x1, 0xc, x5, 352, x7)

inst_117:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x0;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x0, 0x1d, x5, 356, x7)

inst_118:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x59432a19;  immval:0xf
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x59432a19, 0xf, x5, 360, x7)

inst_119:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xceb506f6;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xceb506f6, 0x17, x5, 364, x7)

inst_120:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xc5ec6148;  immval:0x18
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xc5ec6148, 0x18, x5, 368, x7)

inst_121:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x99ef1857;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x99ef1857, 0x1d, x5, 372, x7)

inst_122:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x14b91c79;  immval:0x1e
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x14b91c79, 0x1e, x5, 376, x7)

inst_123:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x973e89c;  immval:0x1f
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x973e89c, 0x1f, x5, 380, x7)

inst_124:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x7843bdb9;  immval:0x1a
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x7843bdb9, 0x1a, x5, 384, x7)

inst_125:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x9798c9d0;  immval:0xe
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x9798c9d0, 0xe, x5, 388, x7)

inst_126:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xd814d576;  immval:0xa
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xd814d576, 0xa, x5, 392, x7)

inst_127:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xe0a37559;  immval:0x14
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xe0a37559, 0x14, x5, 396, x7)

inst_128:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xf79fb998;  immval:0x1e
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xf79fb998, 0x1e, x5, 400, x7)

inst_129:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xf87a2561;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xf87a2561, 0x1c, x5, 404, x7)

inst_130:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfda56d7f;  immval:0xf
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfda56d7f, 0xf, x5, 408, x7)

inst_131:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfe4deab5;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfe4deab5, 0x17, x5, 412, x7)

inst_132:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xff6875bb;  immval:0x13
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xff6875bb, 0x13, x5, 416, x7)

inst_133:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xff93d0e4;  immval:0x8
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xff93d0e4, 0x8, x5, 420, x7)

inst_134:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffd4aa23;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffd4aa23, 0x0, x5, 424, x7)

inst_135:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffe2fc91;  immval:0x18
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffe2fc91, 0x18, x5, 428, x7)

inst_136:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfff1d2a0;  immval:0x1c
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfff1d2a0, 0x1c, x5, 432, x7)

inst_137:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfff904d1;  immval:0xf
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfff904d1, 0xf, x5, 436, x7)

inst_138:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffcdb0b;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffcdb0b, 0x1d, x5, 440, x7)

inst_139:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffec2b4;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffec2b4, 0x17, x5, 444, x7)

inst_140:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffff1e5f;  immval:0x13
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffff1e5f, 0x13, x5, 448, x7)

inst_141:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffa2ee;  immval:0xb
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffa2ee, 0xb, x5, 452, x7)

inst_142:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffd410;  immval:0x10
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffd410, 0x10, x5, 456, x7)

inst_143:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffee0a;  immval:0x1a
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffee0a, 0x1a, x5, 460, x7)

inst_144:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffff32a;  immval:0x16
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffff32a, 0x16, x5, 464, x7)

inst_145:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffb84;  immval:0x8
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffb84, 0x8, x5, 468, x7)

inst_146:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffc1d;  immval:0x1a
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffc1d, 0x1a, x5, 472, x7)

inst_147:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffe31;  immval:0x17
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffe31, 0x17, x5, 476, x7)

inst_148:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffff44;  immval:0x4
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffff44, 0x4, x5, 480, x7)

inst_149:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffffba;  immval:0x1f
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffffba, 0x1f, x5, 484, x7)

inst_150:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffffc6;  immval:0xa
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffffc6, 0xa, x5, 488, x7)

inst_151:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xffffffe8;  immval:0x11
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xffffffe8, 0x11, x5, 492, x7)

inst_152:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffff2;  immval:0x1f
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffff2, 0x1f, x5, 496, x7)

inst_153:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffff9;  immval:0x1d
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffff9, 0x1d, x5, 500, x7)

inst_154:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffffd;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffffd, 0x0, x5, 504, x7)

inst_155:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0xfffffffe;  immval:0x1e
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0xfffffffe, 0x1e, x5, 508, x7)

inst_156:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x4c56bb00;  immval:0x9
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x4c56bb00, 0x9, x5, 512, x7)

inst_157:
// 
// opcode: binvi ; op1:x30; dest:x31; op1val:0x72c58380;  immval:0x0
TEST_IMM_OP( binvi, x31, x30, 0x00000000, 0x72c58380, 0x0, x5, 516, x7)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 28*(XLEN/32),4,0xdeadbeef


signature_x5_0:
    .fill 130*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
