// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Wed Aug  4 06:39:00 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.j instruction of the RISC-V C extension for the cj covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cj)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// imm_val < 0, imm_val == -66
// opcode:c.j; immval:0x42
TEST_CJ_OP(c.j, x2, 0x42, 1b, x1, 0)

inst_1:
// imm_val == -1026, 
// opcode:c.j; immval:0x402
TEST_CJ_OP(c.j, x2, 0x402, 1b, x1, 4)

inst_2:
// imm_val == -514, 
// opcode:c.j; immval:0x202
TEST_CJ_OP(c.j, x2, 0x202, 1b, x1, 8)

inst_3:
// imm_val == -258, 
// opcode:c.j; immval:0x102
TEST_CJ_OP(c.j, x2, 0x102, 1b, x1, 12)

inst_4:
// imm_val == -130, 
// opcode:c.j; immval:0x82
TEST_CJ_OP(c.j, x2, 0x82, 1b, x1, 16)

inst_5:
// imm_val == -34, 
// opcode:c.j; immval:0x22
TEST_CJ_OP(c.j, x2, 0x22, 1b, x1, 20)

inst_6:
// imm_val == -18, 
// opcode:c.j; immval:0x12
TEST_CJ_OP(c.j, x2, 0x12, 1b, x1, 24)

inst_7:
// imm_val == -10, 
// opcode:c.j; immval:0xa
TEST_CJ_OP(c.j, x2, 0xa, 1b, x1, 28)

inst_8:
// imm_val == 1024, imm_val > 0
// opcode:c.j; immval:0x400
TEST_CJ_OP(c.j, x2, 0x400, 3f, x1, 32)

inst_9:
// imm_val == 512, 
// opcode:c.j; immval:0x200
TEST_CJ_OP(c.j, x2, 0x200, 3f, x1, 36)

inst_10:
// imm_val == 1364, 
// opcode:c.j; immval:0x554
TEST_CJ_OP(c.j, x2, 0x554, 3f, x1, 40)

inst_11:
// imm_val == -1366, 
// opcode:c.j; immval:0x556
TEST_CJ_OP(c.j, x2, 0x556, 1b, x1, 44)

inst_12:
// imm_val == 256, 
// opcode:c.j; immval:0x100
TEST_CJ_OP(c.j, x2, 0x100, 3f, x1, 48)

inst_13:
// imm_val == 128, 
// opcode:c.j; immval:0x80
TEST_CJ_OP(c.j, x2, 0x80, 3f, x1, 52)

inst_14:
// imm_val == 64, 
// opcode:c.j; immval:0x40
TEST_CJ_OP(c.j, x2, 0x40, 3f, x1, 56)

inst_15:
// imm_val == 32, 
// opcode:c.j; immval:0x20
TEST_CJ_OP(c.j, x2, 0x20, 3f, x1, 60)

inst_16:
// imm_val == 16, 
// opcode:c.j; immval:0x10
TEST_CJ_OP(c.j, x2, 0x10, 3f, x1, 64)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 17*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
