
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Sun Aug  7 18:29:26 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/anku/work2/bcrypto/32/dataset.yaml \
//                  --cgf /home/anku/work2/bcrypto/32/rv32ik.yaml \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the zip instruction of the RISC-V RV32Zk,RV32Zbkb,RV32Zkn,RV32Zks extension for the zip covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IZk,RV32IZbkb,RV32IZkn,RV32IZks")

.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zk.*);def TEST_CASE_1=True;",zip)

RVTEST_CASE(1,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zkn.*);def TEST_CASE_1=True;",zip)

RVTEST_CASE(2,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zks.*);def TEST_CASE_1=True;",zip)

RVTEST_CASE(3,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zbkb.*);def TEST_CASE_1=True;",zip)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 != rd, rs1==x30, rd==x31, 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffffff;
LI(x30,0xffffffff)
zip x31, x30
sw x31, 0(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x31, 0x00000000)

inst_1:
// rs1 == rd, rs1==x29, rd==x29, 
// opcode: zip ; op1:x29; dest:x29; op1val:0x0;
LI(x29,0x0)
zip x29, x29
sw x29, 4(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x29, 0x00000000)

inst_2:
// rs1==x31, rd==x30, 
// opcode: zip ; op1:x31; dest:x30; op1val:0x80000000;
LI(x31,0x80000000)
zip x30, x31
sw x30, 8(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x30, 0x00000000)

inst_3:
// rs1==x27, rd==x28, 
// opcode: zip ; op1:x27; dest:x28; op1val:0x40000000;
LI(x27,0x40000000)
zip x28, x27
sw x28, 12(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000)

inst_4:
// rs1==x28, rd==x27, 
// opcode: zip ; op1:x28; dest:x27; op1val:0xa0000000;
LI(x28,0xa0000000)
zip x27, x28
sw x27, 16(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x27, 0x00000000)

inst_5:
// rs1==x25, rd==x26, 
// opcode: zip ; op1:x25; dest:x26; op1val:0x90000000;
LI(x25,0x90000000)
zip x26, x25
sw x26, 20(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x26, 0x00000000)

inst_6:
// rs1==x26, rd==x25, 
// opcode: zip ; op1:x26; dest:x25; op1val:0xc8000000;
LI(x26,0xc8000000)
zip x25, x26
sw x25, 24(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000)

inst_7:
// rs1==x23, rd==x24, 
// opcode: zip ; op1:x23; dest:x24; op1val:0x2c000000;
LI(x23,0x2c000000)
zip x24, x23
sw x24, 28(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x24, 0x00000000)

inst_8:
// rs1==x24, rd==x23, 
// opcode: zip ; op1:x24; dest:x23; op1val:0xae000000;
LI(x24,0xae000000)
zip x23, x24
sw x23, 32(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x23, 0x00000000)

inst_9:
// rs1==x21, rd==x22, 
// opcode: zip ; op1:x21; dest:x22; op1val:0x43000000;
LI(x21,0x43000000)
zip x22, x21
sw x22, 36(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000)

inst_10:
// rs1==x22, rd==x21, 
// opcode: zip ; op1:x22; dest:x21; op1val:0xf1800000;
LI(x22,0xf1800000)
zip x21, x22
sw x21, 40(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x21, 0x00000000)

inst_11:
// rs1==x19, rd==x20, 
// opcode: zip ; op1:x19; dest:x20; op1val:0xaec00000;
LI(x19,0xaec00000)
zip x20, x19
sw x20, 44(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x20, 0x00000000)

inst_12:
// rs1==x20, rd==x19, 
// opcode: zip ; op1:x20; dest:x19; op1val:0x99200000;
LI(x20,0x99200000)
zip x19, x20
sw x19, 48(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000)

inst_13:
// rs1==x17, rd==x18, 
// opcode: zip ; op1:x17; dest:x18; op1val:0xb0700000;
LI(x17,0xb0700000)
zip x18, x17
sw x18, 52(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x18, 0x00000000)

inst_14:
// rs1==x18, rd==x17, 
// opcode: zip ; op1:x18; dest:x17; op1val:0x35880000;
LI(x18,0x35880000)
zip x17, x18
sw x17, 56(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x17, 0x00000000)

inst_15:
// rs1==x15, rd==x16, 
// opcode: zip ; op1:x15; dest:x16; op1val:0x5acc0000;
LI(x15,0x5acc0000)
zip x16, x15
sw x16, 60(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000)

inst_16:
// rs1==x16, rd==x15, 
// opcode: zip ; op1:x16; dest:x15; op1val:0x5e3a0000;
LI(x16,0x5e3a0000)
zip x15, x16
sw x15, 64(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x15, 0x00000000)

inst_17:
// rs1==x13, rd==x14, 
// opcode: zip ; op1:x13; dest:x14; op1val:0xae1d0000;
LI(x13,0xae1d0000)
zip x14, x13
sw x14, 68(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x14, 0x00000000)

inst_18:
// rs1==x14, rd==x13, 
// opcode: zip ; op1:x14; dest:x13; op1val:0x6eb38000;
LI(x14,0x6eb38000)
zip x13, x14
sw x13, 72(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000)

inst_19:
// rs1==x11, rd==x12, 
// opcode: zip ; op1:x11; dest:x12; op1val:0xbe164000;
LI(x11,0xbe164000)
zip x12, x11
sw x12, 76(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x12, 0x00000000)

inst_20:
// rs1==x12, rd==x11, 
// opcode: zip ; op1:x12; dest:x11; op1val:0xcdf1a000;
LI(x12,0xcdf1a000)
zip x11, x12
sw x11, 80(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000)

inst_21:
// rs1==x9, rd==x10, 
// opcode: zip ; op1:x9; dest:x10; op1val:0x804dd000;
LI(x9,0x804dd000)
zip x10, x9
sw x10, 84(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000)

inst_22:
// rs1==x10, rd==x9, 
// opcode: zip ; op1:x10; dest:x9; op1val:0x3d4f1800;
LI(x10,0x3d4f1800)
zip x9, x10
sw x9, 88(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000)

inst_23:
// rs1==x7, rd==x8, 
// opcode: zip ; op1:x7; dest:x8; op1val:0xbfa44c00;
LI(x7,0xbfa44c00)
zip x8, x7
sw x8, 92(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000)

inst_24:
// rs1==x8, rd==x7, 
// opcode: zip ; op1:x8; dest:x7; op1val:0x4544fa00;
LI(x8,0x4544fa00)
zip x7, x8
sw x7, 96(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000)

inst_25:
// rs1==x5, rd==x6, 
// opcode: zip ; op1:x5; dest:x6; op1val:0xc7bff300;
LI(x5,0xc7bff300)
zip x6, x5
sw x6, 100(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000)

inst_26:
// rs1==x6, rd==x5, 
// opcode: zip ; op1:x6; dest:x5; op1val:0xd99d0080;
LI(x6,0xd99d0080)
zip x5, x6
sw x5, 104(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x5, 0x00000000)

inst_27:
// rs1==x3, rd==x4, 
// opcode: zip ; op1:x3; dest:x4; op1val:0x205d39c0;
LI(x3,0x205d39c0)
zip x4, x3
sw x4, 108(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x4, 0x00000000)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_28:
// rs1==x4, rd==x3, 
// opcode: zip ; op1:x4; dest:x3; op1val:0x31711ba0;
LI(x4,0x31711ba0)
zip x3, x4
sw x3, 0(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x3, 0x00000000)

inst_29:
// rs1==x1, rd==x2, 
// opcode: zip ; op1:x1; dest:x2; op1val:0xa99e07b0;
LI(x1,0xa99e07b0)
zip x2, x1
sw x2, 4(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x2, 0x00000000)

inst_30:
// rs1==x2, rd==x1, 
// opcode: zip ; op1:x2; dest:x1; op1val:0x3ba8ea68;
LI(x2,0x3ba8ea68)
zip x1, x2
sw x1, 8(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x1, 0x00000000)

inst_31:
// rs1==x0, 
// opcode: zip ; op1:x0; dest:x31; op1val:0x0;
LI(x0,0x0)
zip x31, x0
sw x31, 12(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_32:
// rd==x0, 
// opcode: zip ; op1:x31; dest:x0; op1val:0x89b9b4d6;
LI(x31,0x89b9b4d6)
zip x0, x31
sw x0, 16(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x0, 0x00000000)

inst_33:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x797d76df;
LI(x30,0x797d76df)
zip x31, x30
sw x31, 20(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_34:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x3b1d74c;
LI(x30,0x3b1d74c)
zip x31, x30
sw x31, 24(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_35:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xff7d5ec1;
LI(x30,0xff7d5ec1)
zip x31, x30
sw x31, 28(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_36:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x9bc03e23;
LI(x30,0x9bc03e23)
zip x31, x30
sw x31, 32(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_37:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xaf2529c7;
LI(x30,0xaf2529c7)
zip x31, x30
sw x31, 36(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_38:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xd670a82f;
LI(x30,0xd670a82f)
zip x31, x30
sw x31, 40(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_39:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2054fa9f;
LI(x30,0x2054fa9f)
zip x31, x30
sw x31, 44(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_40:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x6e7c0c3f;
LI(x30,0x6e7c0c3f)
zip x31, x30
sw x31, 48(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_41:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x7ac5f7f;
LI(x30,0x7ac5f7f)
zip x31, x30
sw x31, 52(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_42:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x4b6ea0ff;
LI(x30,0x4b6ea0ff)
zip x31, x30
sw x31, 56(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_43:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xbea425ff;
LI(x30,0xbea425ff)
zip x31, x30
sw x31, 60(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_44:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x36c2a3ff;
LI(x30,0x36c2a3ff)
zip x31, x30
sw x31, 64(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_45:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xd885b7ff;
LI(x30,0xd885b7ff)
zip x31, x30
sw x31, 68(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_46:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x88042fff;
LI(x30,0x88042fff)
zip x31, x30
sw x31, 72(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_47:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x12219fff;
LI(x30,0x12219fff)
zip x31, x30
sw x31, 76(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_48:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2155bfff;
LI(x30,0x2155bfff)
zip x31, x30
sw x31, 80(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_49:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2ff77fff;
LI(x30,0x2ff77fff)
zip x31, x30
sw x31, 84(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_50:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xbbe8ffff;
LI(x30,0xbbe8ffff)
zip x31, x30
sw x31, 88(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_51:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xa415ffff;
LI(x30,0xa415ffff)
zip x31, x30
sw x31, 92(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_52:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x39a3ffff;
LI(x30,0x39a3ffff)
zip x31, x30
sw x31, 96(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_53:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xde87ffff;
LI(x30,0xde87ffff)
zip x31, x30
sw x31, 100(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_54:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x25afffff;
LI(x30,0x25afffff)
zip x31, x30
sw x31, 104(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_55:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xaa9fffff;
LI(x30,0xaa9fffff)
zip x31, x30
sw x31, 108(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_56:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x3b3fffff;
LI(x30,0x3b3fffff)
zip x31, x30
sw x31, 112(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_57:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xa67fffff;
LI(x30,0xa67fffff)
zip x31, x30
sw x31, 116(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_58:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2effffff;
LI(x30,0x2effffff)
zip x31, x30
sw x31, 120(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_59:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xe1ffffff;
LI(x30,0xe1ffffff)
zip x31, x30
sw x31, 124(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_60:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xdbffffff;
LI(x30,0xdbffffff)
zip x31, x30
sw x31, 128(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_61:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xc7ffffff;
LI(x30,0xc7ffffff)
zip x31, x30
sw x31, 132(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_62:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xafffffff;
LI(x30,0xafffffff)
zip x31, x30
sw x31, 136(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_63:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xdfffffff;
LI(x30,0xdfffffff)
zip x31, x30
sw x31, 140(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_64:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xbfffffff;
LI(x30,0xbfffffff)
zip x31, x30
sw x31, 144(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_65:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x7fffffff;
LI(x30,0x7fffffff)
zip x31, x30
sw x31, 148(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_66:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfb710735;
LI(x30,0xfb710735)
zip x31, x30
sw x31, 152(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_67:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x586e86cc;
LI(x30,0x586e86cc)
zip x31, x30
sw x31, 156(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_68:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2ab8ab68;
LI(x30,0x2ab8ab68)
zip x31, x30
sw x31, 160(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_69:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x126b7f63;
LI(x30,0x126b7f63)
zip x31, x30
sw x31, 164(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_70:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x9852f28;
LI(x30,0x9852f28)
zip x31, x30
sw x31, 168(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_71:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x7eff9c1;
LI(x30,0x7eff9c1)
zip x31, x30
sw x31, 172(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_72:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x344dd40;
LI(x30,0x344dd40)
zip x31, x30
sw x31, 176(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_73:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x1e7d160;
LI(x30,0x1e7d160)
zip x31, x30
sw x31, 180(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_74:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xb62f26;
LI(x30,0xb62f26)
zip x31, x30
sw x31, 184(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_75:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x4caf9d;
LI(x30,0x4caf9d)
zip x31, x30
sw x31, 188(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_76:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2bb482;
LI(x30,0x2bb482)
zip x31, x30
sw x31, 192(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_77:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x13edc7;
LI(x30,0x13edc7)
zip x31, x30
sw x31, 196(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_78:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x87994;
LI(x30,0x87994)
zip x31, x30
sw x31, 200(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_79:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x51426;
LI(x30,0x51426)
zip x31, x30
sw x31, 204(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_80:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x28854;
LI(x30,0x28854)
zip x31, x30
sw x31, 208(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_81:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x167ee;
LI(x30,0x167ee)
zip x31, x30
sw x31, 212(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_82:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfe7a;
LI(x30,0xfe7a)
zip x31, x30
sw x31, 216(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_83:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x5e87;
LI(x30,0x5e87)
zip x31, x30
sw x31, 220(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_84:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x31c3;
LI(x30,0x31c3)
zip x31, x30
sw x31, 224(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_85:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x192a;
LI(x30,0x192a)
zip x31, x30
sw x31, 228(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_86:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xe79;
LI(x30,0xe79)
zip x31, x30
sw x31, 232(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_87:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x77a;
LI(x30,0x77a)
zip x31, x30
sw x31, 236(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_88:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x233;
LI(x30,0x233)
zip x31, x30
sw x31, 240(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_89:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x151;
LI(x30,0x151)
zip x31, x30
sw x31, 244(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_90:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xbe;
LI(x30,0xbe)
zip x31, x30
sw x31, 248(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_91:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x77;
LI(x30,0x77)
zip x31, x30
sw x31, 252(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_92:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x22;
LI(x30,0x22)
zip x31, x30
sw x31, 256(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_93:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x16;
LI(x30,0x16)
zip x31, x30
sw x31, 260(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_94:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xe;
LI(x30,0xe)
zip x31, x30
sw x31, 264(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_95:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x4;
LI(x30,0x4)
zip x31, x30
sw x31, 268(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_96:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x2;
LI(x30,0x2)
zip x31, x30
sw x31, 272(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_97:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x1;
LI(x30,0x1)
zip x31, x30
sw x31, 276(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_98:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x61b0ee0a;
LI(x30,0x61b0ee0a)
zip x31, x30
sw x31, 280(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_99:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x9ae6a229;
LI(x30,0x9ae6a229)
zip x31, x30
sw x31, 284(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_100:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xda6ab32a;
LI(x30,0xda6ab32a)
zip x31, x30
sw x31, 288(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_101:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xe38123e6;
LI(x30,0xe38123e6)
zip x31, x30
sw x31, 292(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_102:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xf4338384;
LI(x30,0xf4338384)
zip x31, x30
sw x31, 296(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_103:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfb9f15c5;
LI(x30,0xfb9f15c5)
zip x31, x30
sw x31, 300(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_104:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfd680c1d;
LI(x30,0xfd680c1d)
zip x31, x30
sw x31, 304(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_105:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfe74e45f;
LI(x30,0xfe74e45f)
zip x31, x30
sw x31, 308(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_106:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xff1e5bf0;
LI(x30,0xff1e5bf0)
zip x31, x30
sw x31, 312(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_107:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xff9c25e7;
LI(x30,0xff9c25e7)
zip x31, x30
sw x31, 316(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_108:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffcbcf13;
LI(x30,0xffcbcf13)
zip x31, x30
sw x31, 320(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_109:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffe06f87;
LI(x30,0xffe06f87)
zip x31, x30
sw x31, 324(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_110:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfff7c831;
LI(x30,0xfff7c831)
zip x31, x30
sw x31, 328(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_111:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffa9778;
LI(x30,0xfffa9778)
zip x31, x30
sw x31, 332(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_112:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffceb44;
LI(x30,0xfffceb44)
zip x31, x30
sw x31, 336(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_113:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffe3fba;
LI(x30,0xfffe3fba)
zip x31, x30
sw x31, 340(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_114:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffff1658;
LI(x30,0xffff1658)
zip x31, x30
sw x31, 344(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_115:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffac3a;
LI(x30,0xffffac3a)
zip x31, x30
sw x31, 348(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_116:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffcdf0;
LI(x30,0xffffcdf0)
zip x31, x30
sw x31, 352(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_117:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffe684;
LI(x30,0xffffe684)
zip x31, x30
sw x31, 356(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_118:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffff1c6;
LI(x30,0xfffff1c6)
zip x31, x30
sw x31, 360(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_119:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffff806;
LI(x30,0xfffff806)
zip x31, x30
sw x31, 364(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_120:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffffc78;
LI(x30,0xfffffc78)
zip x31, x30
sw x31, 368(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_121:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffffe3b;
LI(x30,0xfffffe3b)
zip x31, x30
sw x31, 372(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_122:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffff5a;
LI(x30,0xffffff5a)
zip x31, x30
sw x31, 376(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_123:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffff88;
LI(x30,0xffffff88)
zip x31, x30
sw x31, 380(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_124:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffffc1;
LI(x30,0xffffffc1)
zip x31, x30
sw x31, 384(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_125:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xffffffe8;
LI(x30,0xffffffe8)
zip x31, x30
sw x31, 388(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_126:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffffff1;
LI(x30,0xfffffff1)
zip x31, x30
sw x31, 392(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_127:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffffff9;
LI(x30,0xfffffff9)
zip x31, x30
sw x31, 396(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_128:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffffffd;
LI(x30,0xfffffffd)
zip x31, x30
sw x31, 400(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_129:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xfffffffe;
LI(x30,0xfffffffe)
zip x31, x30
sw x31, 404(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_130:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0xa14078b4;
LI(x30,0xa14078b4)
zip x31, x30
sw x31, 408(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)

inst_131:
// 
// opcode: zip ; op1:x30; dest:x31; op1val:0x89b9b4d6;
LI(x30,0x89b9b4d6)
zip x31, x30
sw x31, 412(x5)
RVMODEL_IO_ASSERT_GPR_EQ(x7, x31, 0x00000000)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 28*(XLEN/32),4,0xdeadbeef


signature_x5_0:
    .fill 104*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
