diff --git a/stream_fork.sv b/stream_fork.sv
index ebe65f9b..7ae27c1a 100644
--- a/stream_fork.sv
+++ b/stream_fork.sv
@@ -16,7 +16,7 @@
 // This module has no data ports because stream data does not need to be forked: the data of the
 // input stream can just be applied at all output streams.
 
-`include "common_cells/assertions.svh"
+`include "prim_assert.sv"
 
 module stream_fork #(
     parameter int unsigned N_OUP = 0    // Synopsys DC requires a default value for parameters.
@@ -124,8 +124,6 @@ module stream_fork #(
     assign all_ones = '1;   // Synthesis fix for Vivado, which does not correctly compute the width
                             // of the '1 literal when assigned to a port of parametrized width.
 
-`ifndef COMMON_CELLS_ASSERTS_OFF
-    `ASSERT_INIT(n_oup_0, N_OUP >= 1, "Number of outputs must be at least 1!")
-`endif
+    `ASSERT_INIT(NumOutputLargerZero_A, N_OUP >= 1)
 
 endmodule
