# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

##########################################################

# This file is generated by gen_testlist.py script and largely copies
# the formatting of the testlist.yaml used by riscv-dv, but only specifies
# directed tests.
#
# - All paths are relative to THIS FILE.
# - Each 'test' can specify a config by name to re-use common configuration
# - If a test redefines a key already in the config, the test option takes priority.

##########################################################

- config: riscv-tests
  ld_script: link.ld
  includes: .
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
  rtl_test: core_ibex_base_test
  rtl_params:
    PMPEnable: 1
  timeout_s: 300

- config: riscv-arch-tests
  ld_script: link.ld
  includes: .
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-arch-tests/riscv-test-suite/env/
            -I../../../vendor/riscv-isa-sim/arch_test_target/spike/
  rtl_test: core_ibex_base_test
  rtl_params:
    PMPEnable: 1
  timeout_s: 300

- config: epmp-tests
  ld_script: ../../../../vendor/riscv-isa-sim/tests/mseccfg/mseccfg_test.ld
  includes: .
  gcc_opts: -march=rv32imc -O2 -I . -I ./. -I ../softfloat -I ../riscv -fno-builtin-printf
            -fdata-sections -fno-section-anchors -DPRINTF_SUPPORTED=1
            ../../../vendor/riscv-isa-sim/tests/mseccfg/crt.S
            ../../../vendor/riscv-isa-sim/tests/mseccfg/syscalls.c
            -mcmodel=medany -static -nostdlib -nostartfiles -lm -lgcc
            -Wl,-M -Wl,-Map=link.log
  rtl_test: core_ibex_base_test
  rtl_params:
    PMPEnable: 1
  timeout_s: 300

# Custom directed tests

- test: empty
  desc: >
    Empty directed test
  iterations: 1
  test_srcs: empty/empty.S
  config: riscv-tests

- test: mcounteren_test
  desc: >
    Tests the mcounteren CSR: reset value, hardwired-zero bit 1 (time),
    and U-mode counter access gating.
  iterations: 1
  test_srcs: mcounteren_test/mcounteren_test.S
  config: riscv-tests

- test: mcounteren_lock_test
  desc: >
    Tests that mcounteren retains its value after mcounteren_writable_i is
    de-asserted mid-simulation (write-lock).
  iterations: 1
  rtl_test: core_ibex_mcounteren_lock_test
  test_srcs: mcounteren_test/mcounteren_lock_test.S
  config: riscv-tests

- test: pmp_mseccfg_test_rlb1_l0_0_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=0

- test: pmp_mseccfg_test_rlb1_l0_1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=0

- test: pmp_mseccfg_test_rlb1_l1_0_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=1

- test: pmp_mseccfg_test_rlb1_l1_1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=1

- test: pmp_mseccfg_test_rlb0_l0_0_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DSET_PMP_L=0 -DSET_PMP_L_PREV=0

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_X1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_X1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1_X1

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1_u0
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1_X1

- test: pmp_mseccfg_test_rlb1_l0_0_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -DU_MODE

- test: pmp_mseccfg_test_rlb1_l0_1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DU_MODE

- test: pmp_mseccfg_test_rlb1_l1_0_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=0 -DSET_PMP_L_PREV=1 -DU_MODE

- test: pmp_mseccfg_test_rlb1_l1_1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DRLB -DSET_PMP_L=1 -DSET_PMP_L_PREV=1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_0_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DPMP_REGION=4 -DSET_PMP_L=0 -DSET_PMP_L_PREV=0 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_x1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_X1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_x1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_X1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_w1_x1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_W1_X1 -DU_MODE

- test: pmp_mseccfg_test_rlb0_l0_1_next_l1_r1_w1_x1_u1
  desc: >
    mseccfg test
  iterations: 1
  test_srcs: pmp_mseccfg_test/pmp_mseccfg_test.S
  config: riscv-tests
  gcc_opts: -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
            -I../../../vendor/riscv-test-env/
            -I../../../vendor/riscv-test-env/p/
            -I../../../vendor/riscv-tests/isa/macros/scalar/
            -DSET_PMP_L=1 -DSET_PMP_L_PREV=0 -DPMP_NEXT_L1_R1_W1_X1 -DU_MODE

- test: access_pmp_overlap
  desc: >
    PMP access basic test
  iterations: 1
  test_srcs: access_pmp_overlap/access_pmp_overlap.S
  config: riscv-tests

- test: u_mode_exec_test
  desc: >
    PMP U mode exec test
  iterations: 1
  test_srcs: u_mode_exec_test/u_mode_exec_test.S
  config: riscv-tests

# Test-suite: riscv-tests

- test: breakpoint
  desc: >
    riscv test - breakpoint
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/breakpoint.S
  config: riscv-tests

- test: csr
  desc: >
    riscv test - csr
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/csr.S
  config: riscv-tests

- test: illegal
  desc: >
    riscv test - illegal
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/illegal.S
  config: riscv-tests

- test: lh-misaligned
  desc: >
    riscv test - lh-misaligned
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/lh-misaligned.S
  config: riscv-tests

- test: lw-misaligned
  desc: >
    riscv test - lw-misaligned
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/lw-misaligned.S
  config: riscv-tests

- test: ma_addr
  desc: >
    riscv test - ma_addr
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/ma_addr.S
  config: riscv-tests

- test: ma_fetch
  desc: >
    riscv test - ma_fetch
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/ma_fetch.S
  config: riscv-tests

- test: mcsr
  desc: >
    riscv test - mcsr
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/mcsr.S
  config: riscv-tests

- test: sbreak
  desc: >
    riscv test - sbreak
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sbreak.S
  config: riscv-tests

- test: scall
  desc: >
    riscv test - scall
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/scall.S
  config: riscv-tests

- test: shamt
  desc: >
    riscv test - shamt
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S
  config: riscv-tests

- test: sh-misaligned
  desc: >
    riscv test - sh-misaligned
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S
  config: riscv-tests

- test: sw-misaligned
  desc: >
    riscv test - sw-misaligned
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sw-misaligned.S
  config: riscv-tests

- test: zicntr
  desc: >
    riscv test - zicntr
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/zicntr.S
  config: riscv-tests

- test: rvc
  desc: >
    riscv test - rvc
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32uc/rvc.S
  config: riscv-tests

- test: div
  desc: >
    riscv test - div
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/div.S
  config: riscv-tests

- test: divu
  desc: >
    riscv test - divu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/divu.S
  config: riscv-tests

- test: mulh
  desc: >
    riscv test - mulh
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulh.S
  config: riscv-tests

- test: mulhsu
  desc: >
    riscv test - mulhsu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhsu.S
  config: riscv-tests

- test: mulhu
  desc: >
    riscv test - mulhu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhu.S
  config: riscv-tests

- test: mul
  desc: >
    riscv test - mul
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S
  config: riscv-tests

- test: rem
  desc: >
    riscv test - rem
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/rem.S
  config: riscv-tests

- test: remu
  desc: >
    riscv test - remu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/remu.S
  config: riscv-tests

- test: addi
  desc: >
    riscv test - addi
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/addi.S
  config: riscv-tests

- test: add
  desc: >
    riscv test - add
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/add.S
  config: riscv-tests

- test: andi
  desc: >
    riscv test - andi
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/andi.S
  config: riscv-tests

- test: and
  desc: >
    riscv test - and
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/and.S
  config: riscv-tests

- test: auipc
  desc: >
    riscv test - auipc
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/auipc.S
  config: riscv-tests

- test: beq
  desc: >
    riscv test - beq
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/beq.S
  config: riscv-tests

- test: bge
  desc: >
    riscv test - bge
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/bge.S
  config: riscv-tests

- test: bgeu
  desc: >
    riscv test - bgeu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/bgeu.S
  config: riscv-tests

- test: blt
  desc: >
    riscv test - blt
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/blt.S
  config: riscv-tests

- test: bltu
  desc: >
    riscv test - bltu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/bltu.S
  config: riscv-tests

- test: bne
  desc: >
    riscv test - bne
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/bne.S
  config: riscv-tests

- test: fence_i
  desc: >
    riscv test - fence_i
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/fence_i.S
  config: riscv-tests

- test: jalr
  desc: >
    riscv test - jalr
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jalr.S
  config: riscv-tests

- test: jal
  desc: >
    riscv test - jal
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jal.S
  config: riscv-tests

- test: lb
  desc: >
    riscv test - lb
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lb.S
  config: riscv-tests

- test: lbu
  desc: >
    riscv test - lbu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lbu.S
  config: riscv-tests

- test: lh
  desc: >
    riscv test - lh
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lh.S
  config: riscv-tests

- test: lhu
  desc: >
    riscv test - lhu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lhu.S
  config: riscv-tests

- test: lui
  desc: >
    riscv test - lui
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lui.S
  config: riscv-tests

- test: lw
  desc: >
    riscv test - lw
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lw.S
  config: riscv-tests

- test: ori
  desc: >
    riscv test - ori
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/ori.S
  config: riscv-tests

- test: or
  desc: >
    riscv test - or
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/or.S
  config: riscv-tests

- test: sb
  desc: >
    riscv test - sb
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sb.S
  config: riscv-tests

- test: sh
  desc: >
    riscv test - sh
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sh.S
  config: riscv-tests

- test: simple
  desc: >
    riscv test - simple
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/simple.S
  config: riscv-tests

- test: slli
  desc: >
    riscv test - slli
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slli.S
  config: riscv-tests

- test: sll
  desc: >
    riscv test - sll
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sll.S
  config: riscv-tests

- test: slti
  desc: >
    riscv test - slti
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slti.S
  config: riscv-tests

- test: sltiu
  desc: >
    riscv test - sltiu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltiu.S
  config: riscv-tests

- test: slt
  desc: >
    riscv test - slt
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slt.S
  config: riscv-tests

- test: sltu
  desc: >
    riscv test - sltu
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltu.S
  config: riscv-tests

- test: srai
  desc: >
    riscv test - srai
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srai.S
  config: riscv-tests

- test: sra
  desc: >
    riscv test - sra
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sra.S
  config: riscv-tests

- test: srli
  desc: >
    riscv test - srli
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srli.S
  config: riscv-tests

- test: srl
  desc: >
    riscv test - srl
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srl.S
  config: riscv-tests

- test: sub
  desc: >
    riscv test - sub
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sub.S
  config: riscv-tests

- test: sw
  desc: >
    riscv test - sw
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sw.S
  config: riscv-tests

- test: xori
  desc: >
    riscv test - xori
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xori.S
  config: riscv-tests

- test: xor
  desc: >
    riscv test - xor
  iterations: 1
  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xor.S
  config: riscv-tests

# Test-suite: riscv-arch-tests

- test: div-01
  desc: >
    riscv test - div-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/div-01.S
  config: riscv-arch-tests

- test: divu-01
  desc: >
    riscv test - divu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/divu-01.S
  config: riscv-arch-tests

- test: mul-01
  desc: >
    riscv test - mul-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mul-01.S
  config: riscv-arch-tests

- test: mulh-01
  desc: >
    riscv test - mulh-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulh-01.S
  config: riscv-arch-tests

- test: mulhsu-01
  desc: >
    riscv test - mulhsu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S
  config: riscv-arch-tests

- test: mulhu-01
  desc: >
    riscv test - mulhu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/mulhu-01.S
  config: riscv-arch-tests

- test: rem-01
  desc: >
    riscv test - rem-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/rem-01.S
  config: riscv-arch-tests

- test: remu-01
  desc: >
    riscv test - remu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/M/src/remu-01.S
  config: riscv-arch-tests

- test: cadd-01
  desc: >
    riscv test - cadd-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cadd-01.S
  config: riscv-arch-tests

- test: caddi-01
  desc: >
    riscv test - caddi-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi-01.S
  config: riscv-arch-tests

- test: caddi16sp-01
  desc: >
    riscv test - caddi16sp-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S
  config: riscv-arch-tests

- test: caddi4spn-01
  desc: >
    riscv test - caddi4spn-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S
  config: riscv-arch-tests

- test: cand-01
  desc: >
    riscv test - cand-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cand-01.S
  config: riscv-arch-tests

- test: candi-01
  desc: >
    riscv test - candi-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/candi-01.S
  config: riscv-arch-tests

- test: cbeqz-01
  desc: >
    riscv test - cbeqz-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S
  config: riscv-arch-tests

- test: cbnez-01
  desc: >
    riscv test - cbnez-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cbnez-01.S
  config: riscv-arch-tests

- test: cebreak-01
  desc: >
    riscv test - cebreak-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cebreak-01.S
  config: riscv-arch-tests

- test: cj-01
  desc: >
    riscv test - cj-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cj-01.S
  config: riscv-arch-tests

- test: cjal-01
  desc: >
    riscv test - cjal-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjal-01.S
  config: riscv-arch-tests

- test: cjalr-01
  desc: >
    riscv test - cjalr-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjalr-01.S
  config: riscv-arch-tests

- test: cjr-01
  desc: >
    riscv test - cjr-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cjr-01.S
  config: riscv-arch-tests

- test: cli-01
  desc: >
    riscv test - cli-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cli-01.S
  config: riscv-arch-tests

- test: clui-01
  desc: >
    riscv test - clui-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clui-01.S
  config: riscv-arch-tests

- test: clw-01
  desc: >
    riscv test - clw-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clw-01.S
  config: riscv-arch-tests

- test: clwsp-01
  desc: >
    riscv test - clwsp-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/clwsp-01.S
  config: riscv-arch-tests

- test: cmv-01
  desc: >
    riscv test - cmv-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cmv-01.S
  config: riscv-arch-tests

- test: cnop-01
  desc: >
    riscv test - cnop-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cnop-01.S
  config: riscv-arch-tests

- test: cor-01
  desc: >
    riscv test - cor-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cor-01.S
  config: riscv-arch-tests

- test: cslli-01
  desc: >
    riscv test - cslli-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cslli-01.S
  config: riscv-arch-tests

- test: csrai-01
  desc: >
    riscv test - csrai-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csrai-01.S
  config: riscv-arch-tests

- test: csrli-01
  desc: >
    riscv test - csrli-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csrli-01.S
  config: riscv-arch-tests

- test: csub-01
  desc: >
    riscv test - csub-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csub-01.S
  config: riscv-arch-tests

- test: csw-01
  desc: >
    riscv test - csw-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/csw-01.S
  config: riscv-arch-tests

- test: cswsp-01
  desc: >
    riscv test - cswsp-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cswsp-01.S
  config: riscv-arch-tests

- test: cxor-01
  desc: >
    riscv test - cxor-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/C/src/cxor-01.S
  config: riscv-arch-tests

- test: Fencei
  desc: >
    riscv test - Fencei
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/Zifencei/src/Fencei.S
  config: riscv-arch-tests

- test: add-01
  desc: >
    riscv test - add-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/add-01.S
  config: riscv-arch-tests

- test: addi-01
  desc: >
    riscv test - addi-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/addi-01.S
  config: riscv-arch-tests

- test: and-01
  desc: >
    riscv test - and-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/and-01.S
  config: riscv-arch-tests

- test: andi-01
  desc: >
    riscv test - andi-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/andi-01.S
  config: riscv-arch-tests

- test: auipc-01
  desc: >
    riscv test - auipc-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/auipc-01.S
  config: riscv-arch-tests

- test: beq-01
  desc: >
    riscv test - beq-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/beq-01.S
  config: riscv-arch-tests

- test: bge-01
  desc: >
    riscv test - bge-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/bge-01.S
  config: riscv-arch-tests

- test: bgeu-01
  desc: >
    riscv test - bgeu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/bgeu-01.S
  config: riscv-arch-tests

- test: blt-01
  desc: >
    riscv test - blt-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/blt-01.S
  config: riscv-arch-tests

- test: bltu-01
  desc: >
    riscv test - bltu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/bltu-01.S
  config: riscv-arch-tests

- test: bne-01
  desc: >
    riscv test - bne-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/bne-01.S
  config: riscv-arch-tests

- test: fence-01
  desc: >
    riscv test - fence-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/fence-01.S
  config: riscv-arch-tests

- test: jal-01
  desc: >
    riscv test - jal-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/jal-01.S
  config: riscv-arch-tests

- test: jalr-01
  desc: >
    riscv test - jalr-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/jalr-01.S
  config: riscv-arch-tests

- test: lb-align-01
  desc: >
    riscv test - lb-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/lb-align-01.S
  config: riscv-arch-tests

- test: lbu-align-01
  desc: >
    riscv test - lbu-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S
  config: riscv-arch-tests

- test: lh-align-01
  desc: >
    riscv test - lh-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/lh-align-01.S
  config: riscv-arch-tests

- test: lhu-align-01
  desc: >
    riscv test - lhu-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S
  config: riscv-arch-tests

- test: lui-01
  desc: >
    riscv test - lui-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/lui-01.S
  config: riscv-arch-tests

- test: lw-align-01
  desc: >
    riscv test - lw-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/lw-align-01.S
  config: riscv-arch-tests

- test: misalign1-jalr-01
  desc: >
    riscv test - misalign1-jalr-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/misalign1-jalr-01.S
  config: riscv-arch-tests

- test: or-01
  desc: >
    riscv test - or-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/or-01.S
  config: riscv-arch-tests

- test: ori-01
  desc: >
    riscv test - ori-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/ori-01.S
  config: riscv-arch-tests

- test: sb-align-01
  desc: >
    riscv test - sb-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sb-align-01.S
  config: riscv-arch-tests

- test: sh-align-01
  desc: >
    riscv test - sh-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sh-align-01.S
  config: riscv-arch-tests

- test: sll-01
  desc: >
    riscv test - sll-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sll-01.S
  config: riscv-arch-tests

- test: slli-01
  desc: >
    riscv test - slli-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/slli-01.S
  config: riscv-arch-tests

- test: slt-01
  desc: >
    riscv test - slt-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/slt-01.S
  config: riscv-arch-tests

- test: slti-01
  desc: >
    riscv test - slti-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/slti-01.S
  config: riscv-arch-tests

- test: sltiu-01
  desc: >
    riscv test - sltiu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sltiu-01.S
  config: riscv-arch-tests

- test: sltu-01
  desc: >
    riscv test - sltu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sltu-01.S
  config: riscv-arch-tests

- test: sra-01
  desc: >
    riscv test - sra-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sra-01.S
  config: riscv-arch-tests

- test: srai-01
  desc: >
    riscv test - srai-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/srai-01.S
  config: riscv-arch-tests

- test: srl-01
  desc: >
    riscv test - srl-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/srl-01.S
  config: riscv-arch-tests

- test: srli-01
  desc: >
    riscv test - srli-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/srli-01.S
  config: riscv-arch-tests

- test: sub-01
  desc: >
    riscv test - sub-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sub-01.S
  config: riscv-arch-tests

- test: sw-align-01
  desc: >
    riscv test - sw-align-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/sw-align-01.S
  config: riscv-arch-tests

- test: xor-01
  desc: >
    riscv test - xor-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/xor-01.S
  config: riscv-arch-tests

- test: xori-01
  desc: >
    riscv test - xori-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/I/src/xori-01.S
  config: riscv-arch-tests

- test: andn-01
  desc: >
    riscv test - andn-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/andn-01.S
  config: riscv-arch-tests

- test: bclr-01
  desc: >
    riscv test - bclr-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bclr-01.S
  config: riscv-arch-tests

- test: bclri-01
  desc: >
    riscv test - bclri-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bclri-01.S
  config: riscv-arch-tests

- test: bext-01
  desc: >
    riscv test - bext-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bext-01.S
  config: riscv-arch-tests

- test: bexti-01
  desc: >
    riscv test - bexti-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bexti-01.S
  config: riscv-arch-tests

- test: binv-01
  desc: >
    riscv test - binv-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/binv-01.S
  config: riscv-arch-tests

- test: binvi-01
  desc: >
    riscv test - binvi-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/binvi-01.S
  config: riscv-arch-tests

- test: bset-01
  desc: >
    riscv test - bset-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bset-01.S
  config: riscv-arch-tests

- test: bseti-01
  desc: >
    riscv test - bseti-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/bseti-01.S
  config: riscv-arch-tests

- test: clmul-01
  desc: >
    riscv test - clmul-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmul-01.S
  config: riscv-arch-tests

- test: clmulh-01
  desc: >
    riscv test - clmulh-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmulh-01.S
  config: riscv-arch-tests

- test: clmulr-01
  desc: >
    riscv test - clmulr-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clmulr-01.S
  config: riscv-arch-tests

- test: clz-01
  desc: >
    riscv test - clz-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/clz-01.S
  config: riscv-arch-tests

- test: cpop-01
  desc: >
    riscv test - cpop-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/cpop-01.S
  config: riscv-arch-tests

- test: ctz-01
  desc: >
    riscv test - ctz-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/ctz-01.S
  config: riscv-arch-tests

- test: max-01
  desc: >
    riscv test - max-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/max-01.S
  config: riscv-arch-tests

- test: maxu-01
  desc: >
    riscv test - maxu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/maxu-01.S
  config: riscv-arch-tests

- test: min-01
  desc: >
    riscv test - min-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/min-01.S
  config: riscv-arch-tests

- test: minu-01
  desc: >
    riscv test - minu-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/minu-01.S
  config: riscv-arch-tests

- test: orcb_32-01
  desc: >
    riscv test - orcb_32-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/orcb_32-01.S
  config: riscv-arch-tests

- test: orn-01
  desc: >
    riscv test - orn-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/orn-01.S
  config: riscv-arch-tests

- test: rev8_32-01
  desc: >
    riscv test - rev8_32-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rev8_32-01.S
  config: riscv-arch-tests

- test: rol-01
  desc: >
    riscv test - rol-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rol-01.S
  config: riscv-arch-tests

- test: ror-01
  desc: >
    riscv test - ror-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/ror-01.S
  config: riscv-arch-tests

- test: rori-01
  desc: >
    riscv test - rori-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/rori-01.S
  config: riscv-arch-tests

- test: sext-b-01
  desc: >
    riscv test - sext-b-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sext-b-01.S
  config: riscv-arch-tests

- test: sext-h-01
  desc: >
    riscv test - sext-h-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sext-h-01.S
  config: riscv-arch-tests

- test: sh1add-01
  desc: >
    riscv test - sh1add-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh1add-01.S
  config: riscv-arch-tests

- test: sh2add-01
  desc: >
    riscv test - sh2add-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh2add-01.S
  config: riscv-arch-tests

- test: sh3add-01
  desc: >
    riscv test - sh3add-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/sh3add-01.S
  config: riscv-arch-tests

- test: xnor-01
  desc: >
    riscv test - xnor-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/xnor-01.S
  config: riscv-arch-tests

- test: zext-h_32-01
  desc: >
    riscv test - zext-h_32-01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/B/src/zext-h_32-01.S
  config: riscv-arch-tests

# Test-suite: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp0_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb0_mmwp1_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp0_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock00_rlb1_mmwp1_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp0_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb0_mmwp1_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp0_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock01_rlb1_mmwp1_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp0_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb0_mmwp1_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp0_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml0_sec_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_07.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_11
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_11
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_11.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_12
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_12
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_12.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_13
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_13
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_13.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_14
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_14
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_14.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_15
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_15
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_15.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_16
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_16
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_16.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_17
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_17
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_pmp_17.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_00
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_00
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_00.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_01
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_01
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_01.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_02
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_02
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_02.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_03
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_03
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_03.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_04
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_04
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_04.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_05
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_05
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_05.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_06
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_06
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_06.c
  config: epmp-tests

- test: test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_07
  desc: >
    riscv test - test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_07
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_csr_1_lock10_rlb1_mmwp1_mml1_sec_07.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x0_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw00_x1_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x0_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw10_x1_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x0_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u0_rw11_x1_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x0_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw00_x1_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x0_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw10_x1_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x0_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l0_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match0_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp0_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp0_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp0_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp0_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp0_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp0_mml1.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp1_mml0
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp1_mml0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp1_mml0.c
  config: epmp-tests

- test: test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp1_mml1
  desc: >
    riscv test - test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp1_mml1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_1_u1_rw11_x1_l1_match1_mmwp1_mml1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl0_typex0_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl0_typex0_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl0_typex0_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl0_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl0_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl0_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl0_typex1_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl0_typex1_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl0_typex1_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl0_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl0_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl0_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl1_typex0_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl1_typex0_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl1_typex0_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl1_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl1_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl1_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl1_typex1_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl1_typex1_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl1_typex1_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x0_cfgl1_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x0_cfgl1_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x0_cfgl1_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl0_typex0_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl0_typex0_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl0_typex0_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl0_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl0_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl0_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl0_typex1_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl0_typex1_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl0_typex1_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl0_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl0_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl0_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl1_typex0_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl1_typex0_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl1_typex0_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl1_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl1_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl1_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl1_typex1_umode0
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl1_typex1_umode0
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl1_typex1_umode0.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r0_x1_cfgl1_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r0_x1_cfgl1_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r0_x1_cfgl1_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x0_cfgl0_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x0_cfgl0_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x0_cfgl0_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x0_cfgl0_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x0_cfgl0_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x0_cfgl0_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x0_cfgl1_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x0_cfgl1_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x0_cfgl1_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x0_cfgl1_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x0_cfgl1_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x0_cfgl1_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x1_cfgl0_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x1_cfgl0_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x1_cfgl0_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x1_cfgl0_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x1_cfgl0_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x1_cfgl0_typex1_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x1_cfgl1_typex0_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x1_cfgl1_typex0_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x1_cfgl1_typex0_umode1.c
  config: epmp-tests

- test: test_pmp_ok_share_1_r1_x1_cfgl1_typex1_umode1
  desc: >
    riscv test - test_pmp_ok_share_1_r1_x1_cfgl1_typex1_umode1
  iterations: 1
  test_srcs: ../../../../vendor/riscv-isa-sim/tests/mseccfg/gengen_src/outputs/test_pmp_ok_share_1_r1_x1_cfgl1_typex1_umode1.c
  config: epmp-tests
