diff --git a/fpv/tb/prim_fifo_async_sram_adapter_tb.sv b/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
index cb02d7f3..234e5faf 100644
--- a/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
+++ b/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
@@ -128,7 +128,7 @@ if (FpgaSram == 1) begin : g_sram_fpga
     .b_rdata_o (r_sram_rdata ),
 
     .cfg_i     ('0),
-    .cfg_rsp_o ()
+    .cfg_o     ()
   );
 end else begin : g_sram_ff
   logic [SramDw-1:0] mem [2**SramAw];
diff --git a/rtl/prim_ram_1p_adv.sv b/rtl/prim_ram_1p_adv.sv
index 83087d2b..729e04d9 100644
--- a/rtl/prim_ram_1p_adv.sv
+++ b/rtl/prim_ram_1p_adv.sv
@@ -53,8 +53,8 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
   output logic [1:0]                  rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
   // config
-  input  ram_1p_cfg_t     [NumRamInst-1:0] cfg_i,
-  output ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_rsp_o,
+  input  ram_1p_cfg_req_t [NumRamInst-1:0] cfg_i,
+  output ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_o,
 
   // When detecting multi-bit encoding errors, raise alert.
   output logic                             alert_o
@@ -165,7 +165,7 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
       .wmask_i   (wmask_q),
       .rdata_o   (inst_rdata[i]),
       .cfg_i     (cfg_i[i]),
-      .cfg_rsp_o (cfg_rsp_o[i])
+      .cfg_o     (cfg_o[i])
     );
   end
 
diff --git a/rtl/prim_ram_1p_scr.sv b/rtl/prim_ram_1p_scr.sv
index 16a0732c..5ab1f600 100644
--- a/rtl/prim_ram_1p_scr.sv
+++ b/rtl/prim_ram_1p_scr.sv
@@ -86,8 +86,8 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
   output logic [AddrWidth-1:0]             raddr_o,  // Read address for error reporting.
 
   // config
-  input  ram_1p_cfg_t     [NumRamInst-1:0] cfg_i,
-  output ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_rsp_o,
+  input  ram_1p_cfg_req_t [NumRamInst-1:0] cfg_i,
+  output ram_1p_cfg_rsp_t [NumRamInst-1:0] cfg_o,
 
 
   // Write currently pending inside this module.
@@ -505,7 +505,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
     .rvalid_o ( ),
     .rerror_o,
     .cfg_i,
-    .cfg_rsp_o,
+    .cfg_o,
     .alert_o  ( ram_alert   )
   );
 
diff --git a/rtl/prim_ram_1r1w_adv.sv b/rtl/prim_ram_1r1w_adv.sv
index ff0511f1..9e5799c1 100644
--- a/rtl/prim_ram_1r1w_adv.sv
+++ b/rtl/prim_ram_1r1w_adv.sv
@@ -15,7 +15,7 @@
 
 `include "prim_assert.sv"
 
-module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
+module prim_ram_1r1w_adv import prim_ram_1r1w_pkg::*; #(
   parameter  int Depth                = 512,
   parameter  int Width                = 32,
   parameter  int DataBitsPerMask      = 1,  // Number of data bits per bit of write mask
@@ -50,8 +50,8 @@ module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
   output logic             b_rvalid_o, // read response (b_rdata_o) is valid
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
-  input  ram_2p_cfg_t      cfg_i,
-  output ram_2p_cfg_rsp_t  cfg_rsp_o
+  input  ram_1r1w_cfg_req_t cfg_i,
+  output ram_1r1w_cfg_rsp_t cfg_o
 );
 
   prim_ram_1r1w_async_adv #(
@@ -79,7 +79,7 @@ module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
     .b_rvalid_o,
     .b_rerror_o,
     .cfg_i,
-    .cfg_rsp_o
+    .cfg_o
   );
 
 endmodule : prim_ram_1r1w_adv
diff --git a/rtl/prim_ram_1r1w_async_adv.sv b/rtl/prim_ram_1r1w_async_adv.sv
index 40e06976..93ed0665 100644
--- a/rtl/prim_ram_1r1w_async_adv.sv
+++ b/rtl/prim_ram_1r1w_async_adv.sv
@@ -15,7 +15,7 @@
 
 `include "prim_assert.sv"
 
-module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
+module prim_ram_1r1w_async_adv import prim_ram_1r1w_pkg::*; #(
   parameter  int Depth                = 512,
   parameter  int Width                = 32,
   parameter  int DataBitsPerMask      = 1,  // Number of data bits per bit of write mask
@@ -53,8 +53,8 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
   // config
-  input  ram_2p_cfg_t      cfg_i,
-  output ram_2p_cfg_rsp_t  cfg_rsp_o
+  input  ram_1r1w_cfg_req_t cfg_i,
+  output ram_1r1w_cfg_rsp_t cfg_o
 );
 
 
@@ -115,7 +115,7 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
     .b_rdata_o  (b_rdata_sram),
 
     .cfg_i,
-    .cfg_rsp_o
+    .cfg_o
   );
 
   always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
diff --git a/rtl/prim_ram_2p_adv.sv b/rtl/prim_ram_2p_adv.sv
index 951ae981..24b17ec6 100644
--- a/rtl/prim_ram_2p_adv.sv
+++ b/rtl/prim_ram_2p_adv.sv
@@ -55,7 +55,8 @@ module prim_ram_2p_adv import prim_ram_2p_pkg::*; #(
   output logic             b_rvalid_o, // read response (b_rdata_o) is valid
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
-  input ram_2p_cfg_t       cfg_i
+  input  ram_2p_cfg_req_t  cfg_i,
+  output ram_2p_cfg_rsp_t  cfg_o
 );
 
   prim_ram_2p_async_adv #(
@@ -89,7 +90,8 @@ module prim_ram_2p_adv import prim_ram_2p_pkg::*; #(
     .b_rdata_o,
     .b_rvalid_o,
     .b_rerror_o,
-    .cfg_i
+    .cfg_i,
+    .cfg_o
   );
 
 endmodule : prim_ram_2p_adv
diff --git a/rtl/prim_ram_2p_async_adv.sv b/rtl/prim_ram_2p_async_adv.sv
index 79f1a619..32c65d54 100644
--- a/rtl/prim_ram_2p_async_adv.sv
+++ b/rtl/prim_ram_2p_async_adv.sv
@@ -58,8 +58,8 @@ module prim_ram_2p_async_adv import prim_ram_2p_pkg::*; #(
   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
   // config
-  input  ram_2p_cfg_t      cfg_i,
-  output ram_2p_cfg_rsp_t  cfg_rsp_o
+  input  ram_2p_cfg_req_t  cfg_i,
+  output ram_2p_cfg_rsp_t  cfg_o
 );
 
 
@@ -131,7 +131,7 @@ module prim_ram_2p_async_adv import prim_ram_2p_pkg::*; #(
     .b_rdata_o  (b_rdata_sram),
 
     .cfg_i,
-    .cfg_rsp_o
+    .cfg_o
   );
 
   always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
