diff --git a/rtl/prim_ram_1p.sv b/rtl/prim_ram_1p.sv
index 742d56ba..84a5f09d 100644
--- a/rtl/prim_ram_1p.sv
+++ b/rtl/prim_ram_1p.sv
@@ -23,8 +23,8 @@ module prim_ram_1p import prim_ram_1p_pkg::*; #(
   input  logic [Width-1:0] wdata_i,
   input  logic [Width-1:0] wmask_i,
   output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i is high.
-  input ram_1p_cfg_t       cfg_i,
-  output ram_1p_cfg_rsp_t  cfg_rsp_o
+  input ram_1p_cfg_req_t   cfg_i,
+  output ram_1p_cfg_rsp_t  cfg_o
 );
 
   localparam int PrimMaxWidth = prim_xilinx_pkg::get_ram_max_width(Width, Depth);
@@ -70,7 +70,7 @@ module prim_ram_1p import prim_ram_1p_pkg::*; #(
 
     logic unused_signals;
     assign unused_signals = ^{rst_ni, cfg_i};
-    assign cfg_rsp_o      = '0;
+    assign cfg_o          = RAM_1P_CFG_RSP_DEFAULT;
 
     for (genvar k = 0; k < Width; k = k + PrimMaxWidth) begin : gen_split
       localparam int PrimWidth = ((Width - k) > PrimMaxWidth) ? PrimMaxWidth : Width - k;
