# Instruction Decode

The Instruction Decode stage translates the RISC-V instruction fetched by the previous stage into operands and controls that can be acted upon in the subsequent stages. The Decode stage also catches illegal instructions and misaligned jumps and load/store. The exception is acted upon at the Execute stage.


## ALU Operation

The ALU in the Execute stage takes two operands, `OP1` and `OP2`. The default decode for these operands is `PC` and constant 4, respectively. The default ALU operation is ADD.

Instr  | OP1     | OP2     | ALUOP   |
-------|---------|---------|---------|
Default| PC      | 4       | ADD     |
LUI    | 0       | Imm     | ADD     |
AUIPC  | PC      | Imm     | ADD     |
JAL    | PC      | 4       | ADD     |
JALR   | PC      | 4       | ADD     |
STORE  | PC*     | REG[rs2]| ADD     |
OP     | REG[rs1]| REG[rs2]| {funct7[5], funct3}   |
OPIMM  | REG[rs1]| Imm     | {1'b0**, funct3}   |

The ALU ops are extracted from the `funct3` and `funct7`.

> \* For store instructions, only the OP2 is passed along to the Load Store Unit. The ALU is not used.

>** For shift OPIMM instructions, this takes `funct7[5]`, else it is zero.

## Address Generation

A 32b adder is present at the decode stage to calculate the address for instructions that need it. Looking at the below table and the one above, you can witness the sheer elegance of the RISC-V ISA.

Instr  | base    | offset  | Use     |
-------|---------|---------|---------| 
JAL    | PC      | Imm     | Jump address |
JALR   | REG[rs1]| Imm     | Jump address |
BRANCH | PC      | Imm     | Branch target, if branch condition is true |
LOAD   | REG[rs1]| Imm     | Memory read address |
STORE  | REG[rs1]| Imm     | Memory write address |

## Branch Comparison

The register operands are compared as per the branch instruction to generate a single bit assertion if the instruction needs to branch to the address generated by the AGU.

## Store Data

![sram read](_images/kronos_store.svg)

For data store instructions, the write data is rotated and aligned for a quick LSU store operation. The LSU simply forwards the decoded store data and mask for a simple write operation.

## System Instructions

System instructions (CSR, ECALL, EBREAK, MRET and WFI) are forwarded to the Execute stage as is to work on. For the CSR instructions, the operation and Zimm (zero-extended 5b immediate) is present in the instruction.

## Hazard Control

The Decode stage also has a small Hazard Control Unit (HCU). It is the singular point of read-before-write detection in the entire pipeline. These hazards occur when a register is being read before it's latest value is written back from the Write Back stage (direct write, load or CSR read data). The HCU monitors the register read requirement of the current instruction being decoded, and can stall the Decode if there are writes pending to those registers.

In the Kronos pipeline, there is only one stage ahead of the Decoder. Hence, there can be a maximum of one pending write to any register.

When the register write back is valid, the latest value is forwarded as register operands (if the source matches).