Workspace

	.git
	.Xil
	doc
	fpga
	openocd
	simulation/modelsim
	tools
	verilog
	workspace
	build_digilent_arty_a7_100t.tcl	Sep 10, 2026, 5:19:42 AM	3.05 KiB
	LICENSE	Sep 10, 2026, 5:19:30 AM	1.30 KiB
	processor_ci_defines.vh	Sep 10, 2026, 5:19:42 AM	300 B
	README.md	Sep 10, 2026, 5:19:30 AM	11.34 KiB
(all files in zip)