Skip to content

Workspace

/ mor1kx /
.git
.github/workflows
.Xil
bench
doc
rtl/verilog
.gitignoreSep 8, 2026, 5:13:04 AM6 B
build_digilent_arty_a7_100t.tclSep 8, 2026, 5:13:10 AM6.50 KiB
clockInfo.txtSep 8, 2026, 5:15:15 AM375 B
digilent_arty_a7_100t.bitSep 8, 2026, 5:16:32 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 8, 2026, 5:15:28 AM21.62 KiB
digilent_arty_a7_control_sets.rptSep 8, 2026, 5:15:27 AM44.83 KiB
digilent_arty_a7_drc.rptSep 8, 2026, 5:16:09 AM9.56 KiB
digilent_arty_a7_io.rptSep 8, 2026, 5:15:27 AM96.81 KiB
digilent_arty_a7_power.rptSep 8, 2026, 5:16:12 AM8.90 KiB
digilent_arty_a7_route_status.rptSep 8, 2026, 5:16:07 AM651 B
digilent_arty_a7_timing.rptSep 8, 2026, 5:16:10 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 8, 2026, 5:15:26 AM13.56 KiB
digilent_arty_a7_utilization_place.rptSep 8, 2026, 5:15:26 AM11.30 KiB
JenkinsfileSep 8, 2026, 5:13:04 AM1.93 KiB
LICENSESep 8, 2026, 5:13:04 AM14.20 KiB
mor1kx.coreSep 8, 2026, 5:13:04 AM6.35 KiB
processor_ci_defines.vhSep 8, 2026, 5:13:10 AM300 B
README.mdSep 8, 2026, 5:13:04 AM10.33 KiB