Skip to content

Workspace

/ mor1kx /
.git
.github/workflows
.Xil
bench
doc
rtl/verilog
.gitignoreSep 4, 2026, 5:13:06 AM6 B
build_digilent_arty_a7_100t.tclSep 4, 2026, 5:13:15 AM6.50 KiB
clockInfo.txtSep 4, 2026, 5:15:20 AM375 B
digilent_arty_a7_100t.bitSep 4, 2026, 5:16:37 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 4, 2026, 5:15:34 AM21.62 KiB
digilent_arty_a7_control_sets.rptSep 4, 2026, 5:15:33 AM44.83 KiB
digilent_arty_a7_drc.rptSep 4, 2026, 5:16:15 AM9.56 KiB
digilent_arty_a7_io.rptSep 4, 2026, 5:15:33 AM96.81 KiB
digilent_arty_a7_power.rptSep 4, 2026, 5:16:17 AM8.90 KiB
digilent_arty_a7_route_status.rptSep 4, 2026, 5:16:13 AM651 B
digilent_arty_a7_timing.rptSep 4, 2026, 5:16:15 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 4, 2026, 5:15:33 AM13.56 KiB
digilent_arty_a7_utilization_place.rptSep 4, 2026, 5:15:33 AM11.30 KiB
JenkinsfileSep 4, 2026, 5:13:06 AM1.93 KiB
LICENSESep 4, 2026, 5:13:06 AM14.20 KiB
mor1kx.coreSep 4, 2026, 5:13:06 AM6.35 KiB
processor_ci_defines.vhSep 4, 2026, 5:13:15 AM300 B
README.mdSep 4, 2026, 5:13:06 AM10.33 KiB