MR1 
===

A hobby RISC-V CPU core to learn riscv-formal and SpinalHDL.

See my write-up here: [A Bug Free RISC-V Core without Simulation](https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html).

While this core works and has passed the riscv-formal test suite, it's not nearly as good as the
[VexRiscv](https://github.com/SpinalHDL/VexRiscv) core, which is smaller, synthesizes with higher clocks,
and has better IPC even in slow configurations.