Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Wed Aug  5 00:41:42 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    74 |
|    Minimum number of control sets                        |    74 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   153 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    74 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |    12 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    43 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              47 |           25 |
| No           | No                    | Yes                    |               9 |            4 |
| No           | Yes                   | No                     |             511 |          176 |
| Yes          | No                    | No                     |             261 |           87 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |             867 |          271 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                            Enable Signal                            |                          Set/Reset Signal                          | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------+------------------+----------------+--------------+
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        |                                                                    |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0                   |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG                       |                                                                     |                                                                    |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                 |                                                                    |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0            |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0         |                2 |              4 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/u_Controller/Interpreter/SR[0]                                |                3 |              5 |         1.67 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                             |                                                                    |                2 |              5 |         2.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                                        |                2 |              5 |         2.50 |
|  clk_o_BUFG                          |                                                                     |                                                                    |                4 |              5 |         1.25 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u1/FSM_sequential_state_reg[1]_2[0]  | ptop/mriscvcore_inst/MULT_inst/cont1[4]_i_1_n_0                    |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u5/E[0]                              | ptop/mriscvcore_inst/MULT_inst/cont3[4]_i_1_n_0                    |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/mriscvcore_inst/MEMORY_INTERFACE_inst/inst_reg[0]_2           |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u3/E[0]                              | ptop/mriscvcore_inst/MULT_inst/cont2[4]_i_1_n_0                    |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/mriscvcore_inst/MEMORY_INTERFACE_inst/inst_reg[4]_2           |                3 |              5 |         1.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                        |                2 |              7 |         3.50 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/mriscvcore_inst/UTILITY_inst/TIME[0]_i_1_n_0                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/counter_write_reg[2][0]              | ResetBootSystem/rst_o_reg_0                                        |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                                        |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                                        |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                                        |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0          |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                        |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                        |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                              |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1_n_0          |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                            | ResetBootSystem/rst_o_reg_0                                        |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                        |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                                    |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                                    |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                                    |                5 |             12 |         2.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u5/OutFSM3[0]                        | ptop/u_Controller/Interpreter/rst_core                             |                4 |             16 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u1/OutFSM1[0]                        | ptop/u_Controller/Interpreter/rst_core                             |                3 |             16 |         5.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u3/OutFSM2[0]                        | ptop/u_Controller/Interpreter/rst_core                             |                5 |             17 |         3.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u1/E[0]                              | ptop/mriscvcore_inst/MULT_inst/u1/SR[0]                            |                7 |             17 |         2.43 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u1/E[0]                              | ptop/u_Controller/Interpreter/rst_core                             |                7 |             17 |         2.43 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u5/FSM_sequential_state_reg[1]_1[0]  | ptop/mriscvcore_inst/MULT_inst/u5/SR[0]                            |                5 |             17 |         3.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u5/FSM_sequential_state_reg[1]_1[0]  | ptop/u_Controller/Interpreter/rst_core                             |                7 |             17 |         2.43 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u3/FSM_sequential_state_reg[1]_1[0]  | ptop/mriscvcore_inst/MULT_inst/u3/SR[0]                            |                6 |             18 |         3.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MULT_inst/u3/FSM_sequential_state_reg[1]_1[0]  | ptop/u_Controller/Interpreter/rst_core                             |               11 |             18 |         1.64 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0       |                6 |             23 |         3.83 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                                        |                5 |             24 |         4.80 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                          | ResetBootSystem/rst_o_reg_0                                        |                5 |             24 |         4.80 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0    |                                                                    |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                                        |                4 |             24 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                |                                                                    |               16 |             32 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                                        |                9 |             32 |         3.56 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                        |               10 |             32 |         3.20 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                                    |               15 |             32 |         2.13 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                        |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                                        |                6 |             32 |         5.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/bridge_inst/wb_dat_o[31]_i_1_n_0                               |                                                                    |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0] | ResetBootSystem/rst_o_reg_0                                        |                4 |             32 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/bridge_inst/wb_adr_o[31]_i_1_n_0                               |                                                                    |                5 |             32 |         6.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/bridge_inst/RDATA[31]_i_1_n_0                                  |                                                                    |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/MEMORY_INTERFACE_inst/inst0                    | ptop/u_Controller/Interpreter/rst_core                             |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                        |                9 |             32 |         3.56 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                           | ResetBootSystem/rst_o_reg_0                                        |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     |                                                                    |               20 |             41 |         2.05 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                                    |               14 |             55 |         3.93 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/UTILITY_inst/REAL_TIME                         | ptop/u_Controller/Interpreter/rst_core                             |               16 |             64 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/mriscvcore_inst/MULT_inst/u3/FSM_sequential_state_reg[0]_0[0] |               20 |             64 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/FSM_inst/enable_pc                             | ptop/u_Controller/Interpreter/rst_core                             |               41 |             96 |         2.34 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/mriscvcore_inst/ALU_inst/ALU_sXXx_inst/count_0                 | ptop/u_Controller/Interpreter/rst_core                             |               33 |            101 |         3.06 |
|  clk_o_BUFG                          |                                                                     | ResetBootSystem/rst_o_reg_0                                        |               43 |            118 |         2.74 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_5                    |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_4                    |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_3                    |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_2                    |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_1                    |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_0                    |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]                      |                                                                    |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/wb_adr_o_reg[12]_6                    |                                                                    |               32 |            128 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/u_Controller/Interpreter/rst_core                             |              107 |            316 |         2.95 |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------+------------------+----------------+--------------+


