Skip to content

Workspace

/ mriscv /
.git
.Xil
board
mriscv_apb
mriscv_axi
mriscvcore
.gitignoreJul 27, 2026, 4:39:54 AM537 B
.gitmodulesJul 27, 2026, 4:39:54 AM95 B
build_digilent_arty_a7_100t.tclJul 27, 2026, 4:40:32 AM2.93 KiB
clockInfo.txtJul 27, 2026, 4:41:51 AM375 B
demo1.pdfJul 27, 2026, 4:39:54 AM571.17 KiB
digilent_arty_a7_100t.bitJul 27, 2026, 4:42:56 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 27, 2026, 4:42:00 AM20.75 KiB
digilent_arty_a7_control_sets.rptJul 27, 2026, 4:41:59 AM20.83 KiB
digilent_arty_a7_drc.rptJul 27, 2026, 4:42:35 AM17.11 KiB
digilent_arty_a7_io.rptJul 27, 2026, 4:41:59 AM96.81 KiB
digilent_arty_a7_power.rptJul 27, 2026, 4:42:37 AM8.83 KiB
digilent_arty_a7_route_status.rptJul 27, 2026, 4:42:34 AM651 B
digilent_arty_a7_timing.rptJul 27, 2026, 4:42:35 AM22.75 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 27, 2026, 4:41:59 AM7.67 KiB
digilent_arty_a7_utilization_place.rptJul 27, 2026, 4:41:59 AM10.74 KiB
fully-synthesized-trng.pdfJul 27, 2026, 4:39:54 AM1.02 MiB
LICENSEJul 27, 2026, 4:39:54 AM2.43 KiB
mriscv.jpgJul 27, 2026, 4:39:54 AM44.89 KiB
mriscv.pdfJul 27, 2026, 4:39:54 AM3.79 MiB
PID4063257.pdfJul 27, 2026, 4:39:54 AM297.13 KiB
processor_ci_defines.vhJul 27, 2026, 4:40:32 AM300 B
README.mdJul 27, 2026, 4:39:54 AM2.12 KiB