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==== Data Memory (DMEM)

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|=======================
| Hardware source files:  | neorv32_dmem.vhd     | generic processor-internal data memory (RAM)
|                         | neorv32_dmem_ram.vhd | RAM component (primitive/IP wrapper)
| Software driver files:  | none                 |
| Top entity ports:       | none                 |
| Configuration generics: | `DMEM_EN`            | implement DMEM when `true`
|                         | `DMEM_BASE`          | 32-bit base address (naturally aligned to DMEM size)
|                         | `DMEM_SIZE`          | DMEM size in bytes (use a power of 2)
|                         | `DMEM_OUTREG_EN`     | add DMEM output register stage
| CPU interrupts:         | none                 |
|=======================

**Key Features**

* Burst-capable tightly-coupled on-chip data memory
* Configurable RAM size
* Accessible at the byte level
* Can also be used for executing code
* Mapped to memory primitives
* Optional output register for improved timing


**Overview**

Implementation of the processor-internal data memory is enabled by the processor's `DMEM_EN`
generic. The total memory size in bytes is defined via the `DMEM_SIZE` generic. Only sizes that
are powers of two are supported. If enabled, the DMEM is mapped to base address `0x80000000`
by default (see section <<_address_space>>).

.Custom DMEM Base Address
[IMPORTANT]
The base address of the DMEM can be customized via the `DMEM_BASE` generic. Please note that
the selected address must be naturally aligned to the DMEM size (`DMEM_SIZE`) and that there must
be no overlap with other sections of the internal <<_address_space>> (internal IMEM if enabled
and the internal IO/peripheral address space). Any non-default address must also be passed to the
<<_linker_script>> (e.g. `USER_FLAGS += -Wl,--defsym,__neorv32_ram_base=<DMEM_BASE>`).

.Platform-Specific Memory Primitives
[NOTE]
If required, the default DMEM can be replaced by a platform-/technology-specific primitive to
optimize area utilization, timing and power consumption.

.Output Register Stage
[TIP]
An optional output register stage can be enabled via `DMEM_OUTREG_EN`. For FPGA targets this might improve
mapping/timing results. Note that this option will increase the read latency by one clock cycle. Write accesses
are not affected by this at all.

.Retrieve Memory Configuration by Software
[TIP]
Software can retrieve the DMEM size from the <<_sysinfo_miscellaneous_configuration>> register.

.Memory Primitives
[TIP]
The memory's memory core is encapsulated as individual wrapper (`neorv32_dmem_ram.vhd`) that can be
replaced by a technology-specific IP. All interface ports provide static signal widths to ease replacement.
