<?xml version="1.0" encoding="utf-8"?>

<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
  <vendor>github.com/stnolting/neorv32</vendor>
  <name>neorv32</name>
  <series>RISC-V</series>
  <version>1.13.3</version>
  <description>The NEORV32 RISC-V Processor</description>

  <!-- CPU core -->
  <cpu>
    <name>other</name>
    <revision>r1p0</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>true</fpuPresent>
    <fpuDP>false</fpuDP>
    <dspPresent>false</dspPresent>
    <icachePresent>true</icachePresent>
    <dcachePresent>true</dcachePresent>
    <itcmPresent>true</itcmPresent>
    <dtcmPresent>true</dtcmPresent>
    <nvicPrioBits>4</nvicPrioBits>
  </cpu>

  <!-- defaults for all peripherals -->
  <addressUnitBits>16</addressUnitBits>
  <width>32</width>
  <size>32</size>
  <access>read-write</access>
  <resetValue>0x00000000</resetValue>
  <resetMask>0xffffffff</resetMask>

  <!-- Peripherals -->
  <peripherals>

    <!-- **************************************************************** -->
    <!-- CFS                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>CFS</name>
      <description>Custom functions subsystem</description>
      <baseAddress>0xFFEB0000</baseAddress>

      <interrupt><name>CFS_FIRQ</name><value>1</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x10000</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register><name>REG0</name><description>User-defined</description><addressOffset>0x00</addressOffset></register>
        <register><name>REG1</name><description>User-defined</description><addressOffset>0x04</addressOffset></register>
        <register><name>REG2</name><description>User-defined</description><addressOffset>0x08</addressOffset></register>
        <register><name>REG3</name><description>User-defined</description><addressOffset>0x0C</addressOffset></register>
        <register><name>REG4</name><description>User-defined</description><addressOffset>0x10</addressOffset></register>
        <register><name>REG5</name><description>User-defined</description><addressOffset>0x14</addressOffset></register>
        <register><name>REG6</name><description>User-defined</description><addressOffset>0x18</addressOffset></register>
        <register><name>REG7</name><description>User-defined</description><addressOffset>0x1C</addressOffset></register>
        <register><name>REG8</name><description>User-defined</description><addressOffset>0x20</addressOffset></register>
        <register><name>REG9</name><description>User-defined</description><addressOffset>0x24</addressOffset></register>
        <register><name>REG10</name><description>User-defined</description><addressOffset>0x28</addressOffset></register>
        <register><name>REG11</name><description>User-defined</description><addressOffset>0x2C</addressOffset></register>
        <register><name>REG12</name><description>User-defined</description><addressOffset>0x30</addressOffset></register>
        <register><name>REG13</name><description>User-defined</description><addressOffset>0x34</addressOffset></register>
        <register><name>REG14</name><description>User-defined</description><addressOffset>0x38</addressOffset></register>
        <register><name>REG15</name><description>User-defined</description><addressOffset>0x3C</addressOffset></register>
        <register><name>REG16</name><description>User-defined</description><addressOffset>0x40</addressOffset></register>
        <register><name>REG17</name><description>User-defined</description><addressOffset>0x44</addressOffset></register>
        <register><name>REG18</name><description>User-defined</description><addressOffset>0x48</addressOffset></register>
        <register><name>REG19</name><description>User-defined</description><addressOffset>0x4C</addressOffset></register>
        <register><name>REG20</name><description>User-defined</description><addressOffset>0x50</addressOffset></register>
        <register><name>REG21</name><description>User-defined</description><addressOffset>0x54</addressOffset></register>
        <register><name>REG22</name><description>User-defined</description><addressOffset>0x58</addressOffset></register>
        <register><name>REG23</name><description>User-defined</description><addressOffset>0x5C</addressOffset></register>
        <register><name>REG24</name><description>User-defined</description><addressOffset>0x60</addressOffset></register>
        <register><name>REG25</name><description>User-defined</description><addressOffset>0x64</addressOffset></register>
        <register><name>REG26</name><description>User-defined</description><addressOffset>0x68</addressOffset></register>
        <register><name>REG27</name><description>User-defined</description><addressOffset>0x6C</addressOffset></register>
        <register><name>REG28</name><description>User-defined</description><addressOffset>0x70</addressOffset></register>
        <register><name>REG29</name><description>User-defined</description><addressOffset>0x74</addressOffset></register>
        <register><name>REG30</name><description>User-defined</description><addressOffset>0x78</addressOffset></register>
        <register><name>REG31</name><description>User-defined</description><addressOffset>0x7C</addressOffset></register>
        <register><name>REG32</name><description>User-defined</description><addressOffset>0x80</addressOffset></register>
        <register><name>REG33</name><description>User-defined</description><addressOffset>0x84</addressOffset></register>
        <register><name>REG34</name><description>User-defined</description><addressOffset>0x88</addressOffset></register>
        <register><name>REG35</name><description>User-defined</description><addressOffset>0x8C</addressOffset></register>
        <register><name>REG36</name><description>User-defined</description><addressOffset>0x90</addressOffset></register>
        <register><name>REG37</name><description>User-defined</description><addressOffset>0x94</addressOffset></register>
        <register><name>REG38</name><description>User-defined</description><addressOffset>0x98</addressOffset></register>
        <register><name>REG39</name><description>User-defined</description><addressOffset>0x9C</addressOffset></register>
        <register><name>REG40</name><description>User-defined</description><addressOffset>0xA0</addressOffset></register>
        <register><name>REG41</name><description>User-defined</description><addressOffset>0xA4</addressOffset></register>
        <register><name>REG42</name><description>User-defined</description><addressOffset>0xA8</addressOffset></register>
        <register><name>REG43</name><description>User-defined</description><addressOffset>0xAC</addressOffset></register>
        <register><name>REG44</name><description>User-defined</description><addressOffset>0xB0</addressOffset></register>
        <register><name>REG45</name><description>User-defined</description><addressOffset>0xB4</addressOffset></register>
        <register><name>REG46</name><description>User-defined</description><addressOffset>0xB8</addressOffset></register>
        <register><name>REG47</name><description>User-defined</description><addressOffset>0xBC</addressOffset></register>
        <register><name>REG48</name><description>User-defined</description><addressOffset>0xC0</addressOffset></register>
        <register><name>REG49</name><description>User-defined</description><addressOffset>0xC4</addressOffset></register>
        <register><name>REG50</name><description>User-defined</description><addressOffset>0xC8</addressOffset></register>
        <register><name>REG51</name><description>User-defined</description><addressOffset>0xCC</addressOffset></register>
        <register><name>REG52</name><description>User-defined</description><addressOffset>0xD0</addressOffset></register>
        <register><name>REG53</name><description>User-defined</description><addressOffset>0xD4</addressOffset></register>
        <register><name>REG54</name><description>User-defined</description><addressOffset>0xD8</addressOffset></register>
        <register><name>REG55</name><description>User-defined</description><addressOffset>0xDC</addressOffset></register>
        <register><name>REG56</name><description>User-defined</description><addressOffset>0xE0</addressOffset></register>
        <register><name>REG57</name><description>User-defined</description><addressOffset>0xE4</addressOffset></register>
        <register><name>REG58</name><description>User-defined</description><addressOffset>0xE8</addressOffset></register>
        <register><name>REG59</name><description>User-defined</description><addressOffset>0xEC</addressOffset></register>
        <register><name>REG60</name><description>User-defined</description><addressOffset>0xF0</addressOffset></register>
        <register><name>REG61</name><description>User-defined</description><addressOffset>0xF4</addressOffset></register>
        <register><name>REG62</name><description>User-defined</description><addressOffset>0xF8</addressOffset></register>
        <register><name>REG63</name><description>User-defined</description><addressOffset>0xFC</addressOffset></register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- SDI                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>SDI</name>
      <description>Serial data interface controller</description>
      <baseAddress>0xFFF70000</baseAddress>

      <interrupt><name>SDI_FIRQ</name><value>11</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>SDI_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>SDI enable</description>
            </field>
            <field>
              <name>SDI_CTRL_CLR_RX</name>
              <bitRange>[1:1]</bitRange>
              <access>write-only</access>
              <description>Clear RX FIFO, flag auto-clears</description>
            </field>
            <field>
              <name>SDI_CTRL_CLR_TX</name>
              <bitRange>[2:2]</bitRange>
              <access>write-only</access>
              <description>Clear TX FIFO, flag auto-clears</description>
            </field>
            <field>
              <name>SDI_CTRL_FIFO</name>
              <bitRange>[7:4]</bitRange>
              <description>log2(FIFO size)</description>
            </field>
            <field>
              <name>SDI_CTRL_IRQ_RX_NEMPTY</name>
              <bitRange>[16:16]</bitRange>
              <description>Fire interrupt if RX FIFO is not empty</description>
            </field>
            <field>
              <name>SDI_CTRL_IRQ_RX_FULL</name>
              <bitRange>[17:17]</bitRange>
              <description>Fire interrupt if RX FIFO is full</description>
            </field>
            <field>
              <name>SDI_CTRL_IRQ_TX_EMPTY</name>
              <bitRange>[18:18]</bitRange>
              <description>Fire interrupt if TX FIFO is empty</description>
            </field>
            <field>
              <name>SDI_CTRL_RX_EMPTY</name>
              <bitRange>[24:24]</bitRange>
              <access>read-only</access>
              <description>RX FIFO empty </description>
            </field>
            <field>
              <name>SDI_CTRL_RX_FULL</name>
              <bitRange>[25:25]</bitRange>
              <access>read-only</access>
              <description>RX FIFO full</description>
            </field>
            <field>
              <name>SDI_CTRL_TX_EMPTY</name>
              <bitRange>[26:26]</bitRange>
              <access>read-only</access>
              <description>TX FIFO empty</description>
            </field>
            <field>
              <name>SDI_CTRL_TX_FULL</name>
              <bitRange>[27:27]</bitRange>
              <access>read-only</access>
              <description>TX FIFO full</description>
            </field>
            <field>
              <name>SDI_CTRL_CS_ACTIVE</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>Chip-select line is active when set</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>RX/TX data register</description>
          <addressOffset>0x04</addressOffset>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>SDI_DATA</name>
              <bitRange>[7:0]</bitRange>
              <description>RX data / TX data (via FIFOs)</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- SLINK                                                            -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>SLINK</name>
      <description>Stream Link Interface</description>
      <baseAddress>0xFFEC0000</baseAddress>

      <interrupt><name>SLINK_FIRQ</name><value>14</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x10</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>SLINK_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>SLINK enable flag</description>
            </field>
            <field>
              <name>SLINK_CTRL_RX_EMPTY</name>
              <bitRange>[8:8]</bitRange>
              <access>read-only</access>
              <description>RX FIFO empty</description>
            </field>
            <field>
              <name>SLINK_CTRL_RX_FULL</name>
              <bitRange>[9:9]</bitRange>
              <access>read-only</access>
              <description>RX FIFO full</description>
            </field>
            <field>
              <name>SLINK_CTRL_TX_EMPTY</name>
              <bitRange>[10:10]</bitRange>
              <access>read-only</access>
              <description>TX FIFO empty</description>
            </field>
            <field>
              <name>SLINK_CTRL_TX_FULL</name>
              <bitRange>[11:11]</bitRange>
              <access>read-only</access>
              <description>TX FIFO full</description>
            </field>
            <field>
              <name>SLINK_CTRL_RX_LAST</name>
              <bitRange>[12:12]</bitRange>
              <description>RX link end-of-stream delimiter</description>
            </field>
            <field>
              <name>SLINK_CTRL_IRQ_RX_NEMPTY</name>
              <bitRange>[16:16]</bitRange>
              <description>Interrupt if RX FIFO not empty</description>
            </field>
            <field>
              <name>SLINK_CTRL_IRQ_RX_FULL</name>
              <bitRange>[17:17]</bitRange>
              <description>Interrupt if RX FIFO full</description>
            </field>
            <field>
              <name>SLINK_CTRL_IRQ_TX_EMPTY</name>
              <bitRange>[18:18]</bitRange>
              <description>Interrupt if TX FIFO empty</description>
            </field>
            <field>
              <name>SLINK_CTRL_IRQ_TX_NFULL</name>
              <bitRange>[19:19]</bitRange>
              <description>Interrupt if TX FIFO not full</description>
            </field>
            <field>
              <name>SLINK_CTRL_RX_FIFO</name>
              <bitRange>[27:24]</bitRange>
              <access>read-only</access>
              <description>log2(RX FIFO size)</description>
            </field>
            <field>
              <name>SLINK_CTRL_TX_FIFO</name>
              <bitRange>[31:28]</bitRange>
              <access>read-only</access>
              <description>log2(TX FIFO size)</description>
            </field>
          </fields>
        </register>
        <register>
          <name>ROUTE</name>
          <description>Routing information</description>
          <addressOffset>0x04</addressOffset>
          <fields>
            <field>
              <name>SLINK_ROUTE</name>
              <bitRange>[3:0]</bitRange>
              <description>RX/TX stream source/destination address/ID</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>RX/TX data register</description>
          <addressOffset>0x08</addressOffset>
          <readAction>modify</readAction>
        </register>
        <register>
          <name>DATA_LAST</name>
          <description>TX data register (plus TX end-of-stream delimiter)</description>
          <addressOffset>0x0c</addressOffset>
          <readAction>modify</readAction>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- DMA                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>DMA</name>
      <description>Direct memory access controller</description>
      <baseAddress>0xFFED0000</baseAddress>

      <interrupt><name>DMA_FIRQ</name><value>10</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x10</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control and status register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>DMA_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>DMA enable flag</description>
            </field>
            <field>
              <name>DMA_CTRL_START</name>
              <bitRange>[1:1]</bitRange>
              <access>write-only</access>
              <description>Start programmed DMA transfer(s)</description>
            </field>
            <field>
              <name>DMA_CTRL_FIFO</name>
              <bitRange>[19:16]</bitRange>
              <access>read-only</access>
              <description>log2(descriptor FIFO depth)</description>
            </field>
            <field>
              <name>DMA_CTRL_ACK</name>
              <bitRange>[26:26]</bitRange>
             <access>write-only</access>
              <description>Write 1 to clear ERROR and DONE flags</description>
            </field>
            <field>
              <name>DMA_CTRL_DEMPTY</name>
              <bitRange>[27:27]</bitRange>
              <access>read-only</access>
              <description>Descriptor FIFO is empty</description>
            </field>
            <field>
              <name>DMA_CTRL_DFULL</name>
              <bitRange>[28:28]</bitRange>
              <access>read-only</access>
              <description>Descriptor FIFO is full</description>
            </field>
            <field>
              <name>DMA_CTRL_ERROR</name>
              <bitRange>[29:29]</bitRange>
              <access>read-only</access>
              <description>Error during last transfer</description>
            </field>
            <field>
              <name>DMA_CTRL_DONE</name>
              <bitRange>[30:30]</bitRange>
              <access>read-only</access>
              <description>Transfer(s) done</description>
            </field>
            <field>
              <name>DMA_CTRL_BUSY</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>Transfer(s) in progress</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DESC</name>
          <description>Descriptor FIFO</description>
          <access>write-only</access>
          <addressOffset>0x04</addressOffset>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- PWM                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>PWM</name>
      <description>Pulse-width modulation controller</description>
      <baseAddress>0xFFF00000</baseAddress>

      <addressBlock>
        <offset>0</offset>
        <size>0x100</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>ENABLE</name>
          <description>Channel enable</description>
          <addressOffset>0x00</addressOffset>
        </register>
        <register>
          <name>POLARITY</name>
          <description>Channel polarity</description>
          <addressOffset>0x04</addressOffset>
        </register>
        <register>
          <name>CLKPRSC</name>
          <description>Clock prescaler select</description>
          <addressOffset>0x08</addressOffset>
        </register>
        <register>
          <name>MODE</name>
          <description>Channel operation mode (0 = fast-PWM; 1 = phase-correct PWM)</description>
          <addressOffset>0x0C</addressOffset>
        </register>
        <cluster>
          <dim>32</dim>
          <dimIncrement>0x04</dimIncrement>
          <addressOffset>0x80</addressOffset>
          <name>CHANNEL[%s]</name>
          <description>Channel configuration register</description>
          <register>
            <name>TOPCMP</name>
            <description>Channel counter full word access alias</description>
            <addressOffset>0x0</addressOffset>
            <fields>
              <field>
                <name>CMP</name>
                <bitRange>[15:0]</bitRange>
                <description>Channel counter compare value</description>
              </field>
              <field>
                <name>TOP</name>
                <bitRange>[31:16]</bitRange>
                <description>Channel counter top/wrap value</description>
              </field>
            </fields>
          </register>
        </cluster>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- GPTMR                                                            -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>GPTMR</name>
      <description>General purpose timer</description>
      <baseAddress>0xFFF10000</baseAddress>

      <interrupt><name>GPTMR_FIRQ</name><value>12</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x100</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CSR0</name>
          <description>Control and status register 0</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>ENABLE</name>
              <bitRange>[15:0]</bitRange>
              <description>Per-slice enable bit</description>
            </field>
            <field>
              <name>MODE</name>
              <bitRange>[31:16]</bitRange>
              <description>Per-slice mode bit (0 = single-shot mode, 1 = continuous mode)</description>
            </field>
          </fields>
        </register>
        <register>
          <name>CSR1</name>
          <description>Control and status register 1</description>
          <addressOffset>0x04</addressOffset>
          <fields>
            <field>
              <name>IRQ</name>
              <bitRange>[15:0]</bitRange>
              <description>Per-slice interrupt-pending bit; write 0 to clear</description>
            </field>
            <field>
              <name>PRSC</name>
              <bitRange>[18:16]</bitRange>
              <description>Global clock prescaler select</description>
            </field>
          </fields>
        </register>
        <cluster>
          <dim>16</dim>
          <dimIncrement>0x08</dimIncrement>
          <addressOffset>0x80</addressOffset>
          <name>SLICE[%s]</name>
          <description>Timer slice</description>
          <register>
            <name>CNT</name>
            <description>Counter register</description>
            <addressOffset>0x00</addressOffset>
          </register>
          <register>
            <name>THR</name>
            <description>Threshold register</description>
            <addressOffset>0x04</addressOffset>
          </register>
        </cluster>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- ONEWIRE                                                          -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>ONEWIRE</name>
      <description>1-Wire Interface Controller</description>
      <baseAddress>0xFFF20000</baseAddress>

      <interrupt><name>ONEWIRE_FIRQ</name><value>13</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>ONEWIRE_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>ONEWIRE controller enable</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_CLEAR</name>
              <bitRange>[1:1]</bitRange>
              <access>write-only</access>
              <description>Clear RXT FIFO, auto-clears</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_PRSC</name>
              <bitRange>[3:2]</bitRange>
              <description>Clock prescaler select</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_CLKDIV</name>
              <bitRange>[11:4]</bitRange>
              <description>Clock divider</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_FIFO</name>
              <bitRange>[18:15]</bitRange>
              <access>read-only</access>
              <description>log2(ONEWIRE FIFO size)</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_TX_FULL</name>
              <bitRange>[28:28]</bitRange>
              <access>read-only</access>
              <description>TX FIFO full</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_RX_AVAIL</name>
              <bitRange>[29:29]</bitRange>
              <access>read-only</access>
              <description>RX FIFO data available</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_SENSE</name>
              <bitRange>[30:30]</bitRange>
              <access>read-only</access>
              <description>Current state of the 1-wire bus line</description>
            </field>
            <field>
              <name>ONEWIRE_CTRL_BUSY</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>Operation in progress when set</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DCMD</name>
          <description>Read/write transmission data/command register</description>
          <addressOffset>0x04</addressOffset>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>ONEWIRE_DCMD_DATA</name>
              <bitRange>[7:0]</bitRange>
              <description>RTX data, transmitted LSB-first</description>
            </field>
            <field>
              <name>ONEWIRE_DCMD_CMD</name>
              <bitRange>[9:8]</bitRange>
              <access>write-only</access>
              <description>Operation command</description>
            </field>
            <field>
              <name>ONEWIRE_DCMD_PRESENCE</name>
              <bitRange>[10:10]</bitRange>
              <access>read-only</access>
              <description>Bus presence detected</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- CLINT                                                            -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>CLINT</name>
      <description>Core local interruptor</description>
      <baseAddress>0xFFF40000</baseAddress>

      <addressBlock>
        <offset>0</offset>
        <size>0x10000</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>MSWI0</name>
          <description>Machine software interrupt; hart 0</description>
          <addressOffset>0x0000</addressOffset>
        </register>
        <register>
          <name>MTIMECMP0_LOW</name>
          <description>Machine timer compare low word; hart0</description>
          <addressOffset>0x4000</addressOffset>
        </register>
        <register>
          <name>MTIMECMP0_HI</name>
          <description>Machine timer compare low word; hart0</description>
          <addressOffset>0x4004</addressOffset>
        </register>
        <register>
          <name>MTIME_LOW</name>
          <description>Machine timer low word</description>
          <addressOffset>0xbff8</addressOffset>
        </register>
        <register>
          <name>MTIME_HI</name>
          <description>Machine timer high word</description>
          <addressOffset>0xbffc</addressOffset>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- UART0                                                            -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>UART0</name>
      <description>Primary universal asynchronous receiver and transmitter</description>
      <baseAddress>0xFFF50000</baseAddress>

      <interrupt><name>UART0_FIRQ</name><value>2</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>UART_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>UART enable flag</description>
            </field>
            <field>
              <name>UART_CTRL_SIM_MODE</name>
              <bitRange>[1:1]</bitRange>
              <description>Simulation output override enable, for use in simulation only</description>
            </field>
            <field>
              <name>UART_CTRL_HWFC_EN</name>
              <bitRange>[2:2]</bitRange>
              <description>Enable RTS/CTS hardware flow-control</description>
            </field>
            <field>
              <name>UART_CTRL_PRSC</name>
              <bitRange>[5:3]</bitRange>
              <description>CLock prescaler select</description>
            </field>
            <field>
              <name>UART_CTRL_BAUD</name>
              <bitRange>[15:6]</bitRange>
              <description>BAUD rate divisor</description>
            </field>
            <field>
              <name>UART_CTRL_RX_NEMPTY</name>
              <bitRange>[16:16]</bitRange>
              <access>read-only</access>
              <description>RX FIFO not empty</description>
            </field>
            <field>
              <name>UART_CTRL_RX_FULL</name>
              <bitRange>[17:17]</bitRange>
              <access>read-only</access>
              <description>RX FIFO full</description>
            </field>
            <field>
              <name>UART_CTRL_TX_EMPTY</name>
              <bitRange>[18:18]</bitRange>
              <access>read-only</access>
              <description>TX FIFO empty</description>
            </field>
            <field>
              <name>UART_CTRL_TX_NFULL</name>
              <bitRange>[19:19]</bitRange>
              <access>read-only</access>
              <description>TX FIFO not full</description>
            </field>
            <field>
              <name>UART_CTRL_IRQ_RX_NEMPTY</name>
              <bitRange>[20:20]</bitRange>
              <description>Fire IRQ if RX FIFO not empty</description>
            </field>
            <field>
              <name>UART_CTRL_IRQ_RX_FULL</name>
              <bitRange>[21:21]</bitRange>
              <description>Fire IRQ if RX FIFO full</description>
            </field>
            <field>
              <name>UART_CTRL_IRQ_TX_EMPTY</name>
              <bitRange>[22:22]</bitRange>
              <description>Fire IRQ if TX FIFO empty</description>
            </field>
            <field>
              <name>UART_CTRL_IRQ_TX_NFULL</name>
              <bitRange>[23:23]</bitRange>
              <description>Fire IRQ if TX FIFO not full</description>
            </field>
            <field>
              <name>UART_CTRL_RX_OVER</name>
              <bitRange>[30:30]</bitRange>
              <access>read-only</access>
              <readAction>modify</readAction>
              <description>RX FIFO overflow; clears on CTRL read access</description>
            </field>
            <field>
              <name>UART_CTRL_TX_BUSY</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>Transmitter busy or TX FIFO not empty</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>RTX data register</description>
          <addressOffset>0x04</addressOffset>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>UART_DATA_RTX</name>
              <bitRange>[7:0]</bitRange>
              <description>Receive/transmit data</description>
            </field>
            <field>
              <name>UART_DATA_RX_FIFO</name>
              <bitRange>[11:8]</bitRange>
              <access>read-only</access>
              <description>log2(RX FIFO size)</description>
            </field>
            <field>
              <name>UART_DATA_TX_FIFO</name>
              <bitRange>[15:12]</bitRange>
              <access>read-only</access>
              <description>log2(TX FIFO size)</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- UART1                                                            -->
    <!-- **************************************************************** -->
    <peripheral derivedFrom="UART0">
      <name>UART1</name>
      <description>Secondary universal asynchronous receiver and transmitter</description>
      <baseAddress>0xFFF60000</baseAddress>

      <interrupt><name>UART1_FIRQ</name><value>3</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- SPI                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>SPI</name>
      <description>Serial peripheral interface controller</description>
      <baseAddress>0xFFF80000</baseAddress>

      <interrupt><name>SPI_FIRQ</name><value>6</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>SPI_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>SPI enable flag</description>
            </field>
            <field>
              <name>SPI_CTRL_CPHA</name>
              <bitRange>[1:1]</bitRange>
              <description>Clock phase</description>
            </field>
            <field>
              <name>SPI_CTRL_CPOL</name>
              <bitRange>[2:2]</bitRange>
              <description>Clock polarity</description>
            </field>
            <field>
              <name>SPI_CTRL_PRSC</name>
              <bitRange>[5:3]</bitRange>
              <description>Clock prescaler select</description>
            </field>
            <field>
              <name>SPI_CTRL_CDIV</name>
              <bitRange>[9:6]</bitRange>
              <description>SPI clock divider</description>
            </field>
            <field>
              <name>SPI_CTRL_RX_AVAIL</name>
              <bitRange>[16:16]</bitRange>
              <access>read-only</access>
              <description>RX FIFO data available (RX FIFO not empty)</description>
            </field>
            <field>
              <name>SPI_CTRL_TX_EMPTY</name>
              <bitRange>[17:17]</bitRange>
              <access>read-only</access>
              <description>TX FIFO is empty</description>
            </field>
            <field>
              <name>SPI_CTRL_TX_FULL</name>
              <bitRange>[18:18]</bitRange>
              <access>read-only</access>
              <description>TX FIFO is full</description>
            </field>
            <field>
              <name>SPI_CTRL_FIFO</name>
              <bitRange>[27:24]</bitRange>
              <access>read-only</access>
              <description>log2(FIFO size)</description>
            </field>
            <field>
              <name>SPI_CS_ACTIVE</name>
              <bitRange>[30:30]</bitRange>
              <access>read-only</access>
              <description>Set if a chip-select line is active</description>
            </field>
            <field>
              <name>SPI_CTRL_BUSY</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>SPI busy flag (transmission in progress and TX FIFO not empty)</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>Data register</description>
          <addressOffset>0x04</addressOffset>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>SPI_DATA</name>
              <bitRange>[7:0]</bitRange>
              <description>RX data / TX data/command (via FIFOs)</description>
            </field>
            <field>
              <name>SPI_DATA_CMD</name>
              <bitRange>[31:31]</bitRange>
              <access>write-only</access>
              <description>SPI TX data (0) / command (1) select</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- TWI                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>TWI</name>
      <description>Two-wire interface controller</description>
      <baseAddress>0xFFF90000</baseAddress>

      <interrupt><name>TWI_FIRQ</name><value>7</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>TWI_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>TWI enable flag</description>
            </field>
            <field>
              <name>TWI_CTRL_PRSC</name>
              <bitRange>[3:1]</bitRange>
              <description>Clock prescaler select</description>
            </field>
            <field>
              <name>TWI_CTRL_CDIV</name>
              <bitRange>[7:4]</bitRange>
              <description>TWI clock divider</description>
            </field>
            <field>
              <name>TWI_CTRL_CLKSTR</name>
              <bitRange>[8:8]</bitRange>
              <description>Enable (allow) clock stretching</description>
            </field>
            <field>
              <name>TWI_CTRL_FIFO</name>
              <bitRange>[18:15]</bitRange>
              <access>read-only</access>
              <description>log2(TWI FIFO size)</description>
            </field>
            <field>
              <name>TWI_CTRL_TX_FULL</name>
              <bitRange>[29:29]</bitRange>
              <access>read-only</access>
              <description>TX FIFO full</description>
            </field>
            <field>
              <name>TWI_CTRL_SENSE_SCL</name>
              <bitRange>[27:27]</bitRange>
              <access>read-only</access>
              <description>current state of the SCL bus line</description>
            </field>
            <field>
              <name>TWI_CTRL_SENSE_SDA</name>
              <bitRange>[28:28]</bitRange>
              <access>read-only</access>
              <description>current state of the SDA bus line</description>
            </field>
            <field>
              <name>TWI_CTRL_RX_AVAIL</name>
              <bitRange>[30:30]</bitRange>
              <access>read-only</access>
              <description>RX FIFO not empty (data available)</description>
            </field>
            <field>
              <name>TWI_CTRL_BUSY</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>Bus engine busy of TX FIFO not empty</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DCMD</name>
          <description>RX/TX data/command register</description>
          <addressOffset>0x04</addressOffset>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>TWI_DCMD</name>
              <bitRange>[7:0]</bitRange>
              <description>RX/TX data</description>
            </field>
            <field>
              <name>TWI_DCMD_ACK</name>
              <bitRange>[8:8]</bitRange>
              <description>RX = ACK/NACK, TX = MACK</description>
            </field>
            <field>
              <name>TWI_DCMD_CMD</name>
              <bitRange>[10:9]</bitRange>
              <description>Operation command</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- TWD                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>TWD</name>
      <description>Two-wire device controller</description>
      <baseAddress>0xFFEA0000</baseAddress>

      <interrupt><name>TWD_FIRQ</name><value>4</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>TWD_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>TWD enable flag</description>
            </field>
            <field>
              <name>TWD_CTRL_CLR_RX</name>
              <bitRange>[1:1]</bitRange>
              <access>write-only</access>
              <description>Clear RX FIFO, flag auto-clears</description>
            </field>
            <field>
              <name>TWD_CTRL_CLR_TX</name>
              <bitRange>[2:2]</bitRange>
              <access>write-only</access>
              <description>Clear TX FIFO, flag auto-clears</description>
            </field>
            <field>
              <name>TWD_CTRL_FSEL</name>
              <bitRange>[3:3]</bitRange>
              <description>Bus sample clock / filter select</description>
            </field>
            <field>
              <name>TWD_CTRL_DEV_ADDR</name>
              <bitRange>[10:4]</bitRange>
              <description>Device address (7-bit)</description>
            </field>
            <field>
              <name>TWD_CTRL_IRQ_RX_AVAIL</name>
              <bitRange>[11:11]</bitRange>
              <description>IRQ if RX FIFO data available</description>
            </field>
            <field>
              <name>TWD_CTRL_IRQ_RX_FULL</name>
              <bitRange>[12:12]</bitRange>
              <description>IRQ if RX FIFO full</description>
            </field>
            <field>
              <name>TWD_CTRL_IRQ_TX_EMPTY</name>
              <bitRange>[13:13]</bitRange>
              <description>IRQ if TX FIFO empty</description>
            </field>
            <field>
              <name>TWD_CTRL_IRQ_TX_NFULL</name>
              <bitRange>[14:14]</bitRange>
              <description>IRQ if TX FIFO is not full</description>
            </field>
            <field>
              <name>TWD_CTRL_IRQ_COM_BEG</name>
              <bitRange>[15:15]</bitRange>
              <description>IRQ if begin of communication</description>
            </field>
            <field>
              <name>TWD_CTRL_IRQ_COM_END</name>
              <bitRange>[16:16]</bitRange>
              <description>IRQ if end of communication</description>
            </field>
            <field>
              <name>TWD_CTRL_RX_FIFO</name>
              <bitRange>[20:17]</bitRange>
              <access>read-only</access>
              <description>log2(TWD RX FIFO size)</description>
            </field>
            <field>
              <name>TWD_CTRL_TX_FIFO</name>
              <bitRange>[24:21]</bitRange>
              <access>read-only</access>
              <description>log2(TWD TX FIFO size)</description>
            </field>
            <field>
              <name>TWD_CTRL_RX_AVAIL</name>
              <bitRange>[25:25]</bitRange>
              <access>read-only</access>
              <description>RX FIFO data available</description>
            </field>
            <field>
              <name>TWD_CTRL_RX_FULL</name>
              <bitRange>[26:26]</bitRange>
              <access>read-only</access>
              <description>RX FIFO full</description>
            </field>
            <field>
              <name>TWD_CTRL_TX_EMPTY</name>
              <bitRange>[27:27]</bitRange>
              <access>read-only</access>
              <description>TX FIFO empty</description>
            </field>
            <field>
              <name>TWD_CTRL_TX_FULL</name>
              <bitRange>[28:28]</bitRange>
              <access>read-only</access>
              <description>TX FIFO full</description>
            </field>
            <field>
              <name>TWD_CTRL_COM_BEG</name>
              <bitRange>[29:29]</bitRange>
              <description>communication has started; clear by writing 1</description>
            </field>
            <field>
              <name>TWD_CTRL_COM_END</name>
              <bitRange>[30:30]</bitRange>
              <description>communication has ended; clear by writing 1</description>
            </field>
            <field>
              <name>TWD_CTRL_COM</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>active communication</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>RX/TX data register</description>
          <addressOffset>0x04</addressOffset>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>TWI_DATA</name>
              <bitRange>[7:0]</bitRange>
              <description>RX/TX data FIFO access</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- TRNG                                                             -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>TRNG</name>
      <description>True random number generator</description>
      <baseAddress>0xFFFA0000</baseAddress>

      <interrupt><name>TRNG_FIRQ</name><value>15</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control and data register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>TRNG_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>TRNG enable flag</description>
            </field>
            <field>
              <name>TRNG_CTRL_FIFO_CLR</name>
              <bitRange>[1:1]</bitRange>
              <access>write-only</access>
              <description>Clear data FIFO when set (flag auto clears)</description>
            </field>
            <field>
              <name>TRNG_CTRL_SIM_MODE</name>
              <bitRange>[2:2]</bitRange>
              <access>read-only</access>
              <description>TRNG simulation mode (PRNG!) active</description>
            </field>
            <field>
              <name>TRNG_CTRL_AVAIL</name>
              <bitRange>[3:3]</bitRange>
              <access>read-only</access>
              <description>Random data available</description>
            </field>
            <field>
              <name>TRNG_CTRL_FIFO</name>
              <bitRange>[7:4]</bitRange>
              <access>read-only</access>
              <description>log2(TRNG FIFO depth)</description>
            </field>
            <field>
              <name>TRNG_CTRL_NBIT</name>
              <bitRange>[11:8]</bitRange>
              <access>read-only</access>
              <description>log2(number of raw bits) processed for one output byte</description>
            </field>
            <field>
              <name>TRNG_CTRL_NRO</name>
              <bitRange>[19:12]</bitRange>
              <access>read-only</access>
              <description>Total number of ring-oscillators</description>
            </field>
            <field>
              <name>TRNG_CTRL_NINV</name>
              <bitRange>[31:20]</bitRange>
              <access>read-only</access>
              <description>Number of inverters in first ring-oscillator</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>Random data</description>
          <addressOffset>0x04</addressOffset>
          <access>read-only</access>
          <readAction>modify</readAction>
          <fields>
            <field>
              <name>TRNG_DATA</name>
              <bitRange>[7:0]</bitRange>
              <access>read-only</access>
              <description>Random data</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- WDT                                                              -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>WDT</name>
      <description>Watchdog timer</description>
      <baseAddress>0xFFFB0000</baseAddress>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>WDT_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>WDT enable flag</description>
            </field>
            <field>
              <name>WDT_CTRL_LOCK</name>
              <bitRange>[1:1]</bitRange>
              <description>Lock write access to control register, clears on reset only</description>
            </field>
            <field>
              <name>WDT_CTRL_RCAUSE</name>
              <bitRange>[3:2]</bitRange>
              <access>read-only</access>
              <description>Cause of last system reset: 0=external reset, 1=OCD reset, 2=WDT reset, 3=WDT access violation</description>
            </field>
            <field>
              <name>WDT_CTRL_TIMEOUT</name>
              <bitRange>[31:8]</bitRange>
              <description>Timeout value</description>
            </field>
          </fields>
        </register>
        <register>
          <name>RESET</name>
          <description>Watchdog reset register</description>
          <addressOffset>0x04</addressOffset>
          <fields>
            <field>
              <name>WDT_RESET</name>
              <bitRange>[31:0]</bitRange>
              <access>write-only</access>
              <description>Write password to reset/feed the watchdog (0x709D1AB3)</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- GPIO                                                             -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>GPIO</name>
      <description>General purpose input/output port</description>
      <baseAddress>0xFFFC0000</baseAddress>

      <interrupt><name>GPIO_FIRQ</name><value>8</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x20</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>PORT_IN</name>
          <description>Parallel input port</description>
          <addressOffset>0x00</addressOffset>
          <access>read-only</access>
        </register>
        <register>
          <name>PORT_OUT</name>
          <description>Parallel output port</description>
          <addressOffset>0x04</addressOffset>
        </register>
        <register>
          <name>PORT_DIR</name>
          <description>Port direction configuration: 0 = input, 1 = output</description>
          <addressOffset>0x08</addressOffset>
        </register>
        <register>
          <name>IRQ_TYPE</name>
          <description>Interrupt trigger type (level/edge) for each input pin</description>
          <addressOffset>0x10</addressOffset>
        </register>
        <register>
          <name>IRQ_POLARITY</name>
          <description>Interrupt trigger polarity (rising/falling or high/low) for each input pin</description>
          <addressOffset>0x14</addressOffset>
        </register>
        <register>
          <name>IRQ_ENABLE</name>
          <description>Interrupt enable for each input pin</description>
          <addressOffset>0x18</addressOffset>
        </register>
        <register>
          <name>IRQ_PENDING</name>
          <description>Interrupt pending for each input pin; cleared by writing zero</description>
          <addressOffset>0x1C</addressOffset>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- NEOLED                                                           -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>NEOLED</name>
      <description>Smart LED hardware interface</description>
      <baseAddress>0xFFFD0000</baseAddress>

      <interrupt><name>NEOLED_FIRQ</name><value>9</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x10</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>NEOLED_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>NEOLED enable flag</description>
            </field>
            <field>
              <name>NEOLED_CTRL_PRSC</name>
              <bitRange>[3:1]</bitRange>
              <description>Clock prescaler select</description>
            </field>
            <field>
              <name>NEOLED_CTRL_T_TOT</name>
              <bitRange>[8:4]</bitRange>
              <description>pulse-clock ticks per total period bit</description>
            </field>
            <field>
              <name>NEOLED_CTRL_T_0H</name>
              <bitRange>[13:9]</bitRange>
              <description>pulse-clock ticks per ZERO high-time</description>
            </field>
            <field>
              <name>NEOLED_CTRL_T_1H</name>
              <bitRange>[18:14]</bitRange>
              <description>pulse-clock ticks per ONE high-time</description>
            </field>
            <field>
              <name>NEOLED_CTRL_FIFO</name>
              <bitRange>[28:25]</bitRange>
              <access>read-only</access>
              <description>log2(TX FIFO size)</description>
            </field>
            <field>
              <name>NEOLED_CTRL_TX_EMPTY</name>
              <bitRange>[29:29]</bitRange>
              <access>read-only</access>
              <description>TX FIFO is empty</description>
            </field>
            <field>
              <name>NEOLED_CTRL_TX_FULL</name>
              <bitRange>[30:30]</bitRange>
              <access>read-only</access>
              <description>TX FIFO is full</description>
            </field>
            <field>
              <name>NEOLED_CTRL_TX_BUSY</name>
              <bitRange>[31:31]</bitRange>
              <access>read-only</access>
              <description>busy flag</description>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA24</name>
          <description>Send 24-bit data</description>
          <access>write-only</access>
          <addressOffset>0x04</addressOffset>
        </register>
        <register>
          <name>DATA32</name>
          <description>Send 32-bit data</description>
          <access>write-only</access>
          <addressOffset>0x08</addressOffset>
        </register>
        <register>
          <name>STROBE</name>
          <description>Write any value to send STROBE command</description>
          <access>write-only</access>
          <addressOffset>0x0C</addressOffset>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- TRACER                                                           -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>TRACER</name>
      <description>Execution Trace Buffer</description>
      <baseAddress>0xFFF30000</baseAddress>

      <interrupt><name>TRACER_FIRQ</name><value>5</value></interrupt>

      <addressBlock>
        <offset>0</offset>
        <size>0x10</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CTRL</name>
          <description>Control and status register</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>TRACER_CTRL_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>TRACER enable, reset module when 0</description>
            </field>
            <field>
              <name>TRACER_CTRL_HSEL</name>
              <bitRange>[1:1]</bitRange>
              <description>Hart select for tracing</description>
            </field>
            <field>
              <name>TRACER_CTRL_START</name>
              <bitRange>[2:2]</bitRange>
              <access>write-only</access>
              <description>Start tracing, flag always reads as zero</description>
            </field>
            <field>
              <name>TRACER_CTRL_STOP</name>
              <bitRange>[3:3]</bitRange>
              <access>write-only</access>
              <description>Manually stop tracing, flag always reads as zero</description>
            </field>
            <field>
              <name>TRACER_CTRL_RUN</name>
              <bitRange>[4:4]</bitRange>
              <access>read-only</access>
              <description>Tracing in progress when set</description>
            </field>
            <field>
              <name>TRACER_CTRL_AVAIL</name>
              <bitRange>[5:5]</bitRange>
              <access>read-only</access>
              <description>Trace data available when set</description>
            </field>
            <field>
              <name>TRACER_CTRL_IRQ_CLR</name>
              <bitRange>[6:6]</bitRange>
              <access>write-only</access>
              <description>Clear pending interrupt when writing 1</description>
            </field>
            <field>
              <name>TRACER_CTRL_TBM</name>
              <bitRange>[10:7]</bitRange>
              <access>read-only</access>
              <description>log2 of trace buffer depth</description>
            </field>
          </fields>
        </register>
        <register>
          <name>STOP_ADDR</name>
          <description>Stop tracing when reaching this address, set to all-zero to disable auto-stopping</description>
          <addressOffset>0x04</addressOffset>
        </register>
        <register>
          <name>DELTA_SRC</name>
          <access>read-only</access>
          <description>Trace data: delta source address + first-packet bit</description>
          <addressOffset>0x08</addressOffset>
        </register>
        <register>
          <name>DELTA_DST</name>
          <access>read-only</access>
          <readAction>modify</readAction>
          <description>Trace data: delta destination address + trap-entry bit</description>
          <addressOffset>0x0C</addressOffset>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- SMC                                                             -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>SMC</name>
      <description>Serial Memory Controller</description>
      <baseAddress>0xFFEF0000</baseAddress>

      <addressBlock>
        <offset>0</offset>
        <size>0x08</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CSR0</name>
          <description>Control and status register 0</description>
          <addressOffset>0x00</addressOffset>
          <fields>
            <field>
              <name>SMC_CSR0_EN</name>
              <bitRange>[0:0]</bitRange>
              <description>SMC enable, reset module when 0</description>
            </field>
            <field>
              <name>SMC_CSR0_IOEN</name>
              <bitRange>[1:1]</bitRange>
              <description>Enable control of SMC IO pins</description>
            </field>
            <field>
              <name>SMC_CSR0_DUAL</name>
              <bitRange>[3:3]</bitRange>
              <description>Enable dual-chip mode</description>
            </field>
            <field>
              <name>SMC_CSR0_BUSY</name>
              <bitRange>[4:4]</bitRange>
              <access>read-only</access>
              <description>Memory operation in progress when set</description>
            </field>
            <field>
              <name>SMC_CSR0_MSIZE</name>
              <bitRange>[8:7]</bitRange>
              <description>Memory size select</description>
            </field>
            <field>
              <name>SMC_CSR0_CDIV</name>
              <bitRange>[11:9]</bitRange>
              <description>SPI clock divider</description>
            </field>
            <field>
              <name>SMC_CSR0_RWAIT</name>
              <bitRange>[15:12]</bitRange>
              <description>Memory read access dummy/wait cycles</description>
            </field>
            <field>
              <name>SMC_CSR0_RCMD</name>
              <bitRange>[23:16]</bitRange>
              <description>Memory read command</description>
            </field>
            <field>
              <name>SMC_CSR0_WCMD</name>
              <bitRange>[31:24]</bitRange>
              <description>Memory write command</description>
            </field>
          </fields>
        </register>
        <register>
          <name>CSR1</name>
          <description>Control and status register 0</description>
          <addressOffset>0x04</addressOffset>
          <fields>
            <field>
              <name>SMC_CSR1_ICMD0</name>
              <bitRange>[7:0]</bitRange>
              <description>Initialization command 0</description>
            </field>
            <field>
              <name>SMC_CSR1_ICMD1</name>
              <bitRange>[15:8]</bitRange>
              <description>Initialization command 1</description>
            </field>
            <field>
              <name>SMC_CSR1_ICMD2</name>
              <bitRange>[23:16]</bitRange>
              <description>Initialization command 2</description>
            </field>
            <field>
              <name>SMC_CSR1_MEM_BASE</name>
              <bitRange>[31:28]</bitRange>
              <access>read-only</access>
              <description>Memory base address (top 4 bits / 256MB page)</description>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

    <!-- **************************************************************** -->
    <!-- SYSINFO                                                          -->
    <!-- **************************************************************** -->
    <peripheral>
      <name>SYSINFO</name>
      <description>System configuration information memory</description>
      <baseAddress>0xFFFE0000</baseAddress>

      <addressBlock>
        <offset>0</offset>
        <size>0x10</size>
        <usage>registers</usage>
      </addressBlock>

      <registers>
        <register>
          <name>CLK</name>
          <description>Processor clock speed in Hz</description>
          <addressOffset>0x00</addressOffset>
        </register>
        <register>
          <name>MISC</name>
          <description>Miscellaneous system configurations</description>
          <addressOffset>0x04</addressOffset>
          <access>read-only</access>
          <fields>
            <field><name>SYSINFO_MISC_IMEM</name><bitRange>[7:0]</bitRange><description>log2(IMEM size in bytes)</description></field>
            <field><name>SYSINFO_MISC_DMEM</name><bitRange>[15:8]</bitRange><description>log2(DMEM size in bytes)</description></field>
            <field><name>SYSINFO_MISC_HART</name><bitRange>[19:16]</bitRange><description>Number of physical CPU cores</description></field>
            <field><name>SYSINFO_MISC_BOOT</name><bitRange>[21:20]</bitRange><description>Boot mode configuration select</description></field>
            <field><name>SYSINFO_MISC_ITMO</name><bitRange>[26:22]</bitRange><description>log2(internal bus timeout cycles)</description></field>
            <field><name>SYSINFO_MISC_ETMO</name><bitRange>[31:27]</bitRange><description>log2(external bus timeout cycles)</description></field>
          </fields>
        </register>
        <register>
          <name>SOC</name>
          <description>SoC configuration</description>
          <addressOffset>0x08</addressOffset>
          <access>read-only</access>
          <fields>
            <field><name>SYSINFO_SOC_BOOTLOADER</name><bitRange>[0:0]</bitRange><description>Bootloader implemented</description></field>
            <field><name>SYSINFO_SOC_XBUS</name><bitRange>[1:1]</bitRange><description>External bus interface implemented</description></field>
            <field><name>SYSINFO_SOC_IMEM</name><bitRange>[2:2]</bitRange><description>Processor-internal instruction memory implemented</description></field>
            <field><name>SYSINFO_SOC_DMEM</name><bitRange>[3:3]</bitRange><description>Processor-internal data memory implemented</description></field>
            <field><name>SYSINFO_SOC_OCD</name><bitRange>[4:4]</bitRange><description>On-chip debugger implemented</description></field>
            <field><name>SYSINFO_SOC_ICACHE</name><bitRange>[5:5]</bitRange><description>Processor-internal instruction cache implemented</description></field>
            <field><name>SYSINFO_SOC_DCACHE</name><bitRange>[6:6]</bitRange><description>Processor-internal data cache implemented</description></field>
            <field><name>SYSINFO_SOC_SCM</name><bitRange>[7:7]</bitRange><description>Serial memory controller implemented</description></field>
            <field><name>SYSINFO_SOC_OCD_AUTH</name><bitRange>[11:11]</bitRange><description>On-chip debugger authentication implemented</description></field>
            <field><name>SYSINFO_SOC_IMEM_ROM</name><bitRange>[12:12]</bitRange><description>Processor-internal instruction memory implemented as pre-initialized ROM</description></field>
            <field><name>SYSINFO_SOC_IO_TWD</name><bitRange>[13:13]</bitRange><description>Two-wire device implemented</description></field>
            <field><name>SYSINFO_SOC_IO_DMA</name><bitRange>[14:14]</bitRange><description>Direct memory access controller implemented</description></field>
            <field><name>SYSINFO_SOC_IO_GPIO</name><bitRange>[15:15]</bitRange><description>General purpose input/output port unit implemented</description></field>
            <field><name>SYSINFO_SOC_IO_CLINT</name><bitRange>[16:16]</bitRange><description>Core local interruptor implemented</description></field>
            <field><name>SYSINFO_SOC_IO_UART0</name><bitRange>[17:17]</bitRange><description>Primary universal asynchronous receiver/transmitter implemented</description></field>
            <field><name>SYSINFO_SOC_IO_SPI</name><bitRange>[18:18]</bitRange><description>Serial peripheral interface implemented</description></field>
            <field><name>SYSINFO_SOC_IO_TWI</name><bitRange>[19:19]</bitRange><description>Two-wire interface implemented</description></field>
            <field><name>SYSINFO_SOC_IO_PWM</name><bitRange>[20:20]</bitRange><description>Pulse-width modulation unit implemented</description></field>
            <field><name>SYSINFO_SOC_IO_WDT</name><bitRange>[21:21]</bitRange><description>Watchdog timer implemented</description></field>
            <field><name>SYSINFO_SOC_IO_CFS</name><bitRange>[22:22]</bitRange><description>Custom functions subsystem implemented</description></field>
            <field><name>SYSINFO_SOC_IO_TRNG</name><bitRange>[23:23]</bitRange><description>True random number generator implemented</description></field>
            <field><name>SYSINFO_SOC_IO_SDI</name><bitRange>[24:24]</bitRange><description>Serial data interface implemented</description></field>
            <field><name>SYSINFO_SOC_IO_UART1</name><bitRange>[25:25]</bitRange><description>Secondary universal asynchronous receiver/transmitter implemented</description></field>
            <field><name>SYSINFO_SOC_IO_NEOLED</name><bitRange>[26:26]</bitRange><description>NeoPixel-compatible smart LED interface implemented</description></field>
            <field><name>SYSINFO_SOC_IO_TRACER</name><bitRange>[27:27]</bitRange><description>Execution tracer implemented</description></field>
            <field><name>SYSINFO_SOC_IO_GPTMR</name><bitRange>[28:28]</bitRange><description>General purpose timer implemented</description></field>
            <field><name>SYSINFO_SOC_IO_SLINK</name><bitRange>[29:29]</bitRange><description>Stream link interface implemented</description></field>
            <field><name>SYSINFO_SOC_IO_ONEWIRE</name><bitRange>[30:30]</bitRange><description>1-wire interface controller implemented</description></field>
            <field><name>SYSINFO_SOC_SIM</name><bitRange>[31:31]</bitRange><description>Set if this is a simulation</description></field>
          </fields>
        </register>
        <register>
          <name>CACHE</name>
          <description>Cache configuration</description>
          <addressOffset>0x0C</addressOffset>
          <access>read-only</access>
          <fields>
            <field><name>SYSINFO_CACHE_BLOCK_SIZE</name><bitRange>[3:0]</bitRange><description>log2(Block size in bytes)</description></field>
            <field><name>SYSINFO_CACHE_I_NUM_BLOCKS</name><bitRange>[7:4]</bitRange><description>log2(Number of i-cache blocks)</description></field>
            <field><name>SYSINFO_CACHE_D_NUM_BLOCKS</name><bitRange>[11:8]</bitRange><description>log2(Number of d-cache blocks)</description></field>
            <field><name>YSINFO_CACHE_UC_BEGIN</name><bitRange>[15:12]</bitRange><description>start of uncache address space (256MB page)</description></field>
            <field><name>SYSINFO_CACHE_BURSTS_EN</name><bitRange>[16:16]</bitRange><description>burst transfers enabled</description></field>
          </fields>
        </register>
      </registers>
    </peripheral>

  </peripherals>
</device>
