/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd.

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#************************************************************
#*            Target file generated by rangen               *
#************************************************************
#*                                                          *
#************************************************************

#*************Following is the generated instructions*****************

.text
.align 6
.global main
main:

      .option norvc
.global reg_access
reg_access:
      li x1,0xffffffff
#read to x10 & write x1 to csr
      csrrw x10,mstatus,x1
#read to x10 & set x1 bit to csr
      csrrs x10,mstatus,x1
#read to x10 & clr x1 bit to csr
      csrrc x10,mstatus,x1
#read to x10      
      csrr x10,mstatus
# write x1 to csr
      csrw mstatus,x1
#set x1 bit to csr
      csrs mstatus,x1
#clr x1 bit to csr
      csrc mstatus,x1
.global imm_access
imm_access:
#read to x10 & write imm to csr
      csrrwi x10,mstatus,0x3
#read to x10 & set imm bit to csr
      csrrsi x10,mstatus,0x3
#read to x10 & clr imm bit to csr
      csrrci x10,mstatus,0x3
#write imm bit to csr
      csrs mstatus,0x1
#set imm bit to csr
      csrs mstatus,0x1
#clr imm bit to csr
      csrc mstatus,0x1
.global TEST_EXIT
TEST_EXIT:
      la x1,__exit
      jr x1
.global TEST_FAIL
TEST_FAIL:
      la x1,__fail
      jr x1
.global TEST_WFI
TEST_WFI:
      wfi
      .option rvc
#******this region is added by generator******

