Skip to content
[Jenkins]Jenkins
log in

Workspace

/ pulpino /
.git
.Xil
ci
doc
fpga
ips
rtl
sw
tb
vsim
.gitignoreSep 7, 2026, 4:18:30 AM34 B
.gitlab-ci.ymlSep 7, 2026, 4:18:30 AM2.53 KiB
build_digilent_arty_a7_100t.tclSep 7, 2026, 4:25:38 AM5.17 KiB
clockInfo.txtSep 7, 2026, 4:26:36 AM375 B
create-archive.pySep 7, 2026, 4:18:30 AM1.54 KiB
digilent_arty_a7_100t.bitSep 7, 2026, 4:27:31 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 7, 2026, 4:26:41 AM16.56 KiB
digilent_arty_a7_control_sets.rptSep 7, 2026, 4:26:40 AM12.95 KiB
digilent_arty_a7_drc.rptSep 7, 2026, 4:27:12 AM2.34 KiB
digilent_arty_a7_io.rptSep 7, 2026, 4:26:40 AM96.81 KiB
digilent_arty_a7_power.rptSep 7, 2026, 4:27:13 AM8.59 KiB
digilent_arty_a7_route_status.rptSep 7, 2026, 4:27:11 AM651 B
digilent_arty_a7_timing.rptSep 7, 2026, 4:27:13 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 7, 2026, 4:26:40 AM3.22 KiB
digilent_arty_a7_utilization_place.rptSep 7, 2026, 4:26:40 AM10.57 KiB
generate-scripts.pySep 7, 2026, 4:18:30 AM2.37 KiB
ips_list.ymlSep 7, 2026, 4:18:30 AM1.24 KiB
LICENSESep 7, 2026, 4:18:30 AM10.15 KiB
processor_ci_defines.vhSep 7, 2026, 4:25:38 AM300 B
README.mdSep 7, 2026, 4:18:30 AM7.75 KiB
update-ips.pySep 7, 2026, 4:18:30 AM2.87 KiB