\section{I$^\text{2}$C}

I$^\text{2}$C is an open-drain signaling protocol, meaning that the pad output
driver will be switched on and off, while always driving a low value when
enabled. Logic high values are achieved by using a pull-up resistor on the
\signal{SDA} and \signal{SCL} lines.

\begin{table}[H]
 \caption{I$^\text{2}$C Signals}
 \label{tab:i2c_signals}
  \begin{tabularx}{\textwidth}{@{}llX@{}} \toprule
    \textbf{Signal}                  & \textbf{Direction} & \textbf{Description}        \\ \toprule
    \signal{scl\_pad\_i}             & \textbf{input}     & SCL Input                   \\ \hline
    \signal{scl\_pad\_o}             & \textbf{output}    & SCL Output (always 0)       \\ \hline
    \signal{scl\_padoen\_o}          & \textbf{output}    & SCL Pad Direction           \\ \hline
    \signal{sda\_pad\_i}             & \textbf{input}     & SDA Input                   \\ \hline
    \signal{sda\_pad\_o}             & \textbf{output}    & SDA Output (always 0)       \\ \hline
    \signal{sda\_padoen\_o}          & \textbf{output}    & SDA Pad Direction           \\ \hline
    \signal{interrupt\_o}            & \textbf{output}    & Event/Interrupt             \\ \hline
  \end{tabularx}
\end{table}

\regDesc{0x1A10\_5000}{0x0000\_0000}{CPR (Clock Prescale Register)}{
  \begin{bytefield}[rightcurly=.,endianness=big]{32}
  \bitheader{31,15,0} \\
  \begin{rightwordgroup}{CPR}
    \bitbox{16}{unused}
    \bitbox{16}{PRE}
  \end{rightwordgroup}\\
  \end{bytefield}
}{
  \regItem{Bit 15:0}{PRE}{Prescaler.\\
    Sets the clock prescaler by the value in PRE to
    achieve the desired I$^\text{2}$C clock by dividing the current system clock by the
    given factor.}
}


\regDesc{0x1A10\_5004}{0x0000\_0000}{CTRL (Control Register)}{
  \begin{bytefield}[rightcurly=.,endianness=big]{32}
  \bitheader{31,15,0} \\
  \begin{rightwordgroup}{CTRL}
    \bitbox{24}{unused}
    \bitbox{1}{\rotatebox{90}{\tiny EN}}
    \bitbox{1}{\rotatebox{90}{\tiny IE}}
    \bitbox{1}{-}
    \bitbox{1}{-}
    \bitbox{1}{-}
    \bitbox{1}{-}
    \bitbox{1}{-}
    \bitbox{1}{-}
  \end{rightwordgroup}\\
  \end{bytefield}
}{
  \regItem{Bit 7}{EN}{Enable.\\
  Enable the I$^\text{2}$C peripheral.}
  \regItem{Bit 6}{IE}{Interrupt enable.\\
  Enable interrupts.}
  \regItem{Bit 5:0}{Reserved}{Set to 0.}
}



\regDesc{0x1A10\_5008}{0x0000\_0000}{TX (Transmit Register)}{
  \begin{bytefield}[rightcurly=.,endianness=big]{32}
  \bitheader{31,15,0} \\
  \begin{rightwordgroup}{TX}
    \bitbox{24}{unused}
    \bitbox{8}{TX}
  \end{rightwordgroup}\\
  \end{bytefield}
}{
  \regItem{Bit 7:0}{TX}{Transmit Register}
}


\regDesc{0x1A10\_500C}{0x0000\_0000}{RX (Receive Register)}{
  \begin{bytefield}[rightcurly=.,endianness=big]{32}
  \bitheader{31,15,0} \\
  \begin{rightwordgroup}{TX}
    \bitbox{24}{unused}
    \bitbox{8}{RX}
  \end{rightwordgroup} \\
  \end{bytefield}
}
{
  \regItem{Bit 7:0}{RX}{Receive Register}
}


\regDesc{0x1A10\_5010}{0x0000\_0000}{CMD (Command Register)}{
  \begin{bytefield}[rightcurly=.,endianness=big]{32}
  \bitheader{31,15,0} \\
  \begin{rightwordgroup}{CMD}
    \bitbox{24}{unused}
    \bitbox{1}{\rotatebox{90}{\small \tiny STA}}
    \bitbox{1}{\rotatebox{90}{\small \tiny STO}}
    \bitbox{1}{\rotatebox{90}{\small \tiny RD}}
    \bitbox{1}{\rotatebox{90}{\small \tiny WR}}
    \bitbox{1}{\rotatebox{90}{\small \tiny ACK}}
    \bitbox{1}{0}
    \bitbox{1}{0}
    \bitbox{1}{\rotatebox{90}{\small \tiny IA}}
  \end{rightwordgroup}\\
  \end{bytefield}
}{
  \regItem{Bit 7}{STA}{Send start bit.}
  \regItem{Bit 6}{STO}{Send stop bit.}
  \regItem{Bit 5}{RD}{Read from bus.}
  \regItem{Bit 4}{WR}{Write to bus.}
  \regItem{Bit 3}{ACK}{Acknowledge received data.}
  \regItem{Bit 2:1}{Reserved}{Set to 0.}
  \regItem{Bit 0}{IA}{Interrupt Acknowldge.\\
    Set to one to acknowledge interrupt.
    Cleared when transmission is done or arbitration is lost.}
}


\regDesc{0x1A10\_5014}{0x0000\_0000}{STATUS (Status Register)}{
  \begin{bytefield}[rightcurly=.,endianness=big]{32}
  \bitheader{31,15,0} \\
  \begin{rightwordgroup}{STATUS}
    \bitbox{24}{unused}
    \bitbox{1}{\rotatebox{90}{\small \tiny RXA}}
    \bitbox{1}{\rotatebox{90}{\small \tiny BUS}}
    \bitbox{1}{\rotatebox{90}{\small \tiny AL}}
    \bitbox{1}{0}
    \bitbox{1}{0}
    \bitbox{1}{0}
    \bitbox{1}{\rotatebox{90}{\small \tiny TIP}}
    \bitbox{1}{\rotatebox{90}{\small \tiny IRQ}}
  \end{rightwordgroup}\\
  \end{bytefield}
}{
  \regItem{Bit 7}{RXA}{Acknowledge from sent data.}
  \regItem{Bit 6}{BUS}{Bus is busy.}
  \regItem{Bit 5}{AL}{Arbitration lost.}
  \regItem{Bit 4:2}{Reserved}{Set to 0.}
  \regItem{Bit 1}{TIP}{Transfer in progress.}
  \regItem{Bit 0}{IRQ}{Interrupt received.\\
    This flag is always set when transmission has finished or bus arpitration
  was lostm, regardless of whether interrupts are enabled or not. This flag can
possibly polled and is cleared by writing 1 to the IA command register.}
}

