/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Wed Sep 16 09:21:10 2015
*/


/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "pl.dtsi"
/ {
	cpus {
		cpu@0 {
			operating-points = <666666 1000000 333333 1000000>;
		};
	};
	chosen {
		bootargs = "console=ttyPS1,115200 ip=on root=/dev/mmcblk0p2 rw earlyprintk";
	};
	aliases {
		ethernet0 = &gem0;
		serial0 = &uart0;
		serial1 = &uart1;
	};
	memory {
		device_type = "memory";
		reg = <0x0 0x20000000>;
	};
};
&gem0 {
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";
	xlnx,ptp-enet-clock = <0x69f6bcb>;
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: phy@7 {
			compatible = "marvell,88e1116r";
			device_type = "ethernet-phy";
			reg = <0>;
		};
	};
};
&gpio0 {
	emio-gpio-width = <64>;
	gpio-mask-high = <0x0>;
	gpio-mask-low = <0x5600>;
};
&intc {
	num_cpus = <2>;
	num_interrupts = <96>;
};
&qspi {
	is-dual = <0>;
	num-cs = <1>;
	status = "okay";
};
&sdhci0 {
	clock-frequency = <50000000>;
	status = "okay";
};
&uart1 {
	current-speed = <115200>;
	device_type = "serial";
	port-number = <1>;
	status = "okay";
};
&usb0 {
	dr_mode = "host";
	phy_type = "ulpi";
	status = "okay";
};
&clkc {
	fclk-enable = <0xf>;
	ps-clk-frequency = <33333333>;
};
&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
	device@0 {
		compatible = "spidev";
		reg = <0>;  // Chip select 0
		spi-max-frequency = <500000>;
		spi-cpol = <0x0>;
		spi-cpha = <0x0>;
	};
};
&uart0 {
	current-speed = <115200>;
	device_type = "serial";
	port-number = <0>;
	status = "okay";
};
