Skip to content
[Jenkins]Jenkins
log in

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesAug 22, 2026, 1:18:03 AM66 B
build_digilent_arty_a7_100t.tclAug 22, 2026, 1:21:07 AM3.39 KiB
clockInfo.txtAug 22, 2026, 1:23:08 AM375 B
diagram.pngAug 22, 2026, 1:18:03 AM57.29 KiB
digilent_arty_a7_100t.bitAug 22, 2026, 1:24:24 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 22, 2026, 1:23:21 AM23.58 KiB
digilent_arty_a7_control_sets.rptAug 22, 2026, 1:23:20 AM26.53 KiB
digilent_arty_a7_drc.rptAug 22, 2026, 1:24:02 AM2.34 KiB
digilent_arty_a7_io.rptAug 22, 2026, 1:23:20 AM96.81 KiB
digilent_arty_a7_power.rptAug 22, 2026, 1:24:04 AM9.05 KiB
digilent_arty_a7_route_status.rptAug 22, 2026, 1:24:00 AM651 B
digilent_arty_a7_timing.rptAug 22, 2026, 1:24:02 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 22, 2026, 1:23:20 AM6.36 KiB
digilent_arty_a7_utilization_place.rptAug 22, 2026, 1:23:20 AM10.65 KiB
LICENSEAug 22, 2026, 1:18:03 AM11.06 KiB
processor_ci_defines.vhAug 22, 2026, 1:21:07 AM300 B
README.mdAug 22, 2026, 1:18:03 AM3.88 KiB