# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore

mul:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      mul: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

mulh:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      mulh: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

mulhu:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      mulhu: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

mulhsu:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      mulhsu: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

div:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      div: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

divu:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      divu: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

rem:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      rem: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]

remu:
    config: 
      - check ISA:=regex(.*I.*M.*)
    opcode: 
      remu: 0
    rs1: 
      <<: *all_regs
    rs2: 
      <<: *all_regs
    rd: 
      <<: *all_regs
    op_comb: 
      <<: *rfmt_op_comb
    val_comb:
      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
      abstract_comb:
        'sp_dataset(xlen)': 0
        <<: [*rs1val_walking, *rs2val_walking]
