# Copyright Imperas Software Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http:#www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

Device: rv32imc
Vendor: ibex

ISA: RV32IMC
misa:
  implemented: True
  MXL:
    range:
      rangelist: [[1]]
      mode: Unchanged
  Extensions:
    bitmask:
      mask: 0x0
      default: 0x1104
hw_data_misaligned_support: True
mtvec:
  MODE:
    range:
      rangelist: [[1]]
  BASE:
    range:
      rangelist: [[0x20000020]]

mstatus:
  MPP:
    range:
      rangelist: [[3]]

User_Spec_Version: "2.3"
Privilege_Spec_Version: "1.11"

mvendorid:
  implemented: false
marchid:
  implemented: false
mimpid:
  implemented: false
mhartid: 0

mcycle:
  is_hardwired: true
  implemented: true
minstret:
  is_hardwired: true
  implemented: true

## dont know how to put these in the yaml
# --override riscvOVPsim/cpu/tvec_align=0

## and then we really need to be able to put in these in the config file...:
# --override riscvOVPsim/cpu/addrbits=32 
# --override riscvOVPsim/cpu/wfi_is_nop=F
# --override riscvOVPsim/cpu/tval_ii_code=T

## questions
## if misa Extensions bitmask mask is left out... the yaml defaults to zero... ovpsim does not

