
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Wed Dec 16 04:49:48 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64ic.cgf') \
//                  -- xlen 64 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lwsp instruction of the RISC-V C extension for the clwsp covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*C.*);def TEST_CASE_1=True;",clwsp)

RVTEST_SIGBASE( x8,signature_x8_1)

inst_0:
// rd==x1, imm_val > 0, 
// opcode: c.lwsp; op1:x2; dest:x1; immval:0x18
TEST_LOAD(x8,x12,0,x2,x1,0x18,0,c.lwsp,0)

inst_1:
// rd==x24, imm_val == 0, 
// opcode: c.lwsp; op1:x2; dest:x24; immval:0x0
TEST_LOAD(x8,x12,0,x2,x24,0x0,8,c.lwsp,0)

inst_2:
// rd==x22, imm_val == 4, 
// opcode: c.lwsp; op1:x2; dest:x22; immval:0x4
TEST_LOAD(x8,x12,0,x2,x22,0x4,16,c.lwsp,0)

inst_3:
// rd==x18, imm_val == 8, 
// opcode: c.lwsp; op1:x2; dest:x18; immval:0x8
TEST_LOAD(x8,x12,0,x2,x18,0x8,24,c.lwsp,0)

inst_4:
// rd==x16, imm_val == 16, 
// opcode: c.lwsp; op1:x2; dest:x16; immval:0x10
TEST_LOAD(x8,x12,0,x2,x16,0x10,32,c.lwsp,0)

inst_5:
// rd==x23, imm_val == 32, 
// opcode: c.lwsp; op1:x2; dest:x23; immval:0x20
TEST_LOAD(x8,x12,0,x2,x23,0x20,40,c.lwsp,0)

inst_6:
// rd==x6, imm_val == 64, 
// opcode: c.lwsp; op1:x2; dest:x6; immval:0x40
TEST_LOAD(x8,x12,0,x2,x6,0x40,48,c.lwsp,0)

inst_7:
// rd==x2, imm_val == 128, 
// opcode: c.lwsp; op1:x2; dest:x2; immval:0x80
TEST_LOAD(x8,x12,0,x2,x2,0x80,56,c.lwsp,0)

inst_8:
// rd==x10, imm_val == 248, 
// opcode: c.lwsp; op1:x2; dest:x10; immval:0xf8
TEST_LOAD(x8,x12,0,x2,x10,0xf8,64,c.lwsp,0)

inst_9:
// rd==x5, imm_val == 244, 
// opcode: c.lwsp; op1:x2; dest:x5; immval:0xf4
TEST_LOAD(x8,x12,0,x2,x5,0xf4,72,c.lwsp,0)

inst_10:
// rd==x7, imm_val == 236, 
// opcode: c.lwsp; op1:x2; dest:x7; immval:0xec
TEST_LOAD(x8,x12,0,x2,x7,0xec,80,c.lwsp,0)

inst_11:
// rd==x31, imm_val == 220, 
// opcode: c.lwsp; op1:x2; dest:x31; immval:0xdc
TEST_LOAD(x8,x12,0,x2,x31,0xdc,88,c.lwsp,0)

inst_12:
// rd==x26, imm_val == 188, 
// opcode: c.lwsp; op1:x2; dest:x26; immval:0xbc
TEST_LOAD(x8,x12,0,x2,x26,0xbc,96,c.lwsp,0)

inst_13:
// rd==x28, imm_val == 124, 
// opcode: c.lwsp; op1:x2; dest:x28; immval:0x7c
TEST_LOAD(x8,x12,0,x2,x28,0x7c,104,c.lwsp,0)

inst_14:
// rd==x21, imm_val == 84, 
// opcode: c.lwsp; op1:x2; dest:x21; immval:0x54
TEST_LOAD(x8,x12,0,x2,x21,0x54,112,c.lwsp,0)

inst_15:
// rd==x30, imm_val == 168, 
// opcode: c.lwsp; op1:x2; dest:x30; immval:0xa8
TEST_LOAD(x8,x12,0,x2,x30,0xa8,120,c.lwsp,0)

inst_16:
// rd==x14, 
// opcode: c.lwsp; op1:x2; dest:x14; immval:0x0
TEST_LOAD(x8,x12,0,x2,x14,0x0,128,c.lwsp,0)

inst_17:
// rd==x13, 
// opcode: c.lwsp; op1:x2; dest:x13; immval:0x0
TEST_LOAD(x8,x12,0,x2,x13,0x0,136,c.lwsp,0)

inst_18:
// rd==x20, 
// opcode: c.lwsp; op1:x2; dest:x20; immval:0x0
TEST_LOAD(x8,x12,0,x2,x20,0x0,144,c.lwsp,0)

inst_19:
// rd==x15, 
// opcode: c.lwsp; op1:x2; dest:x15; immval:0x0
TEST_LOAD(x8,x12,0,x2,x15,0x0,152,c.lwsp,0)

inst_20:
// rd==x9, 
// opcode: c.lwsp; op1:x2; dest:x9; immval:0x0
TEST_LOAD(x8,x12,0,x2,x9,0x0,160,c.lwsp,0)

inst_21:
// rd==x19, 
// opcode: c.lwsp; op1:x2; dest:x19; immval:0x0
TEST_LOAD(x8,x12,0,x2,x19,0x0,168,c.lwsp,0)

inst_22:
// rd==x17, 
// opcode: c.lwsp; op1:x2; dest:x17; immval:0x0
TEST_LOAD(x8,x12,0,x2,x17,0x0,176,c.lwsp,0)

inst_23:
// rd==x11, 
// opcode: c.lwsp; op1:x2; dest:x11; immval:0x0
TEST_LOAD(x8,x12,0,x2,x11,0x0,184,c.lwsp,0)

inst_24:
// rd==x3, 
// opcode: c.lwsp; op1:x2; dest:x3; immval:0x0
TEST_LOAD(x8,x12,0,x2,x3,0x0,192,c.lwsp,0)

inst_25:
// rd==x4, 
// opcode: c.lwsp; op1:x2; dest:x4; immval:0x0
TEST_LOAD(x8,x12,0,x2,x4,0x0,200,c.lwsp,0)

inst_26:
// rd==x25, 
// opcode: c.lwsp; op1:x2; dest:x25; immval:0x0
TEST_LOAD(x8,x12,0,x2,x25,0x0,208,c.lwsp,0)

inst_27:
// rd==x29, 
// opcode: c.lwsp; op1:x2; dest:x29; immval:0x0
TEST_LOAD(x8,x3,0,x2,x29,0x0,216,c.lwsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_28:
// rd==x27, 
// opcode: c.lwsp; op1:x2; dest:x27; immval:0x0
TEST_LOAD(x1,x3,0,x2,x27,0x0,0,c.lwsp,0)

inst_29:
// rd==x12, 
// opcode: c.lwsp; op1:x2; dest:x12; immval:0x0
TEST_LOAD(x1,x3,0,x2,x12,0x0,8,c.lwsp,0)

inst_30:
// rd==x8, 
// opcode: c.lwsp; op1:x2; dest:x8; immval:0x0
TEST_LOAD(x1,x3,0,x2,x8,0x0,16,c.lwsp,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x8_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x8_1:
    .fill 28*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 3*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
