Skip to content

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreJul 29, 2026, 2:41:58 AM30 B
build_digilent_arty_a7_100t.tclJul 29, 2026, 2:44:12 AM3.30 KiB
clockInfo.txtJul 29, 2026, 2:45:43 AM375 B
digilent_arty_a7_100t.bitJul 29, 2026, 2:46:56 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 29, 2026, 2:45:54 AM22.33 KiB
digilent_arty_a7_control_sets.rptJul 29, 2026, 2:45:53 AM18.90 KiB
digilent_arty_a7_drc.rptJul 29, 2026, 2:46:34 AM9.43 KiB
digilent_arty_a7_io.rptJul 29, 2026, 2:45:53 AM96.81 KiB
digilent_arty_a7_power.rptJul 29, 2026, 2:46:36 AM8.74 KiB
digilent_arty_a7_route_status.rptJul 29, 2026, 2:46:33 AM651 B
digilent_arty_a7_timing.rptJul 29, 2026, 2:46:34 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 29, 2026, 2:45:53 AM7.30 KiB
digilent_arty_a7_utilization_place.rptJul 29, 2026, 2:45:53 AM10.74 KiB
LICENSEJul 29, 2026, 2:41:58 AM11.09 KiB
processor_ci_defines.vhJul 29, 2026, 2:44:12 AM300 B
README.mdJul 29, 2026, 2:41:58 AM9.81 KiB
simulation.outJul 29, 2026, 2:42:02 AM201.33 KiB