Skip to content
[Jenkins]Jenkins
log in

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreSep 20, 2026, 2:41:49 AM30 B
build_digilent_arty_a7_100t.tclSep 20, 2026, 2:44:05 AM3.30 KiB
clockInfo.txtSep 20, 2026, 2:45:27 AM375 B
digilent_arty_a7_100t.bitSep 20, 2026, 2:46:40 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 20, 2026, 2:45:40 AM22.33 KiB
digilent_arty_a7_control_sets.rptSep 20, 2026, 2:45:39 AM18.90 KiB
digilent_arty_a7_drc.rptSep 20, 2026, 2:46:19 AM9.43 KiB
digilent_arty_a7_io.rptSep 20, 2026, 2:45:39 AM96.81 KiB
digilent_arty_a7_power.rptSep 20, 2026, 2:46:21 AM8.74 KiB
digilent_arty_a7_route_status.rptSep 20, 2026, 2:46:18 AM651 B
digilent_arty_a7_timing.rptSep 20, 2026, 2:46:20 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 20, 2026, 2:45:39 AM7.30 KiB
digilent_arty_a7_utilization_place.rptSep 20, 2026, 2:45:39 AM10.74 KiB
LICENSESep 20, 2026, 2:41:49 AM11.09 KiB
processor_ci_defines.vhSep 20, 2026, 2:44:05 AM300 B
README.mdSep 20, 2026, 2:41:49 AM9.81 KiB
simulation.outSep 20, 2026, 2:41:53 AM201.33 KiB