Skip to content
[Jenkins]Jenkins
log in

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreSep 10, 2026, 2:42:25 AM30 B
build_digilent_arty_a7_100t.tclSep 10, 2026, 2:44:38 AM3.30 KiB
clockInfo.txtSep 10, 2026, 2:46:02 AM375 B
digilent_arty_a7_100t.bitSep 10, 2026, 2:47:11 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 10, 2026, 2:46:12 AM22.33 KiB
digilent_arty_a7_control_sets.rptSep 10, 2026, 2:46:11 AM18.90 KiB
digilent_arty_a7_drc.rptSep 10, 2026, 2:46:50 AM9.43 KiB
digilent_arty_a7_io.rptSep 10, 2026, 2:46:11 AM96.81 KiB
digilent_arty_a7_power.rptSep 10, 2026, 2:46:51 AM8.74 KiB
digilent_arty_a7_route_status.rptSep 10, 2026, 2:46:48 AM651 B
digilent_arty_a7_timing.rptSep 10, 2026, 2:46:50 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 10, 2026, 2:46:11 AM7.30 KiB
digilent_arty_a7_utilization_place.rptSep 10, 2026, 2:46:11 AM10.74 KiB
LICENSESep 10, 2026, 2:42:25 AM11.09 KiB
processor_ci_defines.vhSep 10, 2026, 2:44:38 AM300 B
README.mdSep 10, 2026, 2:42:25 AM9.81 KiB
simulation.outSep 10, 2026, 2:42:29 AM201.33 KiB