Skip to content

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreJul 25, 2026, 2:41:58 AM30 B
build_digilent_arty_a7_100t.tclJul 25, 2026, 2:44:23 AM3.30 KiB
clockInfo.txtJul 25, 2026, 2:45:53 AM375 B
digilent_arty_a7_100t.bitJul 25, 2026, 2:47:08 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 25, 2026, 2:46:02 AM22.33 KiB
digilent_arty_a7_control_sets.rptJul 25, 2026, 2:46:02 AM18.90 KiB
digilent_arty_a7_drc.rptJul 25, 2026, 2:46:47 AM9.43 KiB
digilent_arty_a7_io.rptJul 25, 2026, 2:46:02 AM96.81 KiB
digilent_arty_a7_power.rptJul 25, 2026, 2:46:48 AM8.74 KiB
digilent_arty_a7_route_status.rptJul 25, 2026, 2:46:45 AM651 B
digilent_arty_a7_timing.rptJul 25, 2026, 2:46:47 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 25, 2026, 2:46:01 AM7.30 KiB
digilent_arty_a7_utilization_place.rptJul 25, 2026, 2:46:01 AM10.74 KiB
LICENSEJul 25, 2026, 2:41:58 AM11.09 KiB
processor_ci_defines.vhJul 25, 2026, 2:44:23 AM300 B
README.mdJul 25, 2026, 2:41:58 AM9.81 KiB
simulation.outJul 25, 2026, 2:42:00 AM201.33 KiB