| .git |
| .Xil |
| fpga |
| pic |
| rtl |
| sim |
| tb |
| tests |
| tmp_venv |
| tools |
| .gitignore | Sep 1, 2026, 2:42:24 AM | 30 B | |
| build_digilent_arty_a7_100t.tcl | Sep 1, 2026, 2:44:46 AM | 3.30 KiB | |
| clockInfo.txt | Sep 1, 2026, 2:46:13 AM | 375 B | |
| digilent_arty_a7_100t.bit | Sep 1, 2026, 2:47:23 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Sep 1, 2026, 2:46:23 AM | 22.33 KiB | |
| digilent_arty_a7_control_sets.rpt | Sep 1, 2026, 2:46:22 AM | 18.90 KiB | |
| digilent_arty_a7_drc.rpt | Sep 1, 2026, 2:47:01 AM | 9.43 KiB | |
| digilent_arty_a7_io.rpt | Sep 1, 2026, 2:46:22 AM | 96.81 KiB | |
| digilent_arty_a7_power.rpt | Sep 1, 2026, 2:47:03 AM | 8.74 KiB | |
| digilent_arty_a7_route_status.rpt | Sep 1, 2026, 2:47:00 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Sep 1, 2026, 2:47:02 AM | 22.74 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Sep 1, 2026, 2:46:22 AM | 7.30 KiB | |
| digilent_arty_a7_utilization_place.rpt | Sep 1, 2026, 2:46:22 AM | 10.74 KiB | |
| LICENSE | Sep 1, 2026, 2:42:24 AM | 11.09 KiB | |
| processor_ci_defines.vh | Sep 1, 2026, 2:44:46 AM | 300 B | |
| README.md | Sep 1, 2026, 2:42:24 AM | 9.81 KiB | |
| simulation.out | Sep 1, 2026, 2:42:25 AM | 201.33 KiB | |
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